U.S. patent application number 11/652639 was filed with the patent office on 2007-06-14 for growth of gaas expitaxial layers on si substrate by using a novel gesi buffer layer.
This patent application is currently assigned to National Chiao-Tung University. Invention is credited to Chun-Yen Chang, Edward Y. Chang, Guangli Luo, Tsung-Hsi Yang.
Application Number | 20070134901 11/652639 |
Document ID | / |
Family ID | 38459830 |
Filed Date | 2007-06-14 |
United States Patent
Application |
20070134901 |
Kind Code |
A1 |
Chang; Edward Y. ; et
al. |
June 14, 2007 |
Growth of GaAs expitaxial layers on Si substrate by using a novel
GeSi buffer layer
Abstract
This invention provides a process for growing Ge epitaixial
layers on Si substrate by using ultra-high vacuum chemical vapor
deposition (UHVCVD), and subsequently growing a GaAs layer on Ge
film of the surface of said Ge epitaixial layers by using metal
organic chemical vapor deposition (MOCVD). The process comprises
steps of, firstly, pre-cleaning a silicon wafer in a standard
cleaning procedure, dipping it with HF solution and prebaking to
remove its native oxide layer. Then, growing a high Ge-composition
epitaixial layer, such as Si.sub.0.1Ge.sub.0.9 in a thickness of
0.8 .mu.m on said Si substrate by using ultra-high vacuum chemical
vapor deposition under certain conditions. Thus, many dislocations
are generated and located near the interface and in the low of part
of S.sub.i0.1Ge.sub.0.9 due to the large mismatch between this
layer and Si substrate. Furthermore, a subsequent 0.8 .mu.m
Si.sub.0.05Ge.sub.0.95 layer, and/or optionally a further 0.8 .mu.m
Si.sub.0.02Ge.sub.0.98 layer, are grown. They form strained
interfaces of said layers can bend and terminate the propagated
upward dislocation very effectively. Therefore, a film of pure Ge
is grown on the surface of said epitaixial layers. Finally, a GaAs
epitaixial layer is grown on said Ge film by using MOCVD.
Inventors: |
Chang; Edward Y.; (Taipei
City, TW) ; Luo; Guangli; (Hsinchu City, TW) ;
Yang; Tsung-Hsi; (Shui Lin Village, TW) ; Chang;
Chun-Yen; (Hsinchu City, TW) |
Correspondence
Address: |
BACON & THOMAS, PLLC
625 SLATERS LANE
FOURTH FLOOR
ALEXANDRIA
VA
22314
US
|
Assignee: |
National Chiao-Tung
University
Hsinchu City
TW
|
Family ID: |
38459830 |
Appl. No.: |
11/652639 |
Filed: |
January 12, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10699839 |
Nov 4, 2003 |
|
|
|
11652639 |
Jan 12, 2007 |
|
|
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Current U.S.
Class: |
438/604 ;
257/E21.12; 257/E21.127 |
Current CPC
Class: |
H01L 21/0262 20130101;
H01L 21/02546 20130101; H01L 21/02381 20130101; H01L 33/0066
20130101; H01L 21/0245 20130101; H01L 21/02505 20130101 |
Class at
Publication: |
438/604 |
International
Class: |
H01L 21/28 20060101
H01L021/28 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 28, 2003 |
TW |
092129501 |
Jul 28, 2003 |
TW |
092129502 |
Claims
1-13. (canceled)
14. The semiconductor structure of SiGe epitaxy, comprising a
silicon substrate, a first SiGe epitaxial layer having Ge content
at least 70 wt. %, a second SiGe epitaxial layer having Ge content
more than that of the first layer, an optional third SiGe epitaxial
layer having Ge content more than that of the second layer, a pure
Ge film, and a GaAs epitaxial layer as the topmost layer,
characterized in that the first SiGe epitaxial layer can
accommodate large dislocations which are generated and located near
in the low part of the first layer and the interface due to the
large lattice mismatch, and the second and/or the third optional
layers can form strained interfaces of said layers to bend and
terminate the propagated upward dislocation very effectively.
15. A semiconductor structure of SiGe eptiaxy, comprising a silicon
substrate, a first SiGe epitaxial layer having Ge content at least
70 wt. %, a second SiGe epitaxial layer having Ge content more than
that of the first layer, an optional third SiGe epitaxial layer
having Ge content more than that of the second layer, a pure Ge
film, and a GaAs epitaxial layer as the topmost layer,
characterized in that the thickness of epitaxial layers totally is
controlled in not exceed to 3.0 .mu.m, and the surface of said
layers is very smooth and without planarization using CMP.
16. A semiconductor structure of SiGe eptiaxy, comprising a silicon
substrate, a first SiGe epitaxial layer having Ge content at least
70 wt. %, a second SiGe epitaxial layer having Ge content more than
that of the first layer, an optional third SiGe epitaxial layer
having Ge content more than that of the second layer, a pure Ge
film, and a GaAs epitaxial layer as the topmost layer,
characterized in that the threading density is not controlled in
not exceed to 10.sup.6/cm.sup.2.
17. The semiconductor structure according to claim 14 is suitable
as high-speed devices and optical devices.
18. The semiconductor structure according to claim 14 is further
suitable as a wafer of Group III-IV material and an integrating
wafer which is used to integrate Group III-IV material and Group IV
material.
19. The semiconductor structure according to claim 15 is suitable
as high-speed devices and optical devices.
20. The semiconductor structure according to claim 16 is suitable
as high-speed devices and optical devices.
21. The semiconductor structure according to claim 15 is further
suitable as a wafer of Group III-IV material and an integrating
wafer which is used to integrate Group III-IV material and Group IV
material.
22. The semiconductor structure according to claim 16 is further
suitable as a wafer of Group III-IV material and an integrating
wafer which is used to integrate Group III-IV material and Group IV
material.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to a process for manufacturing
semiconductor structure or devices, more particular for growing a
high quality Ge film on Si substrate using a novel GeSi buffer
method and additionally growing a high quality Group III-V, such as
GaAs epitaixial layer on the grown Ge/SiGe/Si substrate.
[0003] 2. Description of Related Art
[0004] The growth of high quality GaAs or other III-V compound
semiconductors on silicon substrate is recognized as a desirable
goal for the fabrication of advanced semiconductor devices.
Specific advantages of this combinations of materials include the
availability of GaAs with high electron mobility and optical
activity on a silicon substrate with improved mechanical strength
and thermal conductivity over that obtainable with GaAs substrate.
In addition, the growth of high quality GaAs on silicon offers the
possibility of monolithically integrating GaAs and silicon devices
for advanced electronic components.
[0005] However, one of the key limitations in the implementation of
device structure based on heteroepitaixial GaAs on silicon has a
4.0% difference in lattice constant and additional intrinsic
thermal conductivity difference between the two different
materials. This lattice mismatch leads to the formation of a
network of misfit dislocation at the heterointerface and high
density threading dislocation in the epitaixial layers.
[0006] Presently public techniques to overcome the defects produced
from the growth of GaAs on Si substrate include varying epitaixial
growth conditions for directly growing GaAs epitaxy on Si, applying
strained supper lattices buffer to filter threading dislocation and
using Ge composition graded SiGe layers as buffer.
[0007] For example, the techniques for directly growing GaAs
epitaixial layer on Si, for the purpose of lowering the large
threading dislocation due to lattice mismatch of GaAs on Si
substrate, two steps of annealing methods or strained
super-latticed buffer are previously applied to solve those
problems. Related disclosures include U.S. Pat. No. 5,959,308,
5,879,962, 5,473,174, 5,308,444, 5,438,951, 5,238,869, 5,183,776
and 5,141,893, furthermore, it is reported in "Subpicosecond
carrier dynamics in low-temperature grown GaAs on Si substrates"
(Applied Physics Letters, Vol. 75, No. 17, 25 Oct. 1999) from A. C.
Gossard et al., and in "Growth of high quality gallium arsenide on
HF-etched silicon by chemical beam epitaxy" (Applied Physics
Letters, Vol. 62, No. 14. 5 Apr. 1993) from P. J. Goodhew et al.,
and in "Integration of low-temperature GaAs on Si substrates"
(Applied Physics Letters,Vol. 62, No. 3, 18 Jan. 1993) from T. F.
Carrathers et al. These prior arts have less effects on lowering
the threading dislocation density according to the techniques for
production from the directly growing GaAs on Si, wherein the
threading dislocation density is generally about 10.sup.8/cm.sup.2,
and further reduced to about 10.sup.7/cm.sup.2 with an additional
annealing. Furthermore, due to large difference between thermal
expansion coefficient of GaAs and that of Si, it is difficult to
remove the additional dislocation induced during annealing, thus,
these arts obviously are not deemed to be used for fabricating of
high performance device.
[0008] Furthermore, the technique which uses interlayer as buffer
for growing GaAs on Si, that is, a structure of GaAs/interlayer/Si,
as we know the interlayer can include SeS.sub.2, ZnSe or STO film.
For example, an bonding technique disclosed in "High-quality GaAs
on Si substrate by the epitaixial lift-off technique using
SeS.sub.2" (Applied Physics Letters, Vol. 75, No. 24, 13 Dec. 1999)
from M. Umeno et al., which describes that a GaAs wafer is bonded
to silicon substrate using SeS.sub.2 as the interlayer and the
desirable GaAs layer is acquired by applying the lift-off
technique. However, these arts obviously make some problems, such
as high fabricating cost and no large scale of GaAs epitaxy on Si
substrate to be obtained.
[0009] And, the reference "Use of ZnSe as an interlayer for GaAs
growth on Si" (Applied Physics Letters, Vol. 61, No. 2, 13 Jul.
1992) from J. C. Tramontana et al. is reported that ZnSe is used as
the interlayer for growing GaAs epitaxy on Si, i.e., the interlayer
has a structure of GaAs/ZnSe/Si. However, it is difficult to grow a
high quality ZnSe on Si, and the small thermal conductivity of ZnSe
is disadvantageous for fabricating of device, thus, the utilization
of this invention is in the presence of some problems to be
solved.
[0010] In addition, it is reported in "New research yield
epitaixially grown GaAs on Si" (Solid State Technology, 45, 61
2002) from K. Esenbeiser et al., which discloses the use of STO
film as the interlayer for growing GaAs epitaxy on Si, i.e., a
structure of GaAs/STO film/Si. However, it is with high fabricating
cost and low productivity for growth by applying molecule beam
epitaxy (MBE), and additionally it is with small thermal
conductivity of STO film, which is disadvantageous for heat
diffusion of device, thus, the utilization of this invention
totally is in the presence of some problems to be solved, too.
[0011] As for applying the technique in using Ge composition graded
buffer for growing SiGe epitaxy, which is disclosed in "Novel
dislocation structure and surface morphology effects in relaxed
Ge/SiGe(graded)/Si structures" from E. A. Fitzgerald et al.
mentioned above, wherein graded Si.sub.1-xGe.sub.x is applied as
interlayer for the growth of GaAs epitaxy on Si due to almost the
same lattice constant and thermal expansion coefficient for the two
different materials, this technique has comparatively wide field in
application, but is also in the presence of some problems to be
overcome. That is, applying the concept of gradually increasing Ge
content of SiGe epitaxy, since the Ge composition starts from zero
to a very high value and herein forms the crosshatch pattern, where
the pattern brings a very high surface roughness. As for growing
under the condition that the Ge epitaixial layer is 6 degree
oriented to silicon substrate, the roughness is over 150 .ANG.;
comparatively, it gains a surface roughness of over 450 .ANG. for
growing without degrees. Wherein, high surface roughness due to
thick epitaixial layer and cross hatch pattern will increase the
fabrication cost of epitaxy and cause difficulties in device
producing. As for removing cross hatch pattern, chemical-mechanical
polishing (CMP) is subjected to solve these problems in
above-mentioned references and patents, but it increases additional
cost and causes difficulties in processing substantially.
SUMMARY OF THE INVENTION
[0012] A first object of this invention is to solve hereinabove
problems, as for growing Ge epitaxy on Si by using a novel method,
including how to lower the thickness of Ge epitaixial layers, to
flatten the surface roughness induced from high Ge-composition
epitaixial layers without help of CMP, and to lower the high
defects density due to lattice mismatch.
[0013] The epitaixial semiconductor structure has been disclosed in
relevant patents and references from E. A. Fitzgerald et al.,
wherein the structure contains a Ge composition graded buffer layer
and a Ge-composition uniform layer, however it is with a total
epitaixial layer thickness of over 10 .mu.m. The process disclosed
herein is on a silicon substrate, which a first Ge composition
graded SiGe epitaixial layer on said substrate is grown by using
molecular beam epitaxy (MBE) or ultra-high vacuum chemical vapor
deposition, generally at a grading rate of 10% Ge composition per
.mu.m of layers and gradually reaching to 50% of Ge composition,
then the surface of said layers is planarized by using
chemical-mechanical polishing (CMP). Herein the thickness of the
first layer is about 5 .mu.m. Subsequently, a second layer
comprising Ge composition from 50% to 75% is grown and a further
planarizing the surface of said second layer by using CMP is
performed. Herein the thickness of the second layer is about 2.5
.mu.m. Having grown a high Ge-composition third layer, it needs to
vary the epitaixial growth conditions including to lower the growth
temperature and partial pressure of growth gases, herein the
thickness of said third layer is above 2.5 .mu.m. According to the
foregoing process, the product of best mode is a epitaxy layer with
no surface cracking, threading dislocation density of about
10.sup.6/cm.sup.2, particles density on surface of about
150/cm.sup.2, roughness of 24 m and a total epitaixial layer
thickness of at least 10 .mu.m.
[0014] The conception of the process for this invention is, firstly
growing a high Ge-composition epitaixial layer, such as
Si.sub.0.1Ge.sub.0.9 in a thickness of 0.5.about.0.8 .mu.m on Si
substrate, in which many dislocations are generated and located
near the interfaces and in the low of part of this layer due to the
large mismatch between this layer and Si substrate. Subsequently
growing two or three layers of more high Ge-composition epitaixial
layers, such as Si.sub.0.05Ge.sub.0.95 and /or
Si.sub.0.02Ge.sub.0.98 in a thickness of 0.5.about.0.8 .mu.m. The
formed strained interfaces between said layers can bend and
terminate the propagated upward dislocation from the first layer
very effectively. Then, growing a final film of pure Ge on herein
epitaixial layer and a total epitaixial thickness is of only
several micrometers, such as below 3 micrometer.
[0015] The in-situ high temperature annealing for each layers is
performed in growing process therein, and carried out under the
temperature of from 650 to 800.degree. C., and 15.about.30 minutes
to further promote the quality of single crystalline of the Ge
film.
[0016] Compared to the study of E. A. Fitzgerald et al., the
invention applying high Ge content, such as initial
Si.sub.0.1Ge.sub.0.9 layer as the first layer SiGe epitaixial layer
and then providing further high Ge-composition layers, such as a
layer of Si.sub.0.05Ge.sub.0.95 and/or an optional
Si.sub.0.1Ge.sub.0.9 layer, is for the purpose of applying the
formed strained interfaces between the said layers to bend and
terminate the propagated upward dislocation from the first layer.
Thus, this invention has apparently different conception from prior
orts having growing pattern of Ge composition graded at a constant
grading rate of 5% or 10% from zero to 100% and that will be at
least 10 .mu.m in thickness of a total SiGe epitaixial layers
according to the grading rate herein. However, it is of high
possibility for this invention to have a total thickness of below 3
.mu.m.
BRIEF DESCRIPTION OF THE INVENTION
[0017] FIG. 1 is a schematic diagram of this invention for growing
mechanism of Ge epitaxy on Si substrate, which shows the conception
that the strained interface blocks the threading dislocation to be
generated and locks that dislocation near the interface.
[0018] FIG. 2 and 3 are cross-sectional (XTEM) and plane-view
transmission electronic microscope micrographs of the sample
according to this invention, wherein the sample obtained has a
total thickness SiGe epitaixial layers of about 2.6 .mu.m.,
threading dislocation density of about 3.times.10.sup.6/cm.sup.2 on
the top Ge layer, and surface roughness of 3.2 nm.
[0019] FIG. 4 is the analysis of the atomic force microscope
micrograph of the surface roughness of the sample according to this
invention, which shows the sample having a very smooth surface.
[0020] This process for the growth of SiGe epitaxy, which is based
upon ultra-high vacuum chemical vapor deposition and using
SiH.sub.4/Si.sub.2H.sub.6,GeH.sub.4 as growth gases, is carried out
at a temperature ranging from 350.degree. C. to 650.degree. C. and
a pressure ranging from 20 m-Torr to 100 m-Torr for growth gases
herein, and whatever a first, a second and/or an optional third
layers grown is under the same conditions except the feeding flow
of either SiH.sub.4/Si.sub.2H.sub.6 or GeH.sub.4. The low
temperature growing for Ge epitaxy is to prevent island formation
and downgrade the quality of Ge epitaxy, and further, the pressure
is to control the growing velocity for Ge epitaxy, and both factors
including temperature and pressure are preferably kept constant.
However, those prior arts for growth of Ge composition graded
epitaixial layers, in order to keep the Ge grading rate at a
constant, it must be controlled carefully to increase Ge content.
For example, to reduce the threading dislocation density of said
layers, lower a grading rate for Ge content is selected and more
thickly a total epitaxy thickness is formed. In another aspect, if
a higher grading rate, such as more than 10% of Ge composition per
micrometer of layers is selected, it will fast increase the
threading dislocation density.
[0021] Prior arts further comprise planarization for each
epitaixial layer after per growth cycle, said planarization such as
chemical-mechanical polishing is to eliminate the surface roughness
prior to a next layer on said surface. However, without very
complicated work sequence like that, this invention more
particularly allows to provide a surface having more equivalently
smooth-faced than that is planarized by using CMP, this invention
achieves that by means of different dislocation reducing mechanism
as described above.
[0022] A second object of this invention is to solve the problems
in prior arts, which concerns the growth of GaAs epitaixial layers
on silicon substrate by using interlayer, more particularly using
Si.sub.1-xGe.sub.x as buffer.
[0023] With respect to the techniques for GaAs grown on Si using
Si.sub.1-xGe.sub.x as buffer, it is reported in "Impact of GaAs
buffer thickness on electronic quality of GaAs grown on graded
Ge/SiGe/Si substrate" (Applied Physic Letters, Vol. 76, No. 14, 3
Apr. 2000) from E. A. Fitzgerald et al., they use Ge composition
graded buffer layers to grow SiGe epitaxy on silicon wafer, and
apply molecule beam epitaxy (MBE) to grow an GaAs epitaixial layer
on uppermost Ge film of said SiGe epitaxy, wherein the techniques
for Si.sub.1-xGe.sub.x grown on Si has been disclosed in U.S. Pat.
No. 6,291,321, 6,107,653 from E. A. Fitzgerald et al., and besides,
the techniques for growing a GaAs epitaixial layer on Ge applying
MBE has been disclosed in U.S. Pat. No. 5,308,444 from Jeng-Ming
Kuo et al. Therein is a semiconductor structure comprising a SiGe
epitaixial layer which has a Ge composition grading from zero to
100% and having low dislocation density in said layers, it is of a
total epitaixial layer thickness of above 10 .mu.m. The final step
of the process is to grow a thickness of about 2.5 .mu.m of GaAs on
latest Ge film by using MBE.
[0024] For overcoming the problems resulted from the growth of GaAs
on Si by using Ge graded Si.sub.1-xGe.sub.x as buffer, the
invention provides a different solution to grow the epitaixial
layers having reduced total thickness, smoother surface and lower
defects density.
[0025] The conception of the process for this invention is, firstly
growing a high Ge-composition epitaixial layer, such as
Si.sub.0.1Ge.sub.0.9 in a thickness of 0.5.about.0.8 .mu.m on Si
substrate, in which many dislocations are generated and located
near the interface and in the low of the part of this layer due to
large mismatch between this layer and Si substrate. Subsequently
growing two or three layers of more high Ge-composition epitaixial
layers, such as Si.sub.0.05Ge.sub.0.95 and/or
Si.sub.0.02Ge.sub.0.98 in a thickness of 0.5.about.0.8 .mu.m. The
formed strained interfaces of said layers can bend and terminate
the propagated upward dislocation from the first layer very
effectively. Then, growing a film of pure Ge on herein epitaixial
layer, and a total epitaixial thickness being of only several
micrometers, such as below 3 micrometer. Finally, growing a GaAs
epitaixial layer in a certain thickness on said Ge film by using
metal organic chemical vapor deposition (MOCVD), wherein the
thickness of epitaixial GaAs depending upon the properties required
for the fabrication of devices may be 1 to 3 .mu.m in thickness.
Therefore, according to the invention, the thickness of a total
epitaixial SiGe layer neglecting the additional GaAs layer, allows
to be, limited below 3 .mu.m substantially.
[0026] FIG.5 is a XRD micrograph of the GaAs/SiGe/Si epitaixial
layer sample according to this invention, wherein the sample is
obtained with a very high quality for single crystalline.
[0027] FIG.6 is a cross-sectional transmission electronic
microscope (XTEM) micrograph of the sample according to this
invention, and also shows a very good single crystalline
quality.
[0028] Another object of the invention is to be used in fabrication
of high-speed devices and optical devices based on Ge/Si and
GaAs/Ge/Si materials, such as Ge MOSFET combined with high-k gate
material, Ge photodetector, GaAs HBT, MESFET, HEMET, LED, Laser
etc, and future possible integrate of IV and III-V devices on the
same Si wafer.
DETAILED DESCRIPTION OF THE PREFERRED EMBODYMENT
[0029] The invention will be now illustrated in the following
example but not be limited to.
[0030] Firstly, pre-cleaning the silicon wafer in a standard
cleaning procedure, wherein the cleaning treatment comprises steps
of boiling the silicon wafer in a solution containing the mixtures
of H.sub.2O.sub.2:H.sub.2SO.sub.4 with the ratio 1:4 in about 10
min., then taking and rinsing it with de-ion water in 10 min.,
furthermore dipping it in a solution of 10% HF in 30 seconds and
subsequently further taking and rinsing it into de-ion water
loading the wafer into a UHVCVD system immediately after said
cleaning and prebaking the wafer at 850.degree. C. in 10 min to
remove the native oxided layer and then cooling the temperature of
UHVCVD system down to 400.degree. C. While temperature of system
present stable and is capable of growing a high Ge-composition SiGe
epitaixial layer. Wherein UHVCVD system is a quartz tube furnace
equipped with heating sources, and the background is vacuumed by a
molecular pump to a pressure of lower than 5.times.10.sup.-8 torr.
Growth gases including SiH.sub.4 and GeH.sub.4, which regulated by
mass flow controller (MFC) to adjust the feeding flows of the
gases. Wherein the flows supply of SiH.sub.4 is fixed and that of
GeH.sub.4 is adjusted only.
[0031] Growth is in condition of: [0032] (1) growth temperature
range: 350.about.650.degree. C.,preferably 400.degree. C. [0033]
(2) growth gases pressure range: 20.about.100 m-Torr, preferably 20
m-Torr [0034] (3) species of growth gases: high purity of SiH.sub.4
and GeH.sub.4.
[0035] In addition, further growing a second or a third higher
Ge-composition SiGe epitaixial layer being in a thickness of, such
as at least 0.1 .mu.m, preferably 0.5.about.0.8 .mu.m, most
preferably 0.8 .mu.m on the first layer subsequently growing a film
of Ge on said uppermost epitaixial layer in a thickness of, such as
1 .mu.m. At last, growing a GaAs epitaixial layer by using MOCVD in
a thickness of 1.about.3 .mu.m on said Ge film at 650.degree.
C.
[0036] During above-mentioned growth cycle, each of epitaixial
layers needs in-situ high temperature annealing to further promote
the quality of Ge and GaAs epitaxy, i.e., the conditions are a
temperature of 650.about.800.degree. C., preferably 750.degree. C.,
0.25 to 1 hour, and at a pressure of 5 to 20 m-Torr using hydrogen
as atmosphere of said annealing.
[0037] With respect to the growth cycle for Ge epitaxy on Si, the
Ge composition of first layer is at least 70%, preferably
70.about.90%, most preferably 90%, the Ge composition of second
layer is ranging within 80.about.98%, preferably 95%. The growth of
third layer is optionally carried out depending upon the growth
results of epitaxy, wherein the Ge content is decided between which
of second and pure Ge. Of course the uppermost lay is pure Ge,
which has almost the same lattice constant as GaAs, thus GaAs
epitaxy is grown on Ge film therein and is without mismatch at the
interface.
[0038] As for best mode of GaAs grown on Ge epitaxy according to
the invention, a first layer Si.sub.0.1Ge.sub.0.9 having about 0.8
.mu.m in thickness is obtained in conditions that growth
temperature is 400.degree. C., growth gases pressure is 20 m-Torr,
and is further in-situ treated by annealing at 750.degree. C.,in 15
min. After that, a second layer Si.sub.0.05Ge.sub.0.95 having about
0.8 .mu.m in thickness is formed in conditions that growth
temperature is 400.degree. C.,growth gases pressure is 20 m-Torr,
and is further in-situ treated by annealing at 750.degree. C., in
15 min. In the case of optional third layer which is
Si.sub.0.02Ge.sub.0.98 having about 0.8 .mu.m in thickness is also
obtained in conditions that growth temperature is 400.degree.
C.,growth gases pressure is 20 m-Torr, and is treated by annealing
at 750.degree. C., in 15 min. At last, uppermost layer which is
pure Ge having about 1.0 .mu.m in thickness is formed in conditions
that growth temperature is 400.degree. C.,growth gases pressure is
20 m-Torr, and is also in-situ treated by annealing at 750.degree.
C. in 15 min.
[0039] For the purpose of growing GaAs epitaxy on achieved Ge
epitaixial layers, it is carried out at 650.degree. C. by using
metal organic chemical vapor deposition equipment. The thickness of
epitaixial GaAs depends on the device requirement.
* * * * *