U.S. patent application number 11/395338 was filed with the patent office on 2007-06-07 for organic light emitting diode (oled) display panel and method of forming polysilicon channel layer thereof.
Invention is credited to Ming-Yan Chen, Jiunn-Yi Lin.
Application Number | 20070126000 11/395338 |
Document ID | / |
Family ID | 38117814 |
Filed Date | 2007-06-07 |
United States Patent
Application |
20070126000 |
Kind Code |
A1 |
Lin; Jiunn-Yi ; et
al. |
June 7, 2007 |
Organic light emitting diode (OLED) display panel and method of
forming polysilicon channel layer thereof
Abstract
An organic light emitting diode (OLED) display panel and a
method of forming a polysilicon channel layer thereof are provided.
In the method, firstly, a substrate having a polysilicon layer
disposed thereon is provided. Then, a dopant atom not selected from
the IIIA group and the VA group is doped inside the polysilcon
layer to form a polysilicon channel layer.
Inventors: |
Lin; Jiunn-Yi; (Jhubei City,
TW) ; Chen; Ming-Yan; (Jhubei City, TW) |
Correspondence
Address: |
RABIN & Berdo, PC
1101 14TH STREET, NW
SUITE 500
WASHINGTON
DC
20005
US
|
Family ID: |
38117814 |
Appl. No.: |
11/395338 |
Filed: |
April 3, 2006 |
Current U.S.
Class: |
257/40 ;
257/E27.111 |
Current CPC
Class: |
H01L 27/1285 20130101;
H01L 27/3244 20130101; H01L 27/1296 20130101 |
Class at
Publication: |
257/040 |
International
Class: |
H01L 29/08 20060101
H01L029/08; H01L 35/24 20060101 H01L035/24; H01L 51/00 20060101
H01L051/00 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 1, 2005 |
TW |
94142373 |
Claims
1. An organic light emitting diode (OLED) display panel,
comprising: a substrate; a pixel disposed on the substrate; and a
first thin film transistor disposed inside the pixel and comprising
a first polysilicon channel layer, wherein a first dopant atom not
selected from the III A group and the VA group is doped inside the
first polysilicon channel layer.
2. The panel according to claim 1, wherein the doping concentration
of the first dopant atom in the first polysilicon channel layer
ranges 10.sup.11.about.10.sup.15 atoms/cm.sup.2.
3. The panel according to claim 1, wherein the first thin film
transistor further comprises a first gate, a first source and a
first drain, the first source and the first drain are
correspondingly and electrically connected to two ends of the first
polysilicon channel layer, the first source is electrically
connected to a first constant voltage, and the OLED display panel
further comprises: a first scan line and a second scan line both
disposed on the substrate in parallel; a first data line and a
second data line both disposed on the substrate in parallel,
perpendicular to and alternating with the first scan line and the
second scan line to define the pixel; a second thin film transistor
disposed inside the pixel and comprising a second gate, a second
source, a second drain and a second polysilicon channel layer,
wherein the second source and the second drain are correspondingly
and electrically connected to two ends of the second polysilicon
channel layer, the second gate is electrically connected to the
first scan line, the second source is electrically connected to the
first data line, and the second drain is electrically connected to
the first gate; a storage capacitor disposed inside the pixel,
wherein one end of the storage capacitor is electrically connected
between the second drain and the first gate, the other end of the
storage capacitor is electrically connected between the first
source and the first constant voltage; and an organic
electroluminescent device (OELD) disposed inside the pixel to be
electrically connected to the first drain and a second constant
voltage.
4. The panel according to claim 3, wherein a second dopant atom not
selected from the IIIA group and the VA group is doped inside the
second polysilicon channel layer.
5. The panel according to claim 4, wherein the first dopant atom
and the second dopant atom are neutral atoms.
6. The panel according to claim 5, wherein the first dopant atom
and the second dopant atom comprise inert gas and/or the IVA
group.
7. The panel according to claim 6, wherein the first dopant atom
and the second dopant atom respectively are selected from the group
consisting of helium (He), neon (Ne), argon (Ar), krypton (Kr),
xenon (Xe) and radon (Rn) and any combination thereof.
8 The panel according to claim 4, wherein the doping concentration
of the first dopant atom in the first polysilicon channel layer is
larger than the doping concentration of the second dopant atom in
the second polysilicon channel layer.
9. A method of forming a polysilicon channel layer, comprising:
providing a substrate having a first polysilicon layer and a second
polysilicon layer disposed thereon; covering the substrate by a
first mask, wherein the substrate has a first opening for exposing
the first polysilicon layer; and doping a first dopant atom not
selected from the IIIA group and the VA group inside the first
polysilicon layer to form a first polysilicon channel layer.
10. The method according to claim 9, wherein the doping
concentration of the first dopant atom in the first polysilicon
channel layer ranges 10.sup.11.about.10.sup.15 atoms/cm.sup.2.
11. The method according to claim 9, further comprising: removing
the first mask and covering the substrate by a second mask, wherein
the second mask has a second opening for exposing the second
polysilicon layer; and doping a second dopant atom not selected
from the IIIA group and the VA group inside the second polysilicon
layer to form a second polysilicon channel layer, wherein the
doping concentration of the second dopant atom in the second
polysilicon channel layer is the same or different with the doping
concentration of the first dopant atom in the first polysilicon
channel layer.
12. The method according to claim 11, wherein the first dopant atom
and the second dopant atom are neutral atoms.
13. The method according to claim 12, wherein the first dopant atom
and the second dopant atom comprise inert gas and/or the IVA
group.
14. The method according to claim 13, wherein the first dopant atom
and the second dopant atom respectively are selected from the group
consisting of helium (He), neon (Ne), argon (Ar), krypton (Kr),
xenon (Xe) and radon (Rn) and any combination thereof.
15. The method according to claim 14, wherein the doping
concentration of the first dopant atom in the first polysilicon
channel layer is larger than the doping concentration of the second
dopant atom in the second polysilicon channel layer.
16. A method of forming a polysilicon channel layer, comprising:
providing a substrate having a first polysilicon layer and a second
polysilicon layer disposed thereon; covering the substrate by a
first mask, wherein the first mask has a first opening and a second
opening for respectively exposing the first polysilicon layer and
the second polysilicon layer; doping a first dopant atom not
selected from the IIIA group and the VA group inside the first
polysilicon layer and the second polysilicon layer to respectively
form a first polysilicon channel layer and a second polysilicon
channel layer, wherein the doping concentration of the first dopant
atom in the first polysilicon channel layer is the same with the
doping concentration of the first dopant atom in the second
polysilicon channel layer; removing the first mask and covering the
substrate by a second mask, wherein the second mask has a third
opening for exposing the first polysilicon channel layer; and
doping a second dopant atom inside the first polysilicon channel
layer to form a third polysilicon channel layer, wherein the total
doping concentration of the first dopant atom and the second dopant
atom in the third polysilicon channel layer is larger than the
doping concentration of the first dopant atom in the second
polysilicon channel layer.
17. The method according to claim 16, wherein the first dopant atom
and the second dopant atom are neutral atoms.
18. The method according to claim 17, wherein the first dopant atom
and the second dopant atom comprise inert gas and/or the IV A
group.
19. The method according to claim 18, wherein the first dopant atom
and the second dopant atom respectively are selected from the group
consisting of helium (He), neon (Ne), argon (Ar), krypton (Kr),
xenon (Xe) and radon (Rn) and any combination thereof.
20. The method according to claim 16, wherein the total doping
concentration of the first dopant atom and the second dopant atom
in the third polysilicon channel layer ranges
10.sup.11.about.10.sup.15 atoms/cm.sup.2.
Description
[0001] This application claims the benefit of Taiwan application
Serial No. 94142373, filed Dec. 1, 2005, the subject matter of
which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates in general to an organic light
emitting diode (OLED) panel and a method of forming a polysilicon
channel layer thereof, and more particularly to an OLED display
panel having a dopant atom not selected from the IIIA group and the
VA group doped inside a polysilicon channel layer and a method of
forming the polysilicon channel layer thereof.
[0004] 2. Description of the Related Art
[0005] In the conventional process of manufacturing a low
temperature polysilicon (LTPS) liquid crystal display (LCD) panel
and an organic light emitting diode (OLED) display panel, typically
the excimer laser annealing (ELA) technology is used to scan and
melt an amorphous silicon (a-Si) layer to form the crystallization
of a polysilicon layer. The polysilicon layer can be used as a
channel layer of a thin film transistor (TFT) to improve the
electrical performance of the TFT.
[0006] According to related literatures, there are two types of
defects affecting the electrical performance of polysilicon TFT,
namely, the grain boundary trap defect and the interface trap
defect. The grain boundary trap defect mainly occurs during the
process of melting the crystallization of an amorphous silicon
layer to form a polysilicon layer. When the ELA technology is used
to melt the amorphous silicon layer to form the crystallization of
a polysilicon layer (the technology is referred as the ELA
crystallization technology hereafter), the number of grain boundary
trap defects and the number of interface traps are approximately
equal to 1012 and 1011, respectively. It can be seen from the
number of defects that the channel quality of the polysilicon layer
is greatly affected by the grain boundary trap defects.
[0007] In terms of an LTPS LCD, despite defects occur to the
channel layer of the high efficient TFT manufactured according to
the ELA crystallization technology, the TFT, which is merely used
as a switch element of pixels, still meets the requirements of the
LTPS LCD.
[0008] However, when it comes to OLED display panel, the above
negative effect of defects can not be neglected. In the active
pixel matrix of the OLED display panel, each pixel TFT drives an
organic electroluminescent device (OELD) having an anode, a cathode
and an organic material layer by a current. The polysilicon layer
manufactured according to the ELA crystallization technology has
non-uniformed crystallization and defects, causing the channel
layer of each TFT to have different characteristics. As a result,
line mura would occur to the OLED display panel, largely
deteriorating the display quality of the OLED display panel.
SUMMARY OF THE INVENTION
[0009] It is therefore an object of the invention to provide an
OLED display panel and a method of forming a polysilicon channel
layer thereof. The design of disposing a dopant atom not selected
from the IIIA group and the VA group inside the polysilicon layer
(such as the polysilicon layer formed according to the ELA
crystallization technology) formed by applying heat treatment to
the crystallization of the amorphous silicon layer uniforms the
defects of the polysilicon layer. Therefore, the non-uniform
crystallization and defects of the polysilicon layer can be
improved, so that the polysilicon channel layer of each TFT has the
same characteristics. As a result, each pixel TFT has the same
characteristics, preventing the OLED display panel from generating
line mura during operation, largely improving the display quality
of the OLED display panel.
[0010] The invention achieves the above-identified object by
providing an OLED display panel including a substrate, a pixel and
a thin film transistor. The pixel is disposed on the substrate. The
thin film transistor disposed inside the pixel includes a
polysilicon channel layer. A dopant atom not selected from the IIIA
group and the VA group of periodic table the is doped inside the
polysilicon channel layer.
[0011] The invention further achieves the above-identified object
by providing a method of forming a polysilicon channel layer. At
first, a substrate having an amorphous silicon layer disposed
thereon is provided. Then, heat treatment is applied to the
amorphous silicon layer to form a polysilicon layer. Then, a dopant
atom not selected from the IIIA group and the VA group of periodic
table is doped inside the polysilcon layer to form a polysilicon
channel layer.
[0012] The invention further achieves the above-identified object
by providing a method of forming a polysilicon channel layer. At
first, a substrate having a first polysilicon layer and a second
polysilicon layer disposed thereon is provided. Then, a mask having
an opening for exposing the first polysilicon layer is used to
cover the substrate. Then, a dopant atom not selected from the IIIA
group and the VA group of periodic table is doped inside the first
polysilicon layer to form a polysilicon channel layer.
[0013] The invention further achieves the above-identified object
by providing a method of forming a polysilicon channel layer. At
first, a substrate having a first polysilicon layer and a second
polysilicon layer disposed thereon is provided. Then, a first mask
having a first opening and a second opening for respectively
exposing the first polysilicon layer and the second polysilicon
layer is used to cover the substrate. Then, a first dopant atom not
selected from the IIIA group and the VA group of periodic table is
doped inside the first polysilicon layer and the second polysilicon
layer to respectively form a first polysilicon channel layer and a
second polysilicon channel layer. The doping concentration of the
first dopant atom in the first polysilicon channel layer is the
same with the doping concentration of the first dopant atom in the
second polysilicon channel layer. Then, the first mask is removed,
and a second mask having a third opening for exposing the first
polysilicon channel layer is used to cover the substrate. Then, a
second dopant atom not selected from the IIIA group and the VA
group of periodic table is doped inside the first polysilicon
channel layer to form a third polysilicon channel layer. The total
doping concentration of the first dopant atom and the second dopant
atom in the third polysilicon channel layer is larger than the
doping concentration of the first dopant atom in the second
polysilicon channel layer.
[0014] Other objects, features, and advantages of the invention
will become apparent from the following detailed description of the
preferred but non-limiting embodiments. The following description
is made with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 illustrates a circuit structure of a single pixel of
an organic light emitting diode (OLED) display panel according to a
first embodiment of the invention;
[0016] FIG. 2 illustrates a cross-sectional view of detailed
structure of the single pixel of the OLED display panel according
to the first embodiment of the invention;
[0017] FIG. 3 is a flowchart of a method of forming a polysilicon
channel layer according to a second embodiment of the
invention;
[0018] FIG. 4 is a flowchart of a method of forming a polysilicon
channel layer according to a third embodiment of the invention;
[0019] FIGS. 5A.about.5H illustrate cross-sectional views of the
manufacturing process of a polysilicon channel layer according to
the third embodiment of the invention;
[0020] FIG. 6 is a flowchart of a method of forming a polysilicon
channel layer according to a fourth embodiment of the invention;
and
[0021] FIGS. 7A.about.7H illustrate cross-sectional views of the
manufacturing process of a polysilicon channel layer according to
the fourth embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
First Embodiment
[0022] Referring to FIGS. 1.about.2. FIG. 1 illustrates a circuit
structure of a single pixel of an organic light emitting diode
(OLED) display panel according to a first embodiment of the
invention. FIG. 2 illustrates a cross-sectional view of detailed
structure of the single pixel of the OLED display panel according
to the first embodiment of the invention. As shown in FIGS.
1.about.2, the OLED display panel 10 at least includes a substrate
11, a pixel 13 and a first thin film transistor (TFT) T1. The pixel
13 disposed on the substrate 11 is exemplified by one of the
several pixels of an active matrix pixel array. The first thin film
transistor T1 disposed inside the pixel 13 includes a first
polysilicon channel layer 14. Apart from a polysilicon, the first
polysilicon channel layer 14 further includes a first dopant atom
not selected from the III A group and the VA group of periodic
table to uniform the defects of the polysilicon layer before
doping. Therefore, the non-uniformity of the defects and
crystallization of the polysilicon layer can be improved, and the
polysilicon channel layer of each pixel TFT can have the same
characteristics. As a result, the OLED display panel will not
generate line mura during operation, largely improving the display
quality of the OLED display panel and greatly impressing the
consumers.
[0023] Examples of the first dopant atom doped inside the first
polysilicon channel layer 14 includes a neutral atom, an inert gas
and/or the IVA group of periodic table. For example, the first
dopant atom is a dopant atom selected from the group consisting of
helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe) and
radon (Rn) and any combination thereof. The first dopant atom is a
dopant atom selected from the group consisting of carbon (C),
silicon (Si), germanium (Ge), tin (Sn) and lead (Pb) and any
combination thereof. The first dopant atom can also be selected
from the combination of inert gases and the IV A group. However,
the technology of the present embodiment of the invention is not
limited thereto. For example, the first dopant atom can be selected
from neutral dopant atoms other than the IIIA group and the VA
group of the periodic table. That is, the first dopant atom is not
selected from the IIIA group and the VA group of the periodic
table. Furthermore, the doping concentration of the first dopant
atom in the first polysilicon channel layer 14 ranging
10.sup.11.about.10.sup.15 atoms/cm.sup.2 can be larger than
10.sup.12 atoms/cm.sup.2. The above first polysilicon channel layer
14 can be achieved by doping a polysilicon layer with the first
dopant atom, and the polysilicon layer can be achieved by applying
heat treatment to an amorphous silicon layer. For example, the
amorphous silicon layer can be melted according to the laser
annealing method to form the crystallization of the polysilicon
layer. In the laser annealing method, the amorphous silicon layer
is scanned and melted by an excimer laser.
[0024] In the process of manufacturing the first thin film
transistor T1 according to the present embodiment of the invention,
at first, the amorphous silicon layer is melted according to the
excimer laser annealing (ELA) crystallization technology to form
the crystallization of the polysilicon layer. Then, a fixed amount
of first dopant atom is doped inside the polysilicon layer to
achieve the above first polysilicon channel layer 14.
[0025] In the present embodiment of the invention, the first thin
film transistor T1 further includes a first gate G1, a first source
S1 and a first drain D1. The first source S1 and the first drain D1
are disposed on the first polysilicon channel layer 14, and are
correspondingly and electrically connected to the two ends of the
first polysilicon channel layer 14. The first gate G1 is disposed
on the first polysilicon channel layer 14, and positioned between
the first source S1 and the first drain D1. The first source S1 and
the first drain D1 respectively are electrically connected to and
contact the polysilicon channel layer 14 via a heavily doping N
type layer (N+).
[0026] Moreover, the OLED display panel 10 further includes a first
scan line SL1, a second scan line SL2, a first data line DL1, a
second data line DL2, and a second thin film transistor T2. The
first scan line SL1 and the second scan line SL2 are disposed on
the substrate 11 in parallel. The first data line DL1 and the
second data line DL2 are disposed on the substrate 11 in parallel,
and are respectively perpendicular to and alternate with the first
scan line SL1 and the second scan line SL2 to define the pixel 13.
The second thin film transistor T2 disposed inside the pixel 13
includes a second gate G2, a second source S2, a second drain D2
and a second polysilicon channel layer 22. The second source S2 and
the second drain D2 are correspondingly disposed on the two ends of
the second polysilicon channel layer 22, and are electrically
connected to and ohmly contact the two ends of the second
polysilicon channel layer 22 via the N+ layer, respectively. The
second gate G2 is electrically connected to the first scan line
SL1. The second source S2 is electrically connected to the first
data line DL1. The second drain D2 is electrically connected to the
first gate G1.
[0027] A second dopant atom not selected from the IIIA group and
the VA group is doped inside the second polysilicon channel layer
22. The doping concentration of the second dopant atom in the
second polysilicon channel layer 22 is the same or different with
the doping concentration of the first dopant atom in the first
polysilicon channel layer 14. The doping concentration of the first
dopant atom in the first polysilicon channel layer 14 can be larger
than the doping concentration of the second dopant atom in the
second polysilicon channel layer 22. Examples of the second dopant
atom include a neutral atom, an inert gas and/or the IV A group.
For example, the second dopant atom is a dopant atom selected from
the group consisting of helium (He), neon (Ne), argon (Ar), krypton
(Kr), xenon (Xe) and radon (Rn) and any combination thereof. The
second dopant atom is a dopant atom selected from the group
consisting of carbon (C), silicon (Si), germanium (Ge), tin (Sn)
and lead (Pb) and any combination thereof. The second dopant atom
can be selected from the combination of inert gases and the IVA
group. The first dopant atom is the same or different with the
second dopant atom. The second dopant atom can be selected from the
neutral dopant atoms other than the IRA group and the VA group of
the periodic table. Moreover, the above second polysilicon channel
layer 22 can be achieved by doping a polysilicon layer with the
second dopant atom, and the polysilicon layer can be achieved by
applying heat treatment to an amorphous silicon layer. For example,
the amorphous silicon layer can be melted according to the laser
annealing method to form the crystallization of the polysilicon
layer. In the laser annealing method, the amorphous silicon layer
is scanned and melted by an excimer laser.
[0028] The OLED display panel 10 further includes a storage
capacitor Cs and an organic electroluminescent device (OELD) 25.
The storage capacitor Cs is disposed inside the pixel 13. One end
of the storage capacitor Cs is electrically connected between the
first gate G1 and the second drain D2, and the other end of the
storage capacitor Cs is electrically connected between the first
source S1 and a first constant voltage Vdd. The OELD 25 is disposed
inside the pixel 13 to be electrically connected to the first drain
D1 and a second constant voltage Vss.
[0029] Any one who is skilled in the technology of the present
embodiment of the invention will understand that the technology of
the present embodiment of the invention is not limited thereto. For
example, the OLED display panel 10 further includes an isolation
layer 18 disposed among the first polysilicon channel layer 14, the
second polysilicon channel layer 22 and the substrate 11. Besides,
the OLED display panel 10 further includes an isolation layer 19
disposed among the first gate G1, the second gate G2 and the first
polysilicon channel layer 14. Examples of the isolation layers 18
and 19 include oxide, nitride, nitroxide, nitro-silicon or nitrogen
oxide.
[0030] The detailed structure of the OELD 25 is exemplified below.
However, the technology of the present embodiment of the invention
is not limited thereto. The OELD 25 at least includes an anode 26,
a cathode 27 and an organic material layer 28. The organic material
layer 28 is disposed between the anode 26 and the cathode 27. The
anode 26 is electrically connected to the first drain D1. The
cathode 27 can be grounded or receive a constant voltage. The
organic material layer 28 can include an electron hole source, an
electron source and a light emitting layer. The light emitting
layer is disposed between the electron hole source and the electron
source. The electron hole source is adjacent to the anode 26, and
the electron source is adjacent to the cathode 27.
[0031] In the present embodiment of the invention, the OLED display
panel 10 further includes a substrate 21. The substrate 21 and the
substrate 11 are assembled in parallel by a sealant for sealing and
enclosing the pixel 13, the first thin film transistor T1, the
second thin film transistor T2, the storage capacitor Cs and the
OELD 25. Examples of the substrates 11 and 21 include glass
substrate, plastic substrate, ceramic substrate or flexible
substrate.
[0032] Despite the present embodiment of the invention is
exemplified by the TFT structure of the top gate, the technology of
doping the polysilicon channel layer of the present embodiment of
the invention with a dopant atom not selected from the IIIA group
and the VA group can be applied to the TFT structure of the bottom
gate or the dual gates.
[0033] According to the present embodiment of the invention, after
the amorphous silicon layer is melted according to the excimer
laser annealing (ELA) method to form the crystallization of the
polysilicon layer (the ELA crystallization technology), the
original density of the defects of the polysilicon layer is
adjusted by doping the dopant atom not selected from the IIIA group
and the VA group inside the polysilicon layer to form the
polysilicon channel layer. As the doping amount and density of the
dopant atom not selected from the IIIA group and the VA group can
be precisely controlled, the characteristics of the TFT can be
effectively controlled accordingly. The uniformity achieved
according to the doping technology improves the non-uniformity of
the ELA crystallization method as well as the line mura effect. The
table disclosed below illustrates the improvement in the density of
defects of the channel layer of the OLED display panel. The
resulted line mura of the entire OLED display panel before the
dopant atom not selected from the IIIA group and the VA group is
doped is compared with the resulted line mura of the entire OLED
display panel after the dopant atom not selected from the IIIA
group and the VA group is doped. However, the technology of the
present embodiment of the invention is not limited thereto.
TABLE-US-00001 TABLE 1 Area Without Area With Defect Line Mura Line
Mura Ratio Defect Concentration Before 10.sup.12 10.sup.13 10
Doping (defects/cm.sup.2) The Doping concentration of 10.sup.13
10.sup.13 1 the Dopant Atom not Selected from the III A Group and
the VA Group (atoms/cm.sup.2) Defect Concentration After
1.1*10.sup.13 2*10.sup.13 1.67 Doping (defects/cm.sup.2)
[0034] It can be seen from Table 1 that in a conventional OLED
display panel without doping the dopant atom not selected from the
IIIA group and the VA group, the defect ratio between the defects
of the area with line mura and the defects of the area without line
mura is 10:1. In the OLED display panel of the present embodiment
of the invention, after doping the dopant atom not selected from
the IIIA group and the VA group in the polysilicon layer, the
doping concentration of the dopant atom not selected from the MA
group and the VA group increases by 10 times. The defect ratio
between the defects of the area with line mura and the defects of
the area without line mura is improved from 10:1 to 1.67:1 after
doping a calculated amount of dopant not selected from the IIIA
group and the VA group. By doping an appropriate amount of the
dopant atom not selected from the IIIA group and the VA group, the
channel quality is uniformed so that the polysilicon channel layer
of each pixel TFT has the same characteristics and that the
non-uniformity of defects and ELA crystallization of is improved.
As a result, each pixel TFT has the same characteristics.
[0035] With regard to the performance of the OLED display panel
under different doping densities of the dopant atom not selected
from the IIIA group and the VA group according to the present
embodiment of the invention, the doping concentration of the dopant
atom not selected from the IIIA group and the VA group is
1.5*10.sup.12/cm.sup.2 and still has line mura. However, the line
mura in the present embodiment of the invention is fewer than the
line mura under standard conditions.
[0036] When the doping concentration of the dopant atom not
selected from the IIIA group and the VA group is
1.5*10.sup.13/cm.sup.2, no line mura occurs. The effect of line
mura can be improved by appropriately adjusting the doping
concentration of the dopant atom not selected from the IIIA group
and the VA group. This is because the performance of the channel
quality is dominated by the effect of doping the dopant atom not
selected from the IIIA group and the VA group instead of the ELA
crystallization technology.
[0037] The grain size of the polysilicon layer before doping ranges
0.1.about.10 .mu.m. The density of the grain boundary defect of the
polysilicon layer is larger than 10.sup.11 defects/cm.sup.2. When
the polysilicon layer is within 5 .mu.m, the largest thickness
differs with the smallest thickness by more than 100 .ANG., that
is, the height of the protrusion of the polysilicon layer, and the
density of the first dopant atom not selected from the IIIA group
and the VA group doped inside the first polysilicon channel layer
14 can be larger than 10.sup.12 atoms/cm.sup.2. Therefore, the
present embodiment of the invention, according to the grain size of
the polysilicon layer, the density of grain boundary defect, and
the height of the protrusion of the polysilicon layer, can
appropriately adjust the density of the dopant atom not selected
from the IIIA group and the VA group doped inside the polysilicon
layer to form the needed polysilicon channel layer.
Second Embodiment
[0038] Referring to FIG. 3, a flowchart of a method of forming a
polysilicon channel layer according to a second embodiment of the
invention is shown. As shown in FIG. 3, at first, in the step 31, a
substrate having an amorphous silicon layer disposed thereon is
provided. Then, proceed to the step 32, heat treatment is applied
to the amorphous silicon layer to form a polysilicon layer. Then,
proceed to the step 33, a dopant atom not selected from the III A
group and the VA group is doped inside the polysilcon layer to form
a polysilicon channel layer. Examples of the dopant atom include a
neutral atom, an inert gas and/or the IVA group. For example, a
dopant atom is selected from the group consisting of helium (He),
neon (Ne), argon (Ar), krypton (Kr), xenon (Xe) and radon (Rn) and
any combination thereof, but is not selected from the IIIA group
and the VA group in the periodic table. The dopant atom is a dopant
atom selected from the group consisting of carbon (C), silicon
(Si), germanium (Ge), tin (Sn) and lead (Pb) and any combination
thereof. The dopant atom can be selected from the combination of
inert gases and the IV A group. Besides, the doping concentration
of the dopant atom in the polysilicon channel layer ranging
10.sup.11.about.10.sup.15 atoms/cm.sup.2 can be larger than
10.sup.12 atoms/cm.sup.2. Besides, heat treatment can also be
applied to the amorphous silicon layer according to the laser
annealing method. For example, the amorphous silicon layer is step
scanned and melted by an excimer laser to form the polysilicon
layer according to the ELA crystallization technology.
[0039] In the present embodiment of the invention, the design of
doping the crystallization of the polysilicon layer formed by
applying heat treatment to the amorphous silicon layer (such as the
polysilicon layer formed according to the ELA crystallization
technology) with the dopant atom not selected from the IIIA group
and the VA group (such as inert gases) enables the defects of the
polysilicon layer to be uniformed, improving the non-uniformity of
the defects and crystallization of the polysilicon. Thus, the OLED
display panel manufactured in subsequent manufacturing process will
not generate line mura during operation, largely improving the
display quality of the OLED display panel.
Third Embodiment
[0040] Referring to FIGS. 4.about.5H. FIG. 4 is a flowchart of a
method of forming a polysilicon channel layer according to a third
embodiment of the invention. FIGS. 5A.about.5H illustrate
cross-sectional views of the manufacturing process of a polysilicon
channel layer according to the third embodiment of the invention.
As shown in FIG. 4, at first, in the step 41, a substrate 11 having
a first polysilicon layer 24a and a second polysilicon layer 24b
disposed thereon is provided. As for how the first polysilicon
layer 24a and the second polysilicon layer 24b are formed on the
substrate 11 is exemplified below. However, the technology of the
present embodiment of the invention is not limited thereto. As
shown in FIG. 5A, the substrate 11 having an amorphous silicon
layer 23 disposed thereon is provided. Then, heat treatment is
applied to the amorphous silicon layer 23 to form a polysilicon
layer 24 as shown in FIG. 5B. Here, heat treatment can be applied
to the amorphous silicon layer 23 according to the laser annealing
method. For example, the amorphous silicon layer 23 is step scanned
and melted by an excimer laser 53 along the direction of the arrow
54 in FIG. 5A to form the crystallization of the polysilicon layer
24 step by step. Then, as shown in FIG. 5C, part of the polysilicon
layer 24 is removed form the first polysilicon layer 24a and the
second polysilicon layer 24b. However, the technology of forming
the first polysilicon layer 24a and the second polysilicon layer
24b according to the present embodiment of the invention is not
limited thereto.
[0041] After the first polysilicon layer 24a and the second
polysilicon layer 24b are formed on the substrate 11, proceed to
the step 42 as shown in FIG. 5D, the substrate 11 is covered by a
first mask 51. The first mask 51 has a first opening 51a used for
exposing the first polysilicon layer 24a.
[0042] Then, proceed to the step 43 as shown in FIG. 5E, a first
dopant atom not selected from the IIIA group and the VA group A1 is
doped inside the first polysilicon layer 24a to form a first
polysilicon channel layer 14. Examples of the first dopant atom A1
include a neutral atom, an inert gas and/or the IVA group. The
first dopant atom A1 is selected from the group consisting of
helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe) and
radon (Rn) and any combination thereof. The first dopant atom A1 is
a dopant atom selected from the group consisting of carbon (C),
silicon (Si), germanium (Ge), tin (Sn) and lead (Pb) and any
combination thereof. The first dopant atom A1 can be selected from
the combination of inert gases and the IV A group. The doping
concentration of the first dopant atom A1 in the first polysilicon
channel layer 14 ranges 10.sup.11.about.10.sup.15 atoms/cm2. In the
step 43, the first dopant atom A1 can be used as a source of dopant
to be doped inside the first polysilicon layer 24a according to the
ion implantation method.
[0043] Then, proceed to the step 44 as shown in FIG. 5F, the first
mask 51 is removed, and the substrate 11 is covered by a second
mask 52. The second mask 52 has a second opening 52a used for
exposing the second polysilicon layer 24b.
[0044] Then, proceed to the step 45 as shown in FIG. 5G, a second
dopant atom not selected from the IIIA group and the VA group A2 is
doped inside the second polysilicon layer 24b to form a second
polysilicon channel layer 22. Examples of the second dopant atom A2
include a neutral atom, an inert gas and/or the IVA group. The
doping concentration of the second dopant atom A2 in the second
polysilicon channel layer 22 is the same or different with the
doping concentration of the first dopant atom A1 in the first
polysilicon channel layer 14. The doping concentration of the first
dopant atom A1 in the first polysilicon channel layer 14 is larger
than the doping concentration of the second dopant atom A2 in the
second polysilicon channel layer 22. The second dopant atom is a
dopant atom selected from the group consisting of helium (He), neon
(Ne), argon (Ar), krypton (Kr), xenon (Xe) and radon (Rn) and any
combination thereof. The second dopant atom A2 is a dopant atom
selected from the group consisting of carbon (C), silicon (Si),
germanium (Ge), tin (Sn) and lead (Pb) and any combination thereof.
The second dopant atom A2 can be selected from the combination of
inert gases and the IV A group. The first dopant atom A1 and the
second dopant atom A2 can be the same or different. In the step 45,
the second dopant atom A2 can be used as a source of dopant to be
doped inside the second polysilicon layer 24b according to the ion
implantation method. Then, proceed to the step 46 as shown in FIG.
5H, the second mask 52 is removed.
[0045] Any one who is skilled in the technology of the present
embodiment of the invention will understand that the technology of
the present embodiment of the invention is not limited thereto. For
example, after the first polysilicon layer 24a and the second
polysilicon layer 24b are formed on the substrate 11, a thin
sacrifice layer such as silicon dioxide (SiO.sub.2) can be used to
cover the first polysilicon layer 24a and the second polysilicon
layer 24b. Besides. after the second dopant atom A2 is doped inside
the second polysilicon layer 24b, dilute HF is used to remove the
sacrifice layer. Here, the sacrifice layer can be used as a buffer
layer when the first dopant atom A1 and the second dopant atom A2
are respectively doped inside the first polysilicon layer 24a and
the second polysilicon layer 24b to mitigate the damage occurring
to the surface of the first polysilicon layer 24a and the source of
the second polysilicon layer 24b when doped with the first dopant
atom A1 and the second dopant atom A2, respectively.
Fourth Embodiment
[0046] Referring to FIGS. 6.about.7H. FIG. 6 is a flowchart of a
method of forming a polysilicon channel layer according to a fourth
embodiment of the invention. FIGS. 7A.about.7H illustrate
cross-sectional views of the manufacturing process of a polysilicon
channel layer according to the fourth embodiment of the invention.
As shown in FIG. 6, at first, in the step 61, a substrate 11 having
a first polysilicon layer 24a and a second polysilicon layer 24b
disposed thereon is provided. As for how the first polysilicon
layer 24a and the second polysilicon layer 24b are formed on the
substrate 11 as shown in FIGS. 7A.about.7C is already disclosed in
the second embodiment, and is not repeated here.
[0047] Then, proceed to the step 62 as shown in FIG. 7D, the
substrate 11 is covered by a first mask 71. The first mask 71 has a
first opening 71a and a second opening 71b. The first opening 71a
and the second opening 71b are respectively used for exposing the
first polysilicon layer 24a and the second polysilicon layer
24b.
[0048] Then, proceed to the step 63 as shown in FIG. 7E, a first
dopant atom not selected from the IIIA group and the VA group A3 is
doped inside the first polysilicon layer 24a and the second
polysilicon layer 24b to respectively form a third polysilicon
channel layer 24c and a second polysilicon channel layer 22.
Examples of the first dopant atom A3 include a neutral atom, an
inert gas and/or the IVA group. The doping concentration of the
first dopant atom A3 in the second polysilicon channel layer 22 is
the same with the doping concentration of the first dopant atom A3
in the third polysilicon channel layer 24c. The first dopant atom
A3 is a dopant atom selected from the group consisting of helium
(He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe) and radon
(Rn) and any combination thereof. The first dopant atom A3 is a
dopant atom selected from the group consisting of carbon (C),
silicon (Si), germanium (Ge), tin (Sn) and lead (Pb) and any
combination thereof. The first dopant atom A3 can be selected from
the combination of inert gases and the IVA group. In the step 63,
the first dopant atom A3 is used as a source of dapant to be doped
inside the first polysilicon layer 24a and the second polysilicon
layer 24b according to the ion implantation method.
[0049] Then, proceed to the step 64 as shown in FIG. 7F, the first
mask 71 is removed, and the substrate 11 is covered by a second
mask 72. The second mask 72 has a third opening 72a used for
exposing the third polysilicon channel layer 24c.
[0050] Then, proceed to the step 65 as shown in FIG. 7G, a second
dopant atom not selected from the IIIA group and the VA group A4 is
doped inside the third polysilicon channel layer 24c to form a
first polysilicon channel layer 14. Examples of the second dopant
atom A4 include a neutral atom, an inert gas and/or the IVA group.
The total doping concentration of the first dopant atom A3 and the
second dopant atom A4 in the first polysilicon channel layer 14 is
the same or different with the doping concentration of the first
dopant atom A3 in the second polysilicon channel layer 22. For
example, the total doping concentration of the first dopant atom A3
and the second dopant atom A4 in the first polysilicon channel
layer 14 is larger than the doping concentration of the first
dopant atom A3 in the second polysilicon channel layer 22. The
total doping concentration of the first dopant atom A3 and the
second dopant atom A4 in the first polysilicon channel layer 14
ranges 10.sup.11.about.10.sup.15 atoms/cm.sup.2, or is larger than
1012 atoms/cm.sup.2. The second dopant atom A4 is a dopant atom
selected from the group consisting of helium (He), neon (Ne), argon
(Ar), krypton (Kr), xenon (Xe) and radon (Rn) and any combination
thereof. The second dopant atom A4 is a dopant atom selected from
the group consisting of carbon (C), silicon (Si), germanium (Ge),
tin (Sn) and lead (Pb) and any combination thereof. The second
dopant atom A4 can also be selected from the combination of inert
gases and the IV A group. The first dopant atom A3 and the second
dopant atom A4 can be the same or different. In the step 65, the
second dopant atom A4 can be used as a source of the dapant to be
doped inside the third polysilicon channel layer 24c according to
the ion implantation method. Then, proceed to the step 66 as shown
in FIG. 7H, the second mask 72 is removed.
[0051] An OLED display panel and a method of forming a polysilicon
channel layer thereof are disclosed in the above embodiments of the
invention. The design of disposing a dopant atom not selected from
the IIIA group and the VA group inside the polysilicon layer (such
as the polysilicon layer formed according to the ELA
crystallization technology) formed by applying heat treatment to
the crystallization of the amorphous silicon layer can uniform the
defects of the polysilicon layer. Therefore, the non-uniform
crystallization and defect of the polysilicon layer can be
improved, so that the polysilicon channel layer of each pixel TFT
has the same characteristics. As a result, each pixel TFT has the
same characteristics, preventing the OLED display panel from
generating line mura during operation, largely improving the
display quality of the OLED display panel.
[0052] While the invention has been described by way of example and
in terms of a preferred embodiment, it is to be understood that the
invention is not limited thereto. On the contrary, it is intended
to cover various modifications and similar arrangements and
procedures, and the scope of the appended claims therefore should
be accorded the broadest interpretation so as to encompass all such
modifications and similar arrangements and procedures.
* * * * *