U.S. patent application number 11/605552 was filed with the patent office on 2007-05-31 for method for manufacturing semiconductor device.
Invention is credited to Jeong Yel Jang.
Application Number | 20070122753 11/605552 |
Document ID | / |
Family ID | 38087950 |
Filed Date | 2007-05-31 |
United States Patent
Application |
20070122753 |
Kind Code |
A1 |
Jang; Jeong Yel |
May 31, 2007 |
Method for manufacturing semiconductor device
Abstract
A method for manufacturing a semiconductor device is provided.
The method includes forming a polysilicon layer on a semiconductor
substrate, forming an anti-reflection coating on the polysilicon
layer, forming a photoresist (PR) layer pattern on the
anti-reflection coating, etching the anti-reflection coating using
the PR layer pattern as a mask in capacitive coupled plasma (CCP)
equipment using CF.sub.4, Ar, and O.sub.2, so as to cause a
reaction by-product generated by etching the anti-reflect coating
to be deposited on sidewalls of the PR layer pattern, thereby
forming spacers, and etching the polysilicon layer using the PR
layer pattern and the spacers as a mask.
Inventors: |
Jang; Jeong Yel; (Suwon-si,
KR) |
Correspondence
Address: |
SALIWANCHIK LLOYD & SALIWANCHIK;A PROFESSIONAL ASSOCIATION
PO BOX 142950
GAINESVILLE
FL
32614-2950
US
|
Family ID: |
38087950 |
Appl. No.: |
11/605552 |
Filed: |
November 28, 2006 |
Current U.S.
Class: |
430/316 ;
257/E21.038; 257/E21.039; 257/E21.252; 257/E21.256; 257/E21.312;
257/E21.314; 430/313; 430/950 |
Current CPC
Class: |
G03F 7/40 20130101; H01L
21/0337 20130101; H01L 21/31138 20130101; H01L 21/32139 20130101;
H01L 21/31116 20130101; H01L 21/0338 20130101; H01L 21/32137
20130101; G03F 7/091 20130101 |
Class at
Publication: |
430/316 ;
430/313; 430/950 |
International
Class: |
G03F 7/26 20060101
G03F007/26 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 28, 2005 |
KR |
10-2005-0114311 |
Claims
1. A method for manufacturing a semiconductor device, the method
comprising: forming a polysilicon layer on a semiconductor
substrate; forming an anti-reflection coating on the polysilicon
layer; forming a photoresist (PR) layer pattern on the
anti-reflection coating; etching the anti-reflection coating using
the PR layer pattern as a mask, so as to cause a reaction
by-product generated by the etching of the anti-reflection coating
to be deposited on sidewalls of the PR layer pattern, thereby
forming spacers; and etching the polysilicon layer using the PR
layer pattern and the spacers as a mask.
2. The method as claimed in claim 1, further comprising removing
the reaction by-product from the polysilicon layer before etching
the polysilicon layer.
3. The method as claimed in claim 2, wherein the reaction
by-product is removed by ion sputtering.
4. The method as claimed in claim 3, wherein the ion sputtering
uses a reactive gas based on argon (Ar) and fluorocarbon.
5. The method as claimed in claim 3, wherein the ion sputtering
uses CF.sub.4 having a flow rate from 50 sccm to 200 sccm, and
argon (Ar) having a flow rate from 50 sccm to 200 sccm.
6. The method as claimed in claim 1, wherein the anti-reflection
coating is etched in capacitive coupled plasma (CCP) equipment.
7. The method as claimed in clam 6, wherein the anti-reflection
coating is etched under conditions of: Power from 500 W to 1000 W;
Duration from 10 seconds to 20 seconds; Pressure from 40 mT to 70
mT; and Flow rate from 60 sccm to 100 sccm CF.sub.4, from 100 sccm
to 150 sccm Ar, and from 5 sccm to 15 sccm O.sub.2.
8. The method as claimed in clam 6, wherein the anti-reflection
coating is etched using a plasma source spaced apart from the
semiconductor substrate by a distance from 20 mm to 30 mm.
9. The method as claimed in claim 1, wherein the spacers are formed
under conditions of: Power from 500 W to 1000 W; Duration from 15
seconds to 30 seconds; Pressure from 20 mT to 50 mT; and Flow rate
from 10 sccm to 30 sccm C.sub.5F.sub.8, from 2 sccm to 10 sccm
CH.sub.2F.sub.2, from 50 sccm to 100 sccm Ar, and from 0 sccm to 5
sccm O.sub.2.
10. The method as claimed in claim 1, wherein the spacers are
formed in CCP equipment using a plasma source is spaced apart from
the semiconductor substrate by a distance from 25 mm to 30 mm.
11. A method for manufacturing a semiconductor device, the method
comprising: forming a polysilicon layer on a semiconductor
substrate; forming an anti-reflection coating on the polysilicon
layer; forming a photoresist (PR) layer pattern on the
anti-reflection coating; etching the anti-reflection coating using
the PR layer pattern as a mask so as to cause a reaction by-product
generated by etching the anti-reflection coating to be deposited on
sidewalls of the PR layer pattern, thereby forming spacers, wherein
the etching is performed with capacitive coupled plasma (CCP)
equipment using CF.sub.4, Ar, and O.sub.2; and etching the
polysilicon layer using the PR layer pattern and the spacers as a
mask.
12. The method as claimed in claim 11, further comprising removing
the reaction by-product from the polysilicon layer before etching
the polysilicon layer by using a reactive gas based on argon (Ar)
and fluorocarbon by means of ion sputtering.
13. The method as claimed in claim 12, wherein the ion sputtering
uses CF.sub.4 and Ar.
14. The method as claimed in claim 11, wherein the spacers are
formed using C.sub.5F.sub.8, CH.sub.2F.sub.2, Ar, and O.sub.2.
Description
RELATED APPLICATION(S)
[0001] This application claims the benefit under 35 U.S.C.
.sctn.119(e), of Korean Patent Application Number 10-2005-0114311
filed Nov. 28, 2005, which is incorporated herein by reference in
its entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to a method for manufacturing
a semiconductor device.
BACKGROUND OF THE INVENTION
[0003] The critical dimensions (CD) of a semiconductor device are
the dimensions of the smallest features that can be formed during a
manufacturing process. Device scaling has resulted in an increased
integration density, which has resulted in a requirement for
manufacturing processes capable of decreasing the size of the CD. A
logic device has the critical dimension (CD) of a transistor in
inverse proportion to integration density.
[0004] When a floating gate pattern having a CD of 130 nm or less
is formed, the CD of the gate pattern as well as the CD of a space
between the neighboring gate lines is often reduced to 100 nm or
less.
[0005] In this case, in order to secure a depth of focus (DOF)
margin using a KrF light source of 248 nm, the thickness of a
photoresist (PR) layer must be thin. This gives rise to a trade-off
problem that the PR layer must maintain a minimum thickness
required when an etching process is performed. Without a sufficient
DOF margin, pattern defects such as pattern deformation, pattern
collapse, etc. occur.
[0006] One solution to this problem is to change manufacturing
processes by, for example, selecting a material for the PR layer
capable of using an ArF light source of 193 nm instead of the KrF
light source to form a polysilicon transistor. However, in this
case, it is also difficult to form a space between the neighboring
gate patterns up to the CD of 100 nm or less.
[0007] Hereinafter, a conventional method for manufacturing a
semiconductor device having a fine pattern using a KrF light source
will be described.
[0008] A conventional method for manufacturing a semiconductor
device will be described below with reference to the attached
figures.
[0009] FIGS. 1A through 1G are sectional views illustrating a
conventional method for manufacturing a semiconductor device.
[0010] Referring to FIG. 1A, a gate insulating layer 11, a
polysilicon layer 12, a first insulating layer 13, and a bottom
anti-reflection coating (BARC) 14 are deposited on a substrate
10.
[0011] Then, a photoresist (PR) layer is applied to an entire top
surface of the substrate 10 having the BARC 14, and is selectively
exposed and developed to form a PR layer pattern 15.
[0012] Here, the BARC 14 prevents a standing wave phenomenon. The
standing wave phenomenon occurs during the PR layer exposure
process, where light incident onto the substrate 10 interferes with
light reflected on the substrate 10. This interference, or standing
wave phenomenon, causes the pattern profile to be deteriorated
after exposure and development of the PR layer.
[0013] Referring to FIG. 1B, a BARC pattern 14a is formed by
selectively removing the BARC 14 using the PR layer pattern 15 as a
mask.
[0014] Referring to FIG. 1C, a first insulating layer pattern 13a
is formed by etching the first insulating layer 13 using the PR
layer pattern 15 as a mask.
[0015] Referring to FIG. 1D, after removing the PR layer pattern 15
and the BARC pattern 14a, a second insulating layer 16 is formed on
an entire top surface of the polysilicon layer 12 including the
first insulating layer pattern 13a.
[0016] Referring to FIG. 1E, the second insulating layer 16 is
etched back to form sidewall spacers 16a on sidewalls of the first
insulating layer pattern 13a. This etch-back process refers to a
process of etching a target material on a plane at the same
thickness by means of an anisotropic etching process.
[0017] Specifically, the second insulating layer 16 is etched so as
to be completely removed from flat upper portions of both the
polysilicon layer 12 and the first insulating layer pattern 13a,
and to only remain on the sidewalls of the first insulating layer
pattern 13a. In addition, often the sidewalls of the first
insulating layer pattern 13a are partially etched on upper sides
thereof.
[0018] Referring to FIG. 1F, a polysilicon layer pattern 12a is
formed by etching the polysilicon layer 12 using the first
insulating layer pattern 13a and the sidewall spacers 16a located
on the opposite sides of the first insulating layer pattern 13a as
a mask.
[0019] Referring to FIG. 1G, the first insulating layer pattern 13a
and the sidewall spacers 16a, which remain on the polysilicon layer
pattern 12a, are then removed.
[0020] The polysilicon layer pattern 12a formed in this way becomes
a pattern for gate lines or electrodes.
[0021] In this conventional method for manufacturing a
semiconductor device, the process may be complicated because the
deposition and etching processes are repeated several times.
Further, the number of pieces of equipment used increases because
of the number of processes performed.
SUMMARY OF THE INVENTION
[0022] Accordingly, there is provided a method for manufacturing a
semiconductor device, the method including: forming a polysilicon
layer on a semiconductor substrate, forming an anti-reflection
coating on the polysilicon layer; forming a photoresist (PR) layer
pattern on the anti-reflection coating; etching the anti-reflection
coating using the PR layer pattern as a mask so as to cause a
reaction by-product generated by the etching of the anti-reflection
coating to be deposited on sidewalls of the PR layer pattern,
thereby forming spacers; and etching the polysilicon layer using
the PR layer pattern and the spacers as a mask.
[0023] In another embodiment of the present invention, there is
provided a method for manufacturing a semiconductor device, the
method including: forming a polysilicon layer on a semiconductor
substrate; forming an anti-reflection coating on the polysilicon
layer; forming a photoresist (PR) layer pattern on the
anti-reflection coating; etching the anti-reflection coating using
the PR layer pattern as a mask so as to cause a reaction by-product
generated by etching the anti-reflection coating to be deposited on
sidewalls of the PR layer pattern, thereby forming spacers, where
the etching of the anti-reflection coating is performed with
capacitive coupled plasma (CCP) equipment using CF.sub.4, Ar, and
O.sub.2; and etching the polysilicon layer using the PR layer
pattern and the spacers as a mask.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] FIGS. 1A through 1G are sectional views illustrating a
conventional method for manufacturing a semiconductor device;
and
[0025] FIGS. 2A, 2B and 2C are sectional views illustrating a
method for manufacturing a semiconductor device in accordance with
an embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0026] Hereinafter, a method of manufacturing a semiconductor
device according to an exemplary embodiment of the present
invention will be described with reference to the accompanying
drawings.
[0027] FIGS. 2A, 2B and 2C are sectional views illustrating a
method for manufacturing a semiconductor device in accordance with
an embodiment of the present invention.
[0028] Referring to FIG. 2A, a gate insulating layer 101, a
polysilicon layer 102, and a bottom anti-reflection coating (BARC)
103 can be formed on a substrate 100.
[0029] Then, a photoresist (PR) layer can be applied to an entire
top surface of the substrate 100 having the BARC 103, and can be
selectively exposed and developed to form a PR layer pattern 104.
Here, the BARC 103 can be used to prevent a standing wave
phenomenon during the exposure process for the PR layer.
[0030] Referring to FIG. 2B, the BARC 103 can be selectively etched
using the PR layer pattern 104 as a mask to form a BARC pattern
103a. In one embodiment, during the etching process, a
C.sub.xF.sub.y based reaction by-product can be generated by the
etching process. The reaction by-product can be deposited on a top
surface or sidewalls of the PR layer pattern 104. The structure or
sidewalls formed by the reaction by-product deposited on the top
surface or sidewalls of the PR layer pattern 104 can increase the
actual critical dimension (CD) of the PR layer pattern 104. In a
specific embodiment, the reaction by-product can be allowed to be
deposited only on the top surface or the sidewalls of the PR layer
pattern 104, without being deposited on a top surface of the
polysilicon layer 102. If the reaction by-product product is
deposited on the top surface of the polysilicon layer 102, then the
polysilicon layer can be prevented from being etched during a
subsequent etching process because this deposition layer can
function as a mask when the polysilicon layer 102 is etched.
[0031] FIG. 2B shows the reaction by-product as being formed as
spacers 103b on sidewalls of the PR layer pattern 104 and the BARC
pattern 103a. Although not illustrated, the reaction by-product can
also be deposited on the top surface of the PR layer pattern
104.
[0032] In one embodiment, the process of etching the BARC 103 and
the process of forming the spacers 103b have the following
condition. The process of etching the BARC 103 and the process of
forming the spacers 103b can be performed using capacitive coupled
plasma (CCP) equipment, and the conditions of these processes can
be as follows.
[0033] First, the process of etching the BARC 103 to form the BARC
pattern 103a can be performed under the conditions of: Power from
500 W to 1000 W; Duration from 10 seconds to 20 seconds; Pressure
from 40 mT to 70 mT; and Flow rate from 60 sccm to 100 sccm
CF.sub.4, from 100 sccm to 150 sccm Ar, and from 5 sccm to 15 sccm
O.sub.2. In an embodiment, a distance between a plasma source (not
shown) and the substrate 100 in the CCP equipment can be set to a
range from 25 mm to 30 mm.
[0034] Then, the process of depositing the reaction by-product on
the PR layer pattern 104 can be performed under the conditions of:
Power from 500 W to 1000 W; Duration from 15 seconds to 30 seconds;
Pressure from 20 mT to 50 mT; and Flow rate from 10 sccm to 30 sccm
C.sub.5F.sub.8, from 2 sccm to 10 sccm CH.sub.2F.sub.2, from 50
sccm to 100 sccm Ar, and from 0 sccm to 5 sccm O.sub.2. In an
embodiment, a distance between a plasma source (not shown) and the
substrate 100 in the CCP equipment can be set to a range from 25 mm
to 30 mm.
[0035] The etch of the BARC 103, and the deposition of the reaction
by-product on the top surface and sidewalls of the PR layer pattern
104 can be performed in the CCP equipment by injecting a reactive
gas having reactivity with the BARC 103, applying radio frequency
(RF) power to generate plasma, and performing an etch by means of
radicals.
[0036] A residence time of the reaction by-product generated when
the etch is performed can be prolonged to increase a probability of
attaching the reaction by-product to the PR layer pattern 104, so
that the actual CD of the PR layer pattern after the deposition of
the reaction by-product becomes greater than that of the PR layer
pattern after the exposure process.
[0037] Thus, the polysilicon layer 102 for a gate can be etched
using the PR layer pattern 104 and sidewall spacers 103b as a
mask.
[0038] Referring to FIG. 2C, a gate electrode line 102a or a gate
electrode can be formed by etching the polysilicon layer 102 using
both the sidewall spacers 103b formed by the reaction by-product
and the PR layer pattern 104 as a mask.
[0039] Where the reaction by-product is deposited on the sidewalls
as well as the top surface of the PR layer pattern 104, the
deposited reaction by-product itself can act as a mask, and thus
hardly exerts an influence on the subsequent process, i.e. the
process of etching the polysilicon layer 102.
[0040] However, in the case in which the reaction by-product
remains a portion where the polysilicon layer 102 is to be etched,
the remaining reaction by-product can act as a mask in the
selective process of the polysilicon layer 102. Hence, the
polysilicon layer 102 to be etched may not be etched, and process
failures such as the bridge of a floating gate can occur.
[0041] Therefore, in a preferred embodiment, before the process of
etching the polysilicon layer 102, the reaction by-product, which
has been generated by etching the BARC 103 and has remained on the
polysilicon layer 102 can be removed completely.
[0042] According to one embodiment of the present invention, the
reaction by-product remaining on the polysilicon layer 102 can be
completely removed by ion sputtering using a reactive gas based on
argon (Ar) and fluorocarbon.
[0043] In a specific embodiment, the ion sputtering can be
performed using CF.sub.4 and Ar as the reactive gas under the
conditions of: Pressure from 1 mT to 10 mT; Source Power from 200 W
to 1000 W; Bias power from 20 W to 100 W; Duration from 3 seconds
to 20 seconds; and Flow rate from 50 sccm to 200 sccm CF.sub.4 and
from 50 sccm to 200 sccm Ar.
[0044] In this manner, after the reaction by-product remaining on
the polysilicon layer 102 is completely removed, the polysilicon
layer 102 can be etched using the PR layer pattern 104 and the
sidewall spacers 103b as a mask.
[0045] According to an embodiment of the present invention, the
process of etching the polysilicon layer 102 can be performed in
two steps. The first step can be performed under the conditions of:
Pressure from 1 mT to 10 mT; Source Power from 300 W to 1000 W;
Bias power from 50 W to 200 W; Duration from 30 seconds to 60
seconds; and Flow rate from 30 sccm to 70 sccm Cl.sub.2, from 150
sccm to 300 sccm HBr, and from 0 sccm to 20 sccm HeO.sub.2. The
second step can be performed under the conditions of: Pressure from
50 mT to 100 mT; Source Power from 500 W to 1000 W; Bias power from
30 W to 100 W; Duration from 40 seconds to 100 seconds; and Flow
rate from 300 sccm to 500 sccm HBr and from 5 sccm to 30 sccm
HeO.sub.2.
[0046] Subsequently, the PR layer pattern 104, the BARC pattern
103a underneath the PR layer pattern 104, and the sidewall spacers
103b can be removed. The remaining polysilicon layer pattern can be
an interconnection 102a. In embodiments, this interconnection can
serve as a gate line or a gate electrode.
[0047] In embodiments of this method for manufacturing a
semiconductor device, because the pattern is formed in a constant
pitch size, the actual CD of the width of the interconnection after
the etch is completed can be increased up to a range from about 100
nm to about 200 nm, compared to the CD of each pattern line (or the
width) of the PR layer pattern 104 after the exposure process is
performed.
[0048] Accordingly, the CD of a space between the interconnections
is possible to be formed having a width of 100 nm or less. In the
method for manufacturing a semiconductor device in accordance with
the present invention, the interconnection can be formed of a
polysilicon layer.
[0049] In embodiments, a dry etch for the anisotropic etch, and
particularly a plasma etch using plasma, can be performed when
holding a wafer in a plasma etching bath by flowing etching gas
selected for etching a particular layer on the wafer, and applying
a radio frequency (RF) field having high energy, so that the
gaseous molecules are excited to a high energy level, and react
with the layer, thereby etching the layer.
[0050] The plasma source can be one of most important factors, and
has recently undergone rapid changes. Particularly, a plasma source
tries to meet reciprocal requirements such as a high etch rate, a
high selectivity, a low damage, and so on. In order to meet these
requirements of the plasma source, a technique using capacitive
coupled plasma (CCP) and a technique using inductive coupled plasma
(ICP) have been developed.
[0051] In the method for manufacturing a semiconductor device in
accordance with the present invention, the equipment used to form
the sidewall spacers using the reaction by-product generated when
the BARC is etched can be CCP equipment. In a specific embodiment,
the CCP equipment makes use of a dipole ring magnetron (DRM).
[0052] In the method for manufacturing a semiconductor device in
accordance with the present invention, the exposure process can be
performed on the PR layer using a KrF light source of 248 nm. The
reaction by-product, generated when the BARC is etched, can be used
as a hard mask together with the PR layer pattern.
[0053] As such, without a precise light source, the etching process
can be performed so as to be able to form the gate pattern in which
the CD of the space between the neighboring lines (hereinafter,
referred to as a "line-to-line space CD") amounts to 100 nm or
less.
[0054] Accordingly, the number of processes can be reduced compared
to an existing process. Further, the process of manufacturing a
semiconductor device having a fine line-to-line space CD can be
performed without using a PR layer and equipment for an expensive
ArF light source.
[0055] A method for manufacturing a semiconductor device in
accordance with the present invention can have the following
effects.
[0056] When the reaction by-product generated from etching the BARC
is deposited on the top surface of the PR layer pattern without
being immediately removed, the reaction by-product can be formed
into a hard mask having a width greater than that of the PR layer
pattern. Then, the polysilicon layer below the PR layer pattern can
be etched using the formed hard mask to form a poly gate.
[0057] Thus, even if the PR layer and equipment for the KrF light
source of 248 nm is used to form a space of the poly gate having
the line-to-line space CD of 100 nm or less without using
high-resolution PR layer and equipment, the reaction by-product can
increase the narrow width of the PR layer pattern, which decreases
the line-to-line space.
[0058] This makes it possible to use the PR layer and equipment for
the KrF light source even though the design rule becomes small, and
thus the same or similar effect can be obtained without using the
expensive equipment (the PR layer and equipment for the ArF light
source).
[0059] Embodiments of the method for manufacturing a semiconductor
device in accordance with the present invention can reduce the
number of processes, and therefore reduce the number of possible
causes of defects that can take place when each process is
performed. Accordingly, the yield can be increased.
[0060] In a further embodiment, the reaction by-product that may
remain on the polysilicon layer can be completely removed prior to
the process of etching the polysilicon layer to form the gate, so
that process failures such as a floating gate bridge can be
prevented in advance.
* * * * *