U.S. patent application number 11/594077 was filed with the patent office on 2007-05-03 for semiconductor device and manufacturing method of the same.
This patent application is currently assigned to SANYO ELECTRIC CO., LTD.. Invention is credited to Osamu Ikeda, Toshiyuki Ohkoda.
Application Number | 20070096294 11/594077 |
Document ID | / |
Family ID | 33157209 |
Filed Date | 2007-05-03 |
United States Patent
Application |
20070096294 |
Kind Code |
A1 |
Ikeda; Osamu ; et
al. |
May 3, 2007 |
Semiconductor device and manufacturing method of the same
Abstract
This invention miniaturizes a package of a semiconductor device
and simplifies a manufacturing procedure to reduce a manufacturing
cost. A semiconductor wafer formed of a plurality of semiconductor
chips formed with MEMS devices and wiring thereof on front surface
thereof and a cap arrayed wafer disposed with a plurality of
sealing caps are attached to seal the MEMS devices in cavities
between them. Then, a plurality of via-holes is provided
penetrating through the semiconductor wafer to form embedded
electrodes therein, and bump electrodes are formed thereon. After
this procedure, this structure is cut along scribe lines to be
divided into each of packages.
Inventors: |
Ikeda; Osamu; (Gunma,
JP) ; Ohkoda; Toshiyuki; (Gunma, JP) |
Correspondence
Address: |
MORRISON & FOERSTER LLP
1650 TYSONS BOULEVARD
SUITE 300
MCLEAN
VA
22102
US
|
Assignee: |
SANYO ELECTRIC CO., LTD.
Osaka
JP
|
Family ID: |
33157209 |
Appl. No.: |
11/594077 |
Filed: |
November 8, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10855972 |
May 28, 2004 |
7154173 |
|
|
11594077 |
Nov 8, 2006 |
|
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Current U.S.
Class: |
257/704 ;
257/E27.151 |
Current CPC
Class: |
B81C 2203/0118 20130101;
H01L 2924/16235 20130101; H01L 27/1462 20130101; Y10S 257/924
20130101; B81B 7/007 20130101; H01L 27/14806 20130101; H01L
27/14618 20130101 |
Class at
Publication: |
257/704 |
International
Class: |
H01L 23/12 20060101
H01L023/12 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 6, 2003 |
JP |
2003-161634 |
Claims
1-10. (canceled)
11. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor wafer comprising a plurality of device
areas that are defined by scribe lines, each of the device areas
comprising device elements formed on a surface of the semiconductor
wafer; providing a cap arrayed wafer that includes a plurality of
concave portions formed therein; attaching the semiconductor wafer
and the cap arrayed wafer so that the device elements of a device
area of the semiconductor wafer are sealed in a corresponding
concave portion of the cap arrayed wafer; and dividing along the
scribe lines the attached semiconductor wafer and the cap arrayed
wafer into individual packages.
12. the method of claim 11, wherein the device elements of the
device area are sealed in vacuum.
13. The method of claim 11, wherein the device elements of the
device area are sealed in an inert gas.
14. The method of claim 11, further comprising forming a metal thin
film on inner surfaces of the concave portions so as to provide a
filter function of blocking or transmitting light having a
predetermined wavelength.
15. The method of claim 11, further comprising forming a via-hole
in the device area, forming an embedded electrode in the via-holes,
and forming a wiring connecting the embedded electrode and at least
one of the device elements.
16. The method of claim 11, further comprising back-grinding the
semiconductor wafer after attaching the cap arrayed wafer and the
semiconductor wafer.
17. The method of claim 11, further comprising back-grinding the
cap arrayed wafer after attaching the cap arrayed wafer and the
semiconductor wafer.
18. The method of claim 11, further comprising back-grinding the
semiconductor wafer and the cap arrayed wafer after attaching the
cap arrayed wafer and the semiconductor wafer.
Description
CROSS-REFERENCE OF THE INVENTION
[0001] This invention is based on Japanese Patent Application No.
2003-161634, the content of which is incorporated herein by
reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention:
[0003] The invention relates to a semiconductor device and a
manufacturing method thereof, particularly to a semiconductor
device in which devices to be sealed are sealed in a package and a
manufacturing method thereof.
[0004] 2. Description of the Related Art:
[0005] In recent years, a device using a micro electromechanical
system (hereafter, referred to as an MEMS device), a charge coupled
device (hereafter, referred to as a CCD) used as an image sensor
and so on, and a sensor electrically detecting infrared radiation
(hereafter, referred to as an IR sensor) are being developed.
[0006] These electronic devices or micro-sized mechanical devices
(hereafter, referred to as electronic devices) are formed on a
semiconductor chip and packaged. Such a package includes a can
package in which the electronic devices are sealed with a metal cap
and a ceramic package in which the electronic devices are sealed
with a ceramic cap.
[0007] Relating technologies are disclosed in the Japanese Patent
Application Publications Nos. Hei 11-351959, Hei 11-258055 and
2001-13156.
[0008] In a conventional package, however, a semiconductor chip
formed with devices to be sealed such as electronic devices and a
cap for sealing the devices to be sealed are independently prepared
and then assembled. This makes a mass-manufacturing procedure
complex, and accordingly increases a manufacturing cost.
Furthermore, a package size becomes large, resulting in an increase
in a mounting area of the package on a printed board.
SUMMARY OF THE INVENTION
[0009] The invention provides a semiconductor device and a
manufacturing method thereof which simplifies a manufacturing
procedure to reduce a manufacturing cost and reduces a package size
when electronic devices are packaged.
[0010] In a semiconductor device of the invention, a semiconductor
chip formed with devices to be sealed on its front surface is
attached with a sealing cap, the devices to be sealed being sealed
in a cavity formed of a space between the semiconductor chip and
the sealing cap. Here, the device to be sealed is an electronic
device such as an MEMS device, an IR sensor, and a CCD, or a
micro-sized mechanical device.
[0011] The semiconductor chip is formed with via-holes penetrating
therethrough. These via-holes are formed with embedded electrodes.
The embedded electrodes are connected with the devices to be sealed
through wiring. The embedded electrodes are connected with
electrodes for external connection.
[0012] In the invention, a plurality of sealing caps and
semiconductor chips of the semiconductor device are formed on
wafers, attached to each other, and divided into a plurality of
packages. This procedure can simplify a mass-manufacturing
procedure, and reduce a manufacturing cost of each of the
packages.
[0013] Furthermore, via-holes are provided penetrating through the
semiconductor chip of each of the packages and embedded electrodes
are formed therein, so that bump electrodes can be formed on a
bottom of the semiconductor chip. This can miniaturize the package
and reduce a mounting area of the package on a printed board.
[0014] Furthermore, a cavity for sealing devices to be sealed is
filled with an inert gas or kept vacuum so that life and
reliability of the sealed devices can be extended and improved.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1A is a plan view of a semiconductor device of a first
embodiment of the invention, and FIG. 1B is a cross-sectional view
of line X-X of FIG. 1A.
[0016] FIGS. 2A and 2B are plan views of a semiconductor wafer and
a cap arrayed wafer of the first embodiment of the invention.
[0017] FIGS. 3A, 3B and 3C are cross-sectional views for explaining
a manufacturing method of the semiconductor device of the first
embodiment of the invention.
[0018] FIG. 4A is a plan view of a semiconductor device of a second
embodiment of the invention, and FIG. 4B is a cross-sectional view
of line Y-Y of FIG. 4A.
DETAILED DESCRIPTION OF THE INVENTION
[0019] Next, a structure of a semiconductor device of a first
embodiment of the invention will be described with reference to
drawings.
[0020] FIG. 1A is a plan view of a semiconductor device of this
embodiment. FIG. 1B is a cross-sectional view along line X-X of
FIG. 1A.
[0021] A plurality of MEMS devices 11A as devices to be sealed
(e.g., a relay, a condenser, a coil or a motor) is formed in a
region SA (indicated by a dotted line) on a front surface of a
semiconductor chip 10A (e.g., silicon chip). This region SA
includes the MEMS devices 11A that function as a single device.
That is, these MEMS devices 11A are electronic and mechanical
components of a micro-sized mechanism such as a micro-machine.
[0022] Wiring 12 (e.g. made of Cu, Al, or Al alloy) connected with
these MEMS devices 11A is formed extending to a periphery of the
region SA. The wiring 12 is formed in a procedure of forming the
MEMS devices 11A on the semiconductor chip 10A, having a thickness
of about 1 .mu.m.
[0023] A plurality of via-holes 13 is formed right under end
portions of the wiring 12 formed extending to the periphery of the
region SA, penetrating through the semiconductor chip 10A. Each of
these via-holes 13 is formed with an embedded electrode 14 (e.g.,
made of Cu, Al or Al alloy) therein. The embedded electrodes 14 are
formed by a plating method or a sputtering method, and connected
with the wiring 12 of the MEMS devices 11A. Although the embedded
electrodes 14 are completely embedded in the via holes 13 in FIG.
1B, the embedded electrodes 14 can be partially embedded therein by
adjusting a plating time or a sputtering time.
[0024] The embedded electrodes 14 are formed with bump electrodes
15 (e.g. made of solder) on a back surface of the semiconductor
chip 10A. Accordingly, leads of the packaged semiconductor chip 10A
are not necessary to be drawn from sides of the semiconductor chip
10A, but can be drawn from the bottom of the semiconductor chip
10A, thereby realizing miniaturization of the package. This can
prevent increasing of a mounting area of the package on a printed
board.
[0025] The front surface of the semiconductor chip 10A is attached
with a sealing cap 20A made of a glass, a silicon, a ceramic or a
resin. The semiconductor chip lOA and the sealing cap 20A are
attached to each other with an adhesive made of an epoxy resin and
the like, with the front surface of the semiconductor chip 10A and
a concave portion 21A of the sealing cap 20A (inner surface of the
sealing cap 20A) facing each other.
[0026] A cavity CV is formed in a space between the front surface
of the semiconductor chip 10A and the concave portion 21A of the
sealing cap 20A. The MEMS devices 11A are sealed in this cavity CV.
The thickness d of the sealing cap 20A is approximately several ten
to several hundred .mu.m, the height h of the cavity CV is
approximately several to several ten .mu.m, although the embodiment
is not limited to these values.
[0027] The MEMS devices 11A formed on the front surface of the
semiconductor chip 10A are sealed in the cavity CV which is filled
with an inert gas (e.g., N.sub.2) or kept vacuum. This makes the
sealed MEMS devices 11A mechanically protected with the sealing cap
20A, and prevents the MEMS devices 11A from being exposed to air,
thereby preventing corrosion or degradation with oxidation thereof.
Therefore, life and reliability of the MEMS devices 11A formed on
the semiconductor chip 10A can be extended and improved.
[0028] When the sealing cap 20A is made of a glass or a silicon, a
surface of the concave portion 21A can be formed with a metal thin
film 22A having a filter function of blocking or transmitting light
having a predetermined wave length. Handling of such a filter made
of a metal thin film, which has been difficult to handle with its
low strength, can be facilitated by utilizing the cavity CV for
forming such a filter 22A on the surface of the concave portion 21A
of the sealing cap 20A.
[0029] Next, a description will be made on a structure formed with
the above described semiconductor chips 10A and sealing caps 20A
with reference to drawings.
[0030] FIG. 2A is a plan view of a semiconductor wafer 30A formed
of the plurality of the seinconductor chips 10A disposed in a
matrix.
[0031] The semiconductor wafer 30A is made of a semiconductor
material such as silicon. The plurality of the semiconductor chips
10A is partitioned with scribe lines L extending in row and column
directions. The MEMS devices 11A are formed in the region SA, in
each of the semiconductor chips 10A.
[0032] Although not shown, the wiring 12 is connected with each of
the MEMS devices 11A, extending to the periphery of the region
SA.
[0033] FIG. 2B is a plan view of a cap arrayed wafer 40A formed of
the above described sealing caps 20A disposed in a matrix.
[0034] The cap arrayed wafer 40A is made of a glass, a silicon, a
ceramic or a resin. Each of regions partitioned with scribe lines
L' is to face each of the semiconductor chips 10A when attached
thereto. These scribe lines L' of the cap arrayed wafer 40A are
formed in accordance with the scribe lines L of the semiconductor
wafer 30A. The two wafers 30A and 40A are attached so that the
scribe lines L' of the cap arrayed wafer 40A are aligned with the
scribe lines L of the semiconductor wafer 30A.
[0035] Furthermore, the concave portions 21A are formed on the cap
arrayed wafer 40A in the regions corresponding to the regions SA of
the semiconductor chips 10A. When the cap arrayed wafer 40A is made
of a glass, a silicon or a ceramic, the concave portion 21A is
formed by etching.
[0036] Alternatively, when the cap arrayed wafer 40A is made of a
resin, the cap arrayed wafer 40A is formed by injection molding to
have the plurality of the concave portions 21A.
[0037] Although the embedded electrodes 14 and the bump electrodes
15 serving as electrodes for external connection are connected with
the MEMS devices through the wiring 12 in the above described
semiconductor chips 10A and the semiconductor wafer 30A, the
embedded electrodes 14 and the bump electrodes 15 can be directly
connected with the MEMS devices 11A without through the wiring 12.
This is applied to a second embodiment described below.
[0038] Next, a semiconductor device manufacturing method of this
embodiment will be described with reference to drawings.
[0039] As shown in FIG. 3A, the semiconductor wafer 30A formed with
the MEMS devices and the wiring 12 (not shown) on its front surface
is prepared. The structure of the semiconductor wafer 30A is the
same as the structure shown in FIG. 2A.
[0040] Then, the cap arrayed wafer 40A having the plurality of the
concave portion 21A is prepared. The structure of the cap arrayed
wafer 40A is the same as the structure shown in FIG. 2B. When the
cap arrayed wafer 40A is made of a glass or a silicon, the surface
of the concave portion 21A can be formed with the metal thin film
22A having a filter fuiction of blocking or transmitting light
having a predetermined wavelength.
[0041] Then, the cap arrayed wafer 40A and the semiconductor wafer
30A are disposed to face the concave portions 21A of the cap
arrayed wafer 40A and the front surface of the semiconductor wafer
30A.
[0042] Next, as shown in FIG. 3B, the cap arrayed wafer 40A and the
semiconductor wafer 30A are attached with an adhesive made of an
epoxy resin or the like. At this time, each of the concave portions
21A of the cap arrayed wafer 40A faces each of the regions SA of
the semiconductor wafer 30A.
[0043] That is, the cavity CV is formed in a space between each of
the concave portions 21A of the cap arrayed wafer 40A and the front
surface of the semiconductor wafer 30A, and the MEMS devices 11A
are sealed in this cavity. At this time, the cap arrayed wafer 40A
and the semiconductor wafer 30A are attached in a vacuum atmosphere
to maintain the cavity CV in vacuum. Alternatively, the cap arrayed
wafer 40A and the semiconductor wafer 30A can be attached in an
inert gas (e.g., N.sub.2) atmosphere to fill the cavity CV with the
inert gas.
[0044] Then, the semiconductor wafer 30A is ground on its back
surface to make a thickness of the semiconductor wafer 30A several
ten to several hundred .mu.m, for example. Alternatively, this
back-grinding can be performed to the cap arrayed wafer 40A or both
the semiconductor wafer 30A and the cap arrayed wafer 40A.
[0045] Next, as shown in FIG. 3C, the plurality of the via-holes 13
is formed penetrating from the back surface to the front surface of
the semiconductor wafer 30A. An etching method or a laser beam
irradiating method can be used for forming these via-holes 13.
[0046] The embedded electrodes 14 (e.g., made of Cu, Al or Al
alloy) are formed in these via-holes 13 by a plating method or a
sputtering method. Furthermore, the embedded electrodes 14 on the
back surface of the semiconductor wafer 30 are formed with the bump
electrodes 15 (e.g., made of a solder). Although the bump
electrodes 15 are formed right under the embedded electrodes 14 in
the embodiment shown in FIG. 3C, the bump electrodes 15 can be
formed on a back-surface wiring connected with the embedded
electrodes 14.
[0047] After the above procedure, the attached cap arrayed wafer
40A and semiconductor wafer 30A are cut along the scribe lines L by
a dicing blade or laser beams to be divided into each of
packages.
[0048] As described above, the plurality of the packages is formed
from the cap arrayed wafer 40A and the semiconductor wafer 30A
simultaneously, thereby simplifying a mass-manufacturing procedure.
This reduces a manufacturing cost of each of the packages.
[0049] Although the MEMS device 11A is used as a device to be
sealed in the above described embodiment, an electronic device of
other kind (e.g. IR, sensor) can be used as a device to be
sealed.
[0050] Next, a structure of a semiconductor device of a second
embodiment of the invention will be described with reference to
drawings.
[0051] FIG. 4A is a plan view of the semiconductor device of this
embodiment. FIG. 4B is a cross-sectional view along line Y-Y of
FIG. 4A.
[0052] A CCD 11B as a device to be sealed is formed in a region SB
(indicated by a dotted line) for formation of a device to be sealed
on a front surface of a semiconductor chip 10B. The CCD 11B is used
as, for example, an image sensor. A logic circuit LGC for
controlling the CCD 11B is formed in other region for formation of
a device to be sealed, which is adjacent to the region SB, on the
semiconductor chip 10B.
[0053] Wiring 12 (e.g., made of Cu, Al or Al alloy) connected with
the CCD 11B and its logic circuit LGC is formed extending to a
periphery of the region SB and the logic circuit LGC. This wiring
12 is formed in a procedure of forming the CCD 11B and the logic
circuit LGC on the semiconductor chip 10B, having a thickness of
about 1 .mu.m.
[0054] Furthermore, a plurality of via-holes 13 is formed right
under end portions of the wiring 12 formed extending to the
periphery of the region SB, penetrating through the semiconductor
chip 10B. Each of the via-holes 13 is formed with an embedded
electrode 14 (e.g., made of Cu, Al or Al alloy). The embedded
electrodes 14 are formed by a plating method or a sputtering
method, and connected with the wiring 12 of the CCD 11B and the
logic circuit LGC.
[0055] The embedded electrodes 14 are formed with bump electrodes
15 (e.g., made of solder) on a back surface of the semiconductor
chip 10B. Accordingly, leads of the packaged semiconductor chip 10B
are not necessary to be drawn from sides of the semiconductor chip
10B, but can be drawn from the bottom of the semiconductor chip
10B, thereby realizing miniaturization of the package. This can
prevent increasing of a mounting area of the package on a printed
board.
[0056] A sealing cap 20B (e.g., made of glass, silicon, or resin)
is attached to the front surface of the semiconductor chip 10B. The
semiconductor chip 10B and the sealing cap 20B are attached, with
the region SB on the front surface of the semiconductor chip 10B
and the concave portion 21B of the sealing cap 20B facing each
other.
[0057] A cavity CV is formed in a space between the region SB on
the front surface of the semiconductor chip 10B and the concave
portion 21B of the sealing cap 20B. The CCD 12B is sealed in this
cavity CV. Here, the CCD 11B formed on the front surface of the
semiconductor chip 10B is sealed in the cavity CV which is filled
with an inert gas or kept in vacuum. This prevents the CCD 11B from
being exposed to air, thereby preventing corrosion or degradation
with oxidation thereof. Therefore, life and reliability of the CCD
11B formed on the semiconductor chip 10B can be extended and
improved.
[0058] On the region formed with the logic circuit LGC, a convex
portion (not shown) of the sealing cap 20B is attached without
forming the cavity CV.
[0059] The CCD 11B is thus sealed in the cavity CV in order to
prevent stresses generated by a difference in coefficient of
thermal expansion between a material of the sealing cap 20B and a
material of the semiconductor chip 10B from affecting the CCD 11B.
On the other hand, the logic circuit LGC is thus attached with the
convex portion of the sealing cap 20B thereon in order to increase
an attachment area of the sealing cap 20B for obtaining high
attachment strength.
[0060] When the sealing cap 20B is made of a glass or a silicon, a
surface of the concave portion 21B can be formed with a metal thin
film 22B having a filter function of blocking or transmitting light
having a predetermined wave length. Handling of such a filter made
of a metal thin film, which has been difficult to handle with its
low strength, can be facilitated by utilizing the cavity CV for
forming such a filter 22B on the surface of the concave portion 21B
of the sealing cap 20B.
[0061] Next, a structure formed with the plurality of the
semiconductor chips 10B and the sealing caps 20B on wafers will be
described with reference to FIGS. 2A and 2B.
[0062] The semiconductor chips 10B of this embodiment are
partitioned with scribe lines L and disposed in a matrix (not
shown), in a similar manner as in the semiconductor wafer 30A shown
in FIG. 2A. However, in this embodiment, the CCDs 11B are formed in
the region SB (corresponding to approximately a half of the regions
SA in FIG. 2A), and the logic circuits LGC (corresponding to
approximately another half of the regains SA in FIG. 2A) are formed
in positions adjacent the CCDs 11B. The wiring 12 (not shown) is
connected with each of the CCDs 11B and the logic circuits LGC,
extending to the periphery of the region SB and the region formed
with the logic circuit LGC.
[0063] The sealing caps 20B of this embodiment are partitioned with
scribe lines L' and disposed in a matrix similarly to the cap
arrayed wafer 40A shown in FIG. 2B (not shown). However, the
concave portions 21B are formed on the cap arrayed wafer 40A only
in regions corresponding to the regions SB (not shown) provided for
formation of a device to be sealed of the semiconductor chip 10B,
in each of the regions partitioned by the scribe lines L'.
[0064] The concave portion 21B is formed by etching when the cap
arrayed wafer 40A of this embodiment is made of a glass or silicon.
Alternatively, the concave portion 21B can be formed simultaneously
when the cap arrayed wafer 40A is formed by injection molding if
the cap arrayed wafer 40A is made of a resin.
[0065] The above described semiconductor wafer and cap arrayed
wafer of this embodiment are finally divided in each of the
packages through the same procedure of the manufacturing method as
that of the first embodiment.
[0066] Although the CCD 11B is used as a device to be sealed in the
above described embodiment, an electronic device of other kind can
be used as a device to be sealed.
* * * * *