U.S. patent application number 11/642583 was filed with the patent office on 2007-05-03 for substrate frame.
Invention is credited to Norio Takahashi.
Application Number | 20070096271 11/642583 |
Document ID | / |
Family ID | 34214166 |
Filed Date | 2007-05-03 |
United States Patent
Application |
20070096271 |
Kind Code |
A1 |
Takahashi; Norio |
May 3, 2007 |
Substrate frame
Abstract
A substrate frame includes an insulative board (10a) having a
pair of ear portions (13) extending along its longitudinal edges; a
plurality of wiring substrate regions (11) arranged on the
insulative board (10a) between the ear portions (13) at
predetermined intervals; and a plurality of grooves (18) provided
around said wiring substrate regions (11) from which wiring
patterns are removed.
Inventors: |
Takahashi; Norio; (Tokyo,
JP) |
Correspondence
Address: |
TAKEUCHI & KUBOTERA, LLP
SUITE 202
200 DAINGERFIELD ROAD
ALEXANDRIA
VA
22314
US
|
Family ID: |
34214166 |
Appl. No.: |
11/642583 |
Filed: |
December 21, 2006 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10911477 |
Aug 5, 2004 |
7171744 |
|
|
11642583 |
Dec 21, 2006 |
|
|
|
Current U.S.
Class: |
257/669 ;
257/672; 257/676; 257/E23.065; 29/827 |
Current CPC
Class: |
H01L 2224/32225
20130101; Y10T 29/4913 20150115; H05K 2201/09781 20130101; Y10T
428/24314 20150115; H01L 2924/01078 20130101; H01L 2924/00014
20130101; H05K 3/0052 20130101; H01L 2924/01079 20130101; H01L
2224/48227 20130101; H01L 24/73 20130101; H05K 2203/1545 20130101;
H05K 3/0097 20130101; H01L 24/48 20130101; H01L 2924/15311
20130101; H05K 2201/2009 20130101; H01L 2224/05554 20130101; H01L
23/4985 20130101; H01L 2224/48091 20130101; H01L 2924/10162
20130101; H01L 2924/181 20130101; H01L 2224/73265 20130101; Y10T
29/49146 20150115; H01L 2924/07802 20130101; H05K 2201/09063
20130101; Y10T 29/49121 20150115; H01L 2224/48091 20130101; H01L
2924/00014 20130101; H01L 2224/73265 20130101; H01L 2224/32225
20130101; H01L 2224/48227 20130101; H01L 2924/15311 20130101; H01L
2224/73265 20130101; H01L 2224/32225 20130101; H01L 2224/48227
20130101; H01L 2924/00 20130101; H01L 2224/73265 20130101; H01L
2224/32225 20130101; H01L 2224/48227 20130101; H01L 2924/00012
20130101; H01L 2924/15311 20130101; H01L 2224/73265 20130101; H01L
2224/32225 20130101; H01L 2224/48227 20130101; H01L 2924/00012
20130101; H01L 2924/07802 20130101; H01L 2924/00 20130101; H01L
2924/181 20130101; H01L 2924/00012 20130101; H01L 2924/00014
20130101; H01L 2224/45099 20130101; H01L 2924/00014 20130101; H01L
2224/45015 20130101; H01L 2924/207 20130101 |
Class at
Publication: |
257/669 ;
029/827; 257/676; 257/672 |
International
Class: |
H01L 23/495 20060101
H01L023/495 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 1, 2003 |
JP |
2003-308424 |
Claims
1. A substrate frame comprising: an insulative board having a pair
of ear portions extending along its longitudinal edges; a plurality
of wiring substrate regions arranged on said insulative board
between said ear portions at predetermined intervals; and a
plurality of grooves provided around said wiring substrate regions
from which wiring patterns are removed.
2. The substrate frame according to claim 1, wherein said grooves
are made by boundries of said wiring substrate regions.
3. The substrate frame according to claim 1, wherein said grooves
are made suitable for punching to provide individual semiconductor
devices.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional application of prior application Ser.
No. 10/911,477 filed Aug. 5, 2004.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a substrate frame for
connecting to external terminals the electrodes of semiconductor
chips mounted on the substrate frame and a method of making
semiconductor devices using the substrate frame.
[0004] 2. Description of the Related Art
[0005] Japanese patent application Kokai No. 11-87386 discloses
such a semiconductor device as shown in FIGS. 2(a) and 2(b),
wherein a semiconductor chip 2 is mounted on the first surface of a
wiring substrate 1 with a conductive or insulative adhesive 3, with
the circuit forming surface facing up. A plurality of pads or
connecting electrodes 1a and their wirings (not shown) are formed
on the first surface of the wiring substrate 1. The pads 1a are
exposed but the wirings and the other area are covered by a solder
resist. A plurality of wires 4 connect the pads 1a and the pads 2a
of the semiconductor chip 2. The semiconductor chip 2, the adhesive
3, and the wires 4 are covered by a resin such as epoxy resin.
[0006] A plurality of pads and their wirings are formed on the
second surface opposed to the first surface of the wiring substrate
1. Similarly to the first surface, the pads are exposed but the
wirings and the other area are covered by a solder resist. A
plurality of external terminals or solder balls 6 are joined to the
pads on the second surface. It is understood that the wirings on
the first and second surfaces are connected via through-holes.
[0007] How to make such a semiconductor device will be
described.
[0008] As shown in FIG. 2(c), a substrate frame 10 is prepared by
bonding a pair of copper foils on opposite surfaces of an
insulating board and forming a row of wiring substrate regions 11
at predetermined intervals on each surface. On each wiring
substrate, both the surfaces are etched to form wiring patterns
that include pads on the first and second surfaces of a wiring
substrate 1 (FIG. 2(a)) and through holes provided at predetermined
locations for connecting the wiring patterns on the first and
second surfaces. A nickel-gold (NiAu) electrolytic plating is
applied to the interiors of the through holes for connecting the
wiring patters and to the pads for increasing the bonding property
with the wires 4 and the solder balls 6. A solder resist is applied
to the wiring patterns and the other area but the pads.
[0009] A plurality of slits 12 are provided between the wiring
substrate regions 11 and have a length less than that of the wiring
substrate regions 11. A plurality of slits 14 are provided in the
ear portions 13 of the substrate frame 10 and have a length less
that that of the wiring substrate regions 11. These slits 12 and 14
are formed by a router process. A semiconductor chip 2 is bonded to
a central mounting area 11a of the wiring substrate region 11 with
a bond 3. Then, the pads 1a of the wiring substrate region 11 and
the pads 2a of the semiconductor chip 2 are connected with wires 4.
Then, the semiconductor chip 2, the bond 3, and the wires 4 within
a package area 11bare enclosed with a resinous mass 5. A plurality
of solder balls 6 are joined to the pads on the second surface of
the wiring substrate region 11. Finally, the ear portions at the
four corners of the wiring substrate region 11 are punched off to
provide individual semiconductor devices.
[0010] However, the conventional semiconductor device suffers from
the following disadvantages.
[0011] A pair of lead patters are formed between the wiring
substrate region 11 and the ear portion 13 of the substrate frame
10 for electroplating the wiring pattern. The punching at the four
corners of the wiring substrate region 11 can damage the cut face,
lowering the reliability. The punching may be replaced by cutting
the four corners with a rotary saw. The saw cutting, however,
requires cutting in the vertical and lateral directions, lowering
the productivity, especially, of large BGA.
SUMMARY OF THE INVENTION
[0012] Accordingly, it is an object of the invention to provide a
substrate frame having the improved productivity.
[0013] According to the invention there is provided a substrate
frame comprising an insulative board having a pair of ear portions
extending along its longitudinal edges; a plurality of wiring
substrate regions arranged on the insulative board between the ear
portions at predetermined intervals; and a plurality of grooves
provided around the wiring substrate regions from which wiring
patterns are removed.
[0014] The grooves may be made by boundaries of said wiring
substrate regions for punching to provide individual semiconductor
devices.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 is a plan view of a substrate frame according to the
first embodiment of the invention;
[0016] FIG. 2(a) is a perspective view of a conventional
semiconductor device;
[0017] FIG. 2(b) is a sectional view taken along line A-A of FIG.
2(a);
[0018] FIG. 2(c) is a plan view of a substrate frame for the
semiconductor device;
[0019] FIG. 3(a) is a plan view of a substrate frame according to
the second embodiment of the invention;
[0020] FIG. 3(b) is a sectional view taken along line B-B of FIG.
3(a).
DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment
[0021] In FIG. 1, a substrate frame 10A is provided to replace the
substrate frame 10 in FIG. 2(c). Similarly to the substrate frame
10, this frame 10A is made by bonding a pair of copper foils to
opposite surfaces of an insulative board and forming a row of
wiring substrate regions 11 at predetermined intervals on each
surface. The opposite surfaces of each wiring substrate region 11
are etched to form wiring patterns that include pads 1a and 1b on
the first and second surfaces of the wiring substrate 1 and
through-holes provided at predetermined locations for connecting
the wiring patterns on the first and second surfaces. The interiors
of the through-holes are plated to connect the wiring patterns but
a nickel-gold electrolytic plating is applied to the pads 1a and 1b
to increase the bonding property with the wires and solder balls. A
solder resist is coated on the wiring patterns and the other area
except for the pads 1a and 1b.
[0022] A plurality of slits 15 are provided between the wiring
substrate regions 11 of the substrate frame 10A and have a length
greater than that of the wiring substrate regions 11, extending
across the ear portions 13 of the substrate frame 10A. Thus, the
slits 15 separate the adjacent wiring substrate regions 11. These
slits 15 are made by a router process.
[0023] How to make semiconductor devices with the substrate frame
10A will be described below.
[0024] A plurality of semiconductor chips 2 are bonded to the
central mounting areas 11a of wiring substrate regions 11 with a
bond 3 (FIG. 2(a)). Then, the pads 1a of a wiring substrate region
11 and the pads 2a of a semiconductor chip 2 are connected with
bonding wires 4. Then, the semiconductor chip 2, the bond 3, and
the wires 4 within a package area 11bare enclosed with a resinous
mass 5. The solder balls 6 are joined to the pads 1b on the second
surface of the wiring substrate region 11. Then, the ear portions
13 of the substrate frame 10A are cut off with a rotary saw to
provide individual semiconductor devices.
[0025] As has been described above, the wiring substrate regions 11
of the substrate frame 10A are separated completely by the slits
15. Thus, it is possible to provide individual semiconductor
devices by cutting in only one direction without damage to the cut
surface.
Second Embodiment
[0026] In FIG. 3(a), a substrate frame 10B is used to replace the
substrate frame 10 of FIG. 2(c). Similarly to the substrate frame
10, this substrate frame 10B is made by bonding a pair of copper
foils to opposite surfaces of an insulative board 10a to form a
both sided substrate and forming thereon a row of wiring substrate
regions 11 at predetermined intervals. The copper foils 10b of the
both sided substrate are etched to form wiring patterns that
include pads 1a and 1b on the first and second surfaces of the
wiring substrate 1 and through-holes at predetermined locations for
connecting the wiring patterns on the first and second surfaces.
The interiors of the through-holes are plated to connect the wiring
patterns electrically.
[0027] Then, a solder resist 10c is coated over the wiring patterns
and the other areas except for the pads 1a and 1b, to which a
nickel-gold electrolytic plating is applied to increase the bonding
property with the wire and the solder balls. A plurality of slits
17 are formed between the wiring substrate regions 11 by a router
process to reduce the processing stress. A groove 18 is provided
around each wiring substrate region 11 by removing the copper foil
10b and the solder resist 10c in a predetermined width.
[0028] How to make semiconductor devices with the substrate frame
10B will be described below.
[0029] (1) A both sided substrate is prepared by bonding a pair of
copper foils 10b to opposite surfaces of an insulative board 10a.
The copper foils 10c on the opposite sides are etched by the
photolithographic technology to form wiring patterns that include
wiring substrate regions 11 provided at predetermined intervals.
The wiring patterns also include pads 1a and 1b, and lead patterns
for electrolytic plating.
[0030] (2) A plurality of through-holes are provided to connect the
wiring patterns on the opposite sides of the wiring substrate 1. A
plurality of holes 16 are provided in the ear portions 13 for
transportation. A solder resist 10c is coated to the area other
than the pads 1a and 1b and the grooves 18, and a nickel-gold
electrolytic plating is applied to the pads 1a and 1b.
[0031] (3) The area other than the groove 18 is covered with an
etching mask, and the wiring patter at the groove 18 (part of the
lead pattern for electrolytic plating) is removed by etching.
[0032] (4) The etching mask is removed, and slits 17 are formed
between the wiring substrate regions 11 by the router process to
complete the substrate frame 10B.
[0033] (5) A semiconductor chip 2 is bonded with a bond 3 to a
central mounting area 11a of the wiring substrate region 11, and
the pads 1a of the wiring substrate region 11 and the pad 2a of the
semiconductor chip 2 are connected with wires 4.
[0034] (6) The semiconductor chip 2, the bond 3, and the wires 4
within a package area 11bare enclosed with a resin 5. Solder balls
6 are joined to the pads 1b on the second surface of the wiring
substrate region 11.
[0035] (7) The grooves 18 of the wiring substrate regions 11 are
punched with a metal mold to provide individual semiconductor
devices.
[0036] As has been described above, the substrate frame 10B has the
grooves 18 from which the wiring patterns have been removed so that
individual semiconductor devices are separated without any damage
to the cut surfaces merely by punching the grooves 18.
[0037] The substrate frame 10A or 10B may be applied to a
multi-layer substrate having three or more wiring layers. The wire
bonding between the wiring substrate 1 and the semiconductor chip 2
may be replaced by the flip chip bonding.
* * * * *