U.S. patent application number 11/641845 was filed with the patent office on 2007-05-03 for method of forming self-aligned inner gate recess channel transistor.
This patent application is currently assigned to SAMSUNG ELECTRONICS CO., LTD. Invention is credited to Chang-Hyun Cho, Tae-Young Chung, Ji-Young Kim, Soo-Ho Shin.
Application Number | 20070096185 11/641845 |
Document ID | / |
Family ID | 36637663 |
Filed Date | 2007-05-03 |
United States Patent
Application |
20070096185 |
Kind Code |
A1 |
Kim; Ji-Young ; et
al. |
May 3, 2007 |
Method of forming self-aligned inner gate recess channel
transistor
Abstract
A self-aligned inner gate recess channel in a semiconductor
substrate includes a recess trench formed in an active region of
the substrate, a gate dielectric layer formed on a bottom portion
of the recess trench, recess inner sidewall spacers formed on
sidewalls of the recess trench, a gate formed in the recess trench
so that an upper portion of the gate protrudes above an upper
surface of the substrate, wherein a thickness of the recess inner
sidewall spacers causes a center portion of the gate to have a
smaller width than the protruding upper portion and a lower portion
of the gate, a gate mask formed on the gate layer, gate sidewall
spacers formed on the protruding upper portion of gate and the gate
mask, and a source/drain region formed in the active region of the
substrate adjacent the gate sidewall spacers.
Inventors: |
Kim; Ji-Young; (Yongin-city,
KR) ; Cho; Chang-Hyun; (Yongin-city, KR) ;
Shin; Soo-Ho; (Yongin-city, KR) ; Chung;
Tae-Young; (Yongin-city, KR) |
Correspondence
Address: |
LEE & MORSE, P.C.
3141 FAIRVIEW PARK DRIVE
SUITE 500
FALLS CHURCH
VA
22042
US
|
Assignee: |
SAMSUNG ELECTRONICS CO.,
LTD
Suwon-city
KR
|
Family ID: |
36637663 |
Appl. No.: |
11/641845 |
Filed: |
December 20, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10730996 |
Dec 10, 2003 |
7154144 |
|
|
11641845 |
Dec 20, 2006 |
|
|
|
Current U.S.
Class: |
257/301 ;
257/E21.205; 257/E21.429; 257/E29.135; 257/E29.267; 438/243 |
Current CPC
Class: |
H01L 29/42376 20130101;
H01L 29/66553 20130101; H01L 29/66621 20130101; H01L 29/7834
20130101; H01L 21/28114 20130101 |
Class at
Publication: |
257/301 ;
438/243 |
International
Class: |
H01L 29/94 20060101
H01L029/94; H01L 27/108 20060101 H01L027/108; H01L 29/76 20060101
H01L029/76; H01L 31/119 20060101 H01L031/119; H01L 21/8242 20060101
H01L021/8242 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 23, 2003 |
KR |
2003-0050459 |
Claims
1-14. (canceled)
15. A method of forming a self-aligned inner gate recess channel in
a semiconductor substrate, comprising: forming a recess trench in
an active region of the substrate; forming recess inner sidewall
spacers on sidewalls of the recess trench; forming a gate
dielectric on the bottom portion of the recess trench; forming a
gate in the recess trench so that an upper portion of the gate
protrudes above an upper surface of the substrate, wherein a
thickness of the recess inner sidewall spacers causes a center
portion of the gate to have a smaller width than the protruding
upper portion and a lower portion of the gate; forming a gate mask
on the gate; forming gate sidewall spacers on the protruding upper
portion of the gate and the gate mask; and performing an ion
implantation process to form a source/drain region in the active
region of the substrate adjacent the gate sidewall spacers.
16. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 64, further
comprising: enlarging the bottom portion of the recess trench,
prior to forming the recess inner sidewall spacers on sidewalls of
the recess trench.
17. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
source/drain region in the active region of the substrate is an
n.sup.+ source/drain region.
18. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
oxide mask layer has a thickness of about 200 .ANG..
19. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
poly mask is a poly hard mask.
20. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
poly mask layer is formed by a low pressure chemical vapor
deposition (LPCVD) process.
21. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
poly mask layer has a thickness of about 1000 .ANG..
22. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
substrate comprises: a shallow trench isolation region; and the
active region includes a well region, a threshold voltage control
region, and a source/drain region.
23. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 22, wherein the
shallow trench isolation region is formed to a depth of about 3000
.ANG..
24. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 22, wherein the
recess trench has a width at an opening thereof of about 900
.ANG..
25. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein
etching the poly mask layer, the oxide mask layer and the active
region of the substrate to form the recess trench comprises:
etching the poly mask layer using the photoresist layer as a mask
and removing the photoresist layer; and etching the active region
of the substrate using the etched poly mask layer as a mask to form
the recess trench and removing the poly mask layer.
26. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 16, wherein
enlarging the bottom portion of the recess trench is performed
using a chemical dry etching (CDE) process.
27. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
bottom portion of the recess trench is enlarged to a width of about
900 .ANG..
28. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
recess inner sidewall spacers have a thickness of about 200
.ANG..
29. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein
forming the recess inner sidewall spacers comprises: depositing a
spacer layer on the substrate and the recess trench using a LPCVD
process; and anisotropically etching the spacer layer to form the
recess inner sidewall spacers on the sidewalls of the recess
trench.
30. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
etching to increase the depth of the recess trench is an
anisotropic etching process.
31. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
depth of the recess trench is increased by about 300 .ANG..
32. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
total depth of the recess trench after increasing the depth of the
recess trench is between about 1300-1800 .ANG..
33. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
width of the bottom portion of the recess trench is enlarged using
a chemical dry etching (CDE) process.
34. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 16, wherein a
width of the bottom portion of the recess trench is enlarged to a
width of about 900 .ANG..
35. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
gate dielectric is selected from the group consisting of an oxide
layer, an oxynitride layer, an alumina (Al.sub.2O.sub.3) layer, and
a ruthenium oxide (RuO) layer.
36. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
gate dielectric is formed using a thermal oxidation process.
37. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
gate dielectric has a thickness of about 50 .ANG..
38. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, wherein the
gate is formed by depositing a gate layer using a LPCVD process and
etching the gate layer.
39. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate, as claimed in claim 15, wherein
forming the gate and forming the recess inner sidewall spacers
includes: forming and a first gate layer to partially fill a lower
portion of the recess trench; forming the recess inner sidewall
spacers on sidewalls of an upper portion of the recess trench above
the first gate layer; forming and a second gate layer on the first
gate layer in the recess trench so that an upper portion of the
second gate layer protrudes above an upper surface of the
substrate, wherein the thickness of the recess inner sidewall
spacers causes a lower portion of the second gate layer to have a
smaller width than the protruding upper portion of the second gate
layer and the first gate layer.
40. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 39, further
comprising: enlarging a bottom portion of the recess trench, prior
to forming the gate dielectric layer within the recess trench.
41.-47. (canceled)
48. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 39, wherein the
etching to form the recess trench is an isotropic etching
process.
49. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 39, wherein the
recess trench has a depth of about 1500 .ANG..
50. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 40, wherein the
enlarging the bottom portion of the recess trench is performed
using a chemical dry etching (CDE) process.
51. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 40, wherein the
lower width of the recess trench is enlarged to a width of about
900 .ANG..
52.-54. (canceled)
55. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 39, wherein the
first gate layer is a poly gate layer.
56. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 39, wherein the
first gate layer has a thickness of about 800 .ANG..
57. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 39, wherein
forming the first gate layer comprises: depositing a first gate
layer on the substrate and recess trench to fill the recess trench;
and performing an etchback process on the first gate layer until
the first gate layer remains only in the lower portion of the
recess trench.
58. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 57, wherein the
first gate layer is deposited using a LPCVD process.
59. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 39, wherein the
recess inner sidewall spacers have a thickness of about 200
.ANG..
60.-61. (canceled)
62. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 39, wherein the
second gate layer is a poly gate layer.
63. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 39, wherein the
second gate layer is formed by a LPCVD process.
64. The method of forming a self-aligned inner gate recess channel
in a semiconductor substrate as claimed in claim 15, further
comprising. removing a bottom portion of the recess trench to
increase a depth of the recess trench; and enlarging a width of the
bottom portion of the recess trench below the recess inner sidewall
spacers.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This is a divisional application based on pending
application Ser. No. 10/730,996, filed Dec. 10, 2003, the entire
contents of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a recess channel transistor
and a method of forming the same. More particularly, the present
invention relates to a self-aligned recess channel transistor
having an inner gate with a center portion that has a smaller width
than a protruding upper portion and a lower portion of the gate and
a method of forming the same.
[0004] 2. Description of the Related Art
[0005] Conventionally, a recess transistor is used to achieve a
higher density as a cell size is scaled down to the sub-micron
range. As a planar gate size narrows in a recess transistor,
however, short channel effects, junction leakage, and source/drain
breakdown voltage become significant issues. Conventional recess
gates have several disadvantages. A disadvantage of a conventional
recess transistor, for example, is a large gate oxide area, which
increases a gate loading capacitance. Additionally, another
disadvantage of a conventional recess transistor structure is a
deep junction depth, which increases a gate to source/drain overlap
capacitance and a bit line loading capacitance. A conventional
recess gate structure has a further disadvantage of having a weak
photo misalign margin.
SUMMARY OF THE INVENTION
[0006] In an effort to overcome at least some of the problems
described above, the present invention provides a self-aligned
recess channel transistor having a gate with a center portion that
has a smaller width than a protruding upper portion and a lower
portion of the gate and a method of forming the same.
[0007] It is a feature of an embodiment of the present invention to
provide a self-aligned inner gate recess channel in a semiconductor
substrate including a recess trench formed in an active region of
the substrate, a gate dielectric layer formed on a bottom portion
of the recess trench, recess inner sidewall spacers formed on
sidewalls of the recess trench, a gate formed in the recess trench
so that an upper portion of the gate protrudes above an upper
surface of the substrate, wherein a thickness of the recess inner
sidewall spacers causes a center portion of the gate to have a
smaller width than the protruding upper portion and a lower portion
of the gate, a gate mask formed on the gate layer, gate sidewall
spacers formed on the protruding upper portion of gate and the gate
mask, and a source/drain region formed in the active region of the
substrate adjacent the gate sidewall spacers.
[0008] Preferably, the recess trench has a width at an opening
thereof of about 900 .ANG. and a depth of between about 1300-1800
.ANG.. Preferably, the shallow trench isolation region has a depth
of approximately 3000 .ANG..
[0009] Preferably, the substrate includes a shallow trench
isolation region and the active region includes a well region, a
threshold voltage control region, and a source/drain region.
[0010] The gate dielectric layer may be an oxide layer, an
oxynitride layer, an alumina (Al2O3) layer, or a ruthenium oxide
(RuO) layer and have a thickness of about 50 .ANG..
[0011] Preferably, the recess inner sidewall spacers have a
thickness of about 200 .ANG. and are formed of either silicon oxide
or silicon nitride.
[0012] The gate formed in the recess trench may include a first
gate layer formed in a bottom portion of the recess trench and a
second gate layer formed on the first gate layer in an upper
portion of the recess trench, the second gate layer having a lower
portion within the recess trench and an upper portion that
protrudes above the upper surface of the substrate, wherein a
thickness of the recess inner sidewall spacers causes the lower
portion of the second gate layer to have a smaller width than the
protruding upper portion of the second gate layer and the first
gate layer. The first gate layer may be a poly gate layer and have
a thickness of about 800 .ANG.. The second gate layer may be a poly
gate layer.
[0013] Preferably, the source/drain region in the active region of
the substrate is an n+ source/drain region.
[0014] It is another feature of an embodiment of the present
invention to provide a method of forming a self-aligned inner gate
recess channel in a semiconductor substrate including sequentially
depositing an oxide mask layer, a poly mask layer, and a
photoresist layer on the substrate having an active region, etching
the poly mask layer, the oxide mask layer and the active region of
the substrate to form a recess trench, forming recess inner
sidewall spacers on sidewalls of the recess trench, etching a
bottom portion of the recess trench to increase a depth of the
recess trench, enlarging a width of the bottom portion of the
recess trench below the recess inner sidewall spacers, forming a
gate dielectric on the bottom portion of the recess trench, forming
a gate in the recess trench so that an upper portion of the gate
protrudes above an upper surface of the substrate, wherein a
thickness of the recess inner sidewall spacers causes a center
portion of the gate to have a smaller width than the protruding
upper portion and a lower portion of the gate, forming a gate mask
on the gate, forming gate sidewall spacers on the protruding upper
portion of the gate and the gate mask, and performing an ion
implantation process to form a source/drain region in the active
region of the substrate adjacent the gate sidewall spacers.
[0015] The method may further include enlarging a lower portion of
the recess trench, prior to forming the recess inner sidewall
spacers on sidewalls of the recess trench.
[0016] Preferably, etching the poly mask layer, the oxide mask
layer and the active region of the substrate to form the recess
trench includes etching the poly mask layer using the photoresist
layer as a mask and removing the photoresist layer and etching the
active region of the substrate using the etched poly mask layer as
a mask to form the recess trench and removing the poly mask
layer.
[0017] Preferably, forming the recess inner sidewall spacers
includes depositing a spacer layer on the substrate and the recess
trench using a LPCVD process and anisotropically etching the spacer
layer to form the recess inner sidewall spacers on the sidewalls of
the recess trench.
[0018] It is still another feature of an embodiment of the present
invention to provide a method of forming a self-aligned inner gate
recess channel in a semiconductor substrate including sequentially
depositing an oxide mask layer, a poly mask layer, and a
photoresist layer on the substrate having an active region, etching
the poly mask layer, the oxide mask layer and the active region of
the substrate to form a recess trench, forming a gate dielectric
layer within the recess trench, forming and etching a first gate
layer to partially fill a lower portion of the recess trench,
forming recess inner sidewall spacers on sidewalls of an upper
portion of the recess trench above the first gate layer, forming
and etching a second gate layer on the first gate layer to form a
gate in the recess trench so that an upper portion of the second
gate layer protrudes above an upper surface of the substrate,
wherein a thickness of the recess inner sidewall spacers causes a
lower portion of the second gate layer to have a smaller width than
the protruding upper portion of the second gate layer and the first
gate layer, forming a gate mask on the second gate layer, forming
gate sidewall spacers on the protruding upper portion of the second
gate layer and the gate mask, and performing an ion implantation
process to form a source/drain region in the active region of the
substrate adjacent the gate sidewall spacers.
[0019] The method may further include enlarging a lower portion of
the recess trench, prior to forming the recess inner sidewall
spacers on sidewalls of the recess trench.
[0020] Preferably, forming the first gate layer includes depositing
a first gate layer on the substrate and recess trench to fill the
recess trench and performing an etchback process on the first gate
layer until the first gate layer remains only in the lower portion
of the recess trench.
[0021] Preferably, forming the recess inner sidewall spacers
includes depositing a spacer layer on the substrate and the recess
trench using a LPCVD process and anisotropically etching the spacer
layer to form the recess inner sidewall spacers on the sidewalls of
the recess trench.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The above and other features and advantages of the present
invention will become more apparent to those of ordinary skill in
the art by describing in detail preferred embodiments thereof with
reference to the attached drawings in which:
[0023] FIG. 1 illustrates a top view of a layout of a self-aligned
recess channel transistor according to a first embodiment of the
present invention;
[0024] FIGS. 2 through 11 illustrate cross-sectional views of
stages in a method of forming self-aligned inner gate recess
channel transistor according to the first embodiment of the present
invention, wherein FIGS. 2 through 9 and 11 illustrate
cross-sectional views taken along line I-I' of FIG. 1 and FIG. 10
illustrates a cross-sectional view taken along line II-II' of FIG.
1;
[0025] FIG. 12 illustrates a top view of a layout of a self-aligned
recess channel transistor according to a second embodiment of the
present invention;
[0026] FIGS. 13 through 22 illustrate cross-sectional views of
stages in a method of forming a self-aligned inner gate recess
channel transistor according to the second embodiment of the
present invention, wherein FIGS. 13 through 20 and 22 illustrate
cross-sectional views taken along line I-I' of FIG. 12 and FIG. 21
illustrates a cross-sectional view taken along line II-II' of FIG.
12.
DETAILED DESCRIPTION OF THE INVENTION
[0027] The present invention will now be described more fully
hereinafter with reference to the accompanying drawings, in which
preferred and alternate embodiments of the invention are shown. The
invention may, however, be embodied in different forms and should
not be construed as limited to the embodiments set forth herein.
Rather, these embodiments are provided so that this disclosure will
be thorough and complete, and will fully convey the scope of the
invention to those skilled in the art. In the drawings, the
thickness of layers and regions are exaggerated for clarity. It
will also be understood that when a layer is referred to as being
"on" another layer or substrate, it can be directly on the other
layer or substrate, or intervening layers may also be present. Like
reference numerals and characters refer to like elements
throughout.
First Embodiment
[0028] FIG. 1 illustrates a top view of a layout of a self-aligned
recess channel transistor according to a first embodiment of the
present invention. FIGS. 2 through 11 illustrate cross-sectional
views of stages in a method of forming a self-aligned inner gate
recess channel transistor according to the first embodiment of the
present invention. More specifically, FIGS. 2 through 9 and 11
illustrate cross-sectional views taken along line I-I' of FIG. 1
and FIG. 10 illustrates a cross-sectional view taken along line
II-II' of FIG. 1.
[0029] FIG. 1 illustrates a gate layer 122 formed over an active
area 108 and a field area 102 of a semiconductor substrate. FIG. 1
includes cross-sectional lines I-I' and II-II' taken along an
x-direction and a y-direction, respectively, of the semiconductor
substrate.
[0030] Referring now to FIG. 2, FIG. 2 illustrates a
cross-sectional view, taken along line I-I' of FIG. 1, of an
initial stage in the method of forming the self-aligned inner gate
recess channel transistor according to the first embodiment of the
present invention. A substrate 100, including a well region 104, is
provided. Preferably, the well region 104 is formed using an ion
implantation process. A shallow trench isolation (STI) region 102
is conventionally formed by anisotropically etching a trench and
filling the trench with an insulation layer. The STI region 102
forms a field area of the semiconductor substrate. Preferably, the
STI trench has a depth of about 3000 .ANG.. Threshold voltage (Vt)
control ions are implanted by an ion implantation process on the
well region 104 to form a Vt control region 106. Subsequently,
source/drain (S/D) ions are implanted by an ion implantation
process to form a source/drain (S/D) region 108. The source/drain
(S/D) region 108 forms an active area of the semiconductor
substrate. Preferably, the source/drain (S/D) region 108 is an N-
source/drain (S/D) region.
[0031] Referring to FIG. 3, an oxide mask layer 110 is formed on
the active area 108 and the field area 102. Preferably, the oxide
mask layer 110 is formed to a thickness of about 200 .ANG.. Next, a
poly mask layer 112 is formed on the oxide mask layer 110 using a
low-pressure chemical vapor deposition (LPCVD). Preferably, the
poly mask layer 112 is a ploy hard mask layer and is formed to a
thickness of about 1000 .ANG.. A recess pattern is then formed on
the poly mask layer 112 by depositing a photoresist 114 and
performing a photolithographic process.
[0032] Referring to FIG. 4, a first recess hole 116 is formed in
the active area 108 using a two-step isotropical etching process.
In a first step, the poly hard mask 112 is etched using the
photoresist (114 of FIG. 3) as a mask and then the photoresist is
removed using a photoresist stripping process. In a second step,
the active area 108 of the substrate is etched using the etched
poly hard mask (114 of FIG. 3) as a pattern to form the first
recess hole 116. Subsequently, the poly hard mask 112 is removed.
Preferably, the first recess hole 116 has a depth of about 1000
.ANG..
[0033] In FIG. 5, an optional etching process is performed to
enlarge a width of a lower portion of the first recess hole 116.
The etching process may use a chemical dry etch (CDE) process. The
first recess hole 116 is preferably enlarged by a thickness of
about 200 .ANG.. Preferably, a width of an opening of the first
recess hole 116 is about 900 .ANG..
[0034] Referring to FIG. 6, a spacer layer is deposited on the
sides of the first recess hole 116, the active area 108, and the
field area 102 using a LPCVD process. The spacer layer is then
anisotropically etched to form a recess inner oxide spacer 118.
Preferably, the recess inner oxide spacer 118 has a thickness of
about 200 .ANG.. Although the inner spacer 118 is described as an
inner oxide spacer, the spacer layer may be formed of either
silicon oxide (SiO) or silicon nitride (SiN).
[0035] As shown in FIG. 7, a second recess hole 117 is formed by
anisotropically etching a bottom of the first recess hole 116 below
the recess inner oxide spacer 118. Preferably, the second recess
hole 117 has a depth of about 300 .ANG.. A width L1 of the first
recess hole 116 and the second hole recess 117 is approximately 500
.ANG..
[0036] Referring to FIG. 8, the initial width L1 of the second
recess hole 117 is enlarged using a chemical dry etching (CDE)
process. Preferably, the enlarged width L2 of the second recess
hole 117 is increased to a width of about 900 .ANG.. A final total
recess depth of the first recess hole 116 and the second recess
hole 117 is preferably about 1300-1800 .ANG..
[0037] As shown in FIG. 9, a gate dielectric layer 120 is formed on
sidewalls of the second recess hole 117. The gate dielectric layer
120 may be an oxide layer, an oxynitride layer, an alumina (Al2O3)
layer, or a ruthenium oxide (RuO) layer. The gate dielectric layer
120 may be formed using a thermal oxidation process. Preferably,
the gate dielectric layer 120 has a thickness of about 50 .ANG..
Subsequently, a gate layer and a gate mask layer are formed on the
active area 108, the field area 102, and the first recess hole 116
using a LPCVD process. A gate 122 and a gate mask 124 are then
formed using photolithography and an etching process. An upper
portion 125 of the gate 122, which additionally includes the gate
mask 124, protrudes above an upper surface of the substrate.
[0038] FIG. 10 illustrates a cross-sectional view, taken along line
II-II' of FIG. 1, of the stage in the method of forming the recess
gate shown in FIG. 9. FIG. 10 further illustrates a thickness L3 of
the recess inner oxide spacer 118, which is preferably 200
.ANG..
[0039] FIG. 11 illustrates a completed structure of a recess
channel according to the first embodiment the present invention. As
shown in FIG. 11, a gate spacer layer is deposited on the gate mask
124, the active area 108 and the field area 102. The gate spacer
layer is then anisotropically etched to form a sidewall spacer 128
on the gate 122 and the gate mask 124. Subsequently, source/drain
(S/D) ions 130 are implanted using an ion implantation process on
the active area 108 to form an S/D region 130. Preferably, the S/D
ions are N+ ions implanted to form an N+ S/D region.
[0040] In the first embodiment of the present invention, a recess
inner oxide spacer is a relatively thick oxide layer, which
decreases a gate loading capacitance and a bit line loading
capacitance, thereby increasing a refresh time. In addition, the
recess inner oxide spacer improves the photo misalign margin and
reduces a S/D junction capacitance, thereby increasing a device
speed.
Second Embodiment
[0041] FIG. 12 illustrates a top view of a layout of a self-aligned
recess channel transistor according to a second embodiment of the
present invention. FIGS. 13 through 22 illustrate cross-sectional
views of stages in a method of forming a self-aligned inner gate
recess channel transistor according to the second embodiment of the
present invention. More specifically, FIGS. 13 through 20 and 22
illustrate cross-sectional views taken along line I-I' of FIG. 12
and FIG. 21 illustrates a cross-sectional view taken along line
II-II' of FIG. 12.
[0042] FIG. 12 illustrates a gate layer 222 formed over an active
area 208 and a field area 202 of a semiconductor substrate. FIG. 12
includes cross-sectional lines I-I' and II-II' taken along an
x-direction and a y-direction, respectively, of the semiconductor
substrate.
[0043] Referring to FIG. 13, FIG. 13 illustrates a cross-sectional
view, taken along line I-I' of FIG. 12, of an initial stage in the
method of forming the self-aligned inner gate recess channel
transistor according to the second embodiment of the present
invention. A substrate 200, including a well region 204, is
provided. Preferably, the well region 204 is formed using an ion
implantation process. A shallow trench isolation (STI) region 202
is conventionally formed by anisotropically etching a trench and
filling the trench with an insulation layer. The STI region 202
forms a field area of the semiconductor substrate. Preferably, the
STI trench has a depth of about 3000 .ANG.. Threshold voltage (Vt)
control ions are implanted by an ion implantation process on the
well region 204 to form a Vt control region 206. Subsequently,
source/drain (S/D) ions are implanted by an ion implantation
process to form a source/drain (S/D) region 208. The source/drain
(S/D) region 208 forms an active area of the semiconductor
substrate. Preferably, the source/drain (S/D) region 208 is an N-
source/drain (S/D) region.
[0044] Referring to FIG. 14, an oxide mask layer 210 is formed on
the active area 208 and the field area 202. Preferably, the oxide
mask layer 210 is formed to a thickness of about 200 .ANG.. Next, a
poly mask layer 212 is formed on the oxide mask layer 210 using a
low-pressure chemical vapor deposition (LPCVD). Preferably, the
poly hard mask layer 212 is a poly hard mask and is formed to a
thickness of about 1000 .ANG.. A recess pattern is then formed on
the poly mask layer 212 by depositing a photoresist 214 and
performing a photolithographic process.
[0045] Referring to FIG. 15, a recess hole 216 is formed in the
active area 208 using an isotropical etching process. Preferably,
the recess hole 216 has a depth of about 1500 .ANG. and a width at
an opening of about 900 .ANG.. Subsequently, the photoresist (214
of FIG. 14) is removed using a photoresist stripping process.
[0046] In FIG. 16, an optional etching process is performed to
enlarge a width of a lower portion of the recess hole 216. The
etching process may be a chemical dry etch (CDE) process. The
recess hole 216 is preferably enlarged to a width of about 900
.ANG..
[0047] As shown in FIG. 17, a gate dielectric layer 217 is formed
on sidewalls of the recess hole 216. The gate dielectric layer 217
may be an oxide layer, an oxynitride layer, an alumina (Al2O3)
layer, or a ruthenium oxide (RuO) layer. The gate dielectric layer
217 may be formed using a thermal oxidation process. Preferably,
the gate dielectric layer 217 has a thickness of about 50
.ANG..
[0048] Referring to FIG. 18, a first poly gate layer 219 is
deposited in the recess hole 216 using an LPCVD process and an
etchback process. After the etchback process, the first poly gate
layer 219 preferably has a remaining thickness of about 800
.ANG..
[0049] As shown in FIG. 19, a spacer layer is deposited on the
sides of the recess hole 216, the active area 208, and the field
area 202 using a LPCVD process. The spacer layer is then
anisotropically etched to form a recess inner oxide spacer 218.
Preferably, the recess inner oxide spacer 218 has a thickness of
about 200 .ANG.. Although the inner spacer 218 is described as an
inner oxide spacer, the spacer layer may be formed of either
silicon oxide (SiO) or silicon nitride (SiN).
[0050] Subsequently, as shown in FIG. 20, a gate layer and a gate
mask layer are formed on the active area 208, the field area 202,
and the recess hole 216 using a LPCVD process. A gate 222 and a
gate mask 224 are then formed using photolithography and an etching
process. An upper portion 225 of the gate 222, which additionally
includes the gate mask 224, protrudes above an upper surface of the
substrate.
[0051] FIG. 21 illustrates a cross-sectional view, taken along line
II-II' of FIG. 12, of the stage in the method of forming the recess
gate shown in FIG. 20.
[0052] FIG. 22 illustrates a completed structure of a recess
channel according to the second embodiment the present invention.
As shown in FIG. 22, a gate spacer layer is deposited on the gate
mask 224, the active area 208 and the field area 202. The gate
spacer layer is then anisotropically etched to form a sidewall
spacer 228 on the gate 222 and the gate mask 224. Subsequently,
source/drain (S/D) ions are implanted using an ion implantation
process on the active area 208 to form an S/D region 230.
Preferably, the S/D ions are N+ ions implanted to form an N+ S/D
region.
[0053] By way of comparison, whereas the first embodiment of the
present invention discloses a two-step etching process to form the
recess hole and a single step deposition process to form the gate,
the second embodiment of the present invention discloses a single
step etching process to form the recess hole and a two-step
deposition process to form the gate.
[0054] Similar to the first embodiment of the present invention, in
the second embodiment, a recess inner oxide spacer is a relatively
thick oxide layer, which decreases a gate loading capacitance and a
bit line loading capacitance, thereby increasing a refresh time. In
addition, the recess inner oxide spacer improves the photo misalign
margin and reduces a S/D junction capacitance, thereby increasing a
device speed.
[0055] Preferred embodiments of the present invention have been
disclosed herein and, although specific terms are employed, they
are used and are to be interpreted in a generic and descriptive
sense only and not for purpose of limitation. Accordingly, it will
be understood by those of ordinary skill in the art that various
changes in form and details may be made without departing from the
spirit and scope of the present invention as set forth in the
following claims.
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