U.S. patent application number 11/292004 was filed with the patent office on 2007-04-05 for method of saving power consumed by a storage system.
Invention is credited to Yoichi Mizuno.
Application Number | 20070079063 11/292004 |
Document ID | / |
Family ID | 37903200 |
Filed Date | 2007-04-05 |
United States Patent
Application |
20070079063 |
Kind Code |
A1 |
Mizuno; Yoichi |
April 5, 2007 |
Method of saving power consumed by a storage system
Abstract
Provided is a method of saving power consumed by a storage
system that is connected to a host computer via a network,
including a disk device for storing to be written data requested by
the host computer, and controllers that control access to the disk
device, in which the controllers each have an interface connected
to the network, a processor connected to the interface, and a
memory connected to the processor, in which the processor measures
a load of the storage system, and in which the processor controls
power to the controllers in accordance with the measured load of
the storage system.
Inventors: |
Mizuno; Yoichi; (Yokohama,
JP) |
Correspondence
Address: |
MATTINGLY, STANGER, MALUR & BRUNDIDGE, P.C.
1800 DIAGONAL ROAD
SUITE 370
ALEXANDRIA
VA
22314
US
|
Family ID: |
37903200 |
Appl. No.: |
11/292004 |
Filed: |
December 2, 2005 |
Current U.S.
Class: |
711/112 ;
711/170; 713/320 |
Current CPC
Class: |
G06F 3/0625 20130101;
G06F 3/0653 20130101; G06F 3/067 20130101; G06F 3/0634 20130101;
Y02D 10/00 20180101 |
Class at
Publication: |
711/112 ;
711/170; 713/320 |
International
Class: |
G06F 12/00 20060101
G06F012/00; G06F 1/32 20060101 G06F001/32 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 3, 2005 |
JP |
2005-289941 |
Claims
1. A method of saving power consumed by a storage system that is
connected to a host computer via a network, wherein the storage
system has a disk device for storing to be written data requested
by the host computer, and plural controllers that control access to
the disk device, wherein the controllers each have an interface
connected to the network, a processor connected to the interface,
and a memory connected to the processor, wherein the processor
measures a load of the storage system, and wherein the processor
controls power to the controllers in accordance with the measured
load of the storage system.
2. The method of saving power consumed by a storage system
according to claim 1, wherein the memory stores controller count
control information, which indicates the association between the
load of the storage system and the count of operating controllers,
wherein, based on the controller count control information and the
measured load of the storage system, the processor determines the
number of controllers that are to be put into operation, and
wherein the processor controls power to the controllers in a manner
that puts the determined number of controllers into operation.
3. The method of saving power consumed by a storage system
according to claim 1, wherein the host computer recognizes a
storage area of the disk device on a logical storage area basis,
and wherein, prior to turning off power to one of the controllers,
the processor allocates a logical storage area allocated to this
controller whose power is to be turned off to another
controller.
4. The method of saving power consumed by a storage system
according to claim 1, wherein the host computer recognizes a
storage area of the disk device on a logical storage area basis,
and wherein, as the power is turned on in one of the controllers,
the processor allocates a logical storage area allocated to another
controller to the controller whose power is turned on.
5. The method of saving power consumed by a storage system
according to claim 1, wherein the processor controls power to the
controllers in accordance with an instruction given from the host
computer.
6. The method of saving power consumed by a storage system
according to claim 1, wherein the memory stores mode management
information, which indicates the association between the load of
the storage system and an operation mode of the controllers, and
wherein, based on the measured load and the mode management
information, the processor determines which operation mode is to be
employed by the controllers.
7. The method of saving power consumed by a storage system
according to claim 6, wherein one operation mode differs from other
operation modes in at least one of drive frequency of the
processor, count of operating processors, and count of cores that
are operating in each processor.
8. A method of saving power consumed by a storage system that is
connected to a host computer via a network, wherein the storage
system has a disk device for storing to be written data requested
by the host computer, and plural controllers that controls access
to the disk device, wherein the controller has an interface
connected to the network, a processor connected to the interface,
and a memory connected to the processor, wherein the memory stores
mode management information, which indicates the association
between a load of the storage system and an operation mode of the
controller, wherein the processor measures the load of the storage
system, and wherein, based on the measured load and the mode
management information, the processor determines which operation
mode is to be employed by the controller.
9. The method of saving power consumed by a storage system
according to claim 8, wherein one operation mode differs from
another operation mode in at least one of drive frequency of the
processor, count of operating processors, and count of cores that
are operating in each processor.
10. The method of saving power consumed by a storage system
according to claim 8, wherein the load of the storage system
includes at least one of a activity ratio of the processor, a
activity ratio of the interface, and a data transfer rate of the
controller.
11. The method of saving power consumed by a storage system
according to claim 8, wherein the storage system has plural
controllers, and wherein the processor controls power to the
controllers in accordance with the measured load of the storage
system.
12. A storage system accessed by a host computer, comprising: a
disk device to store to be written data requested by the host
computer; and plural controllers that control access to the disk
device, wherein the controllers each have: a measuring unit which
measures a load of the storage system; and a power control unit
which controls power to the controllers in accordance with the load
of the storage system measured by the measuring unit.
13. The storage system according to claim 12, wherein the
controllers stores controller count control information, which
indicates the association between the load of the storage system
and the count of operating controllers, wherein, based on the
controller count control information and the load of the storage
system measured by the measuring unit, the power control unit
determines the number of controllers that are to be put into
operation, and wherein the power control unit controls power to the
controllers in a manner that puts the determined number of
controllers into operation.
14. The storage system according to claim 12, wherein the host
computer recognizes a storage area of the disk device on a logical
storage area basis, wherein each controller has an access control
unit which controls allocation of the logical storage area, and
wherein, prior to shutting off power to one of the controllers, the
access control unit allocates a logical storage area allocated to
this controller whose power is to be turned off to another
controller.
15. The storage system according to claim 12, wherein the host
computer recognizes a storage area of the disk device on a logical
storage area basis, wherein each controller has an access control
unit which controls allocation of the logical storage area, and
wherein, as the power is turned on in one of the controllers, the
access control unit allocates a logical storage area allocated to
another controller to the controller whose power is turned on.
16. The storage system according to claim 12, wherein the power
control unit controls power to the controllers in accordance with
an instruction given by the host computer.
17. The storage system according to claim 12, wherein the load of
the storage system includes at least one of a activity ratio of the
processor, a activity ratio of the interface, and a data transfer
rate of the controllers.
18. The storage system according to claim 12, wherein the
controllers store mode management information, which indicates the
association between the load of the storage system and an operation
mode of the controllers, and wherein, based on the measured load
and the mode management information, the power control unit
determines which operation mode is to be employed by the
controllers.
19. The storage system according to claim 18, wherein one operation
mode differs from other operation modes in at least one of drive
frequency of the controller, count of operating controllers, and
count of cores that are operating in each controller.
Description
CLAIM OF PRIORITY
[0001] The present application claims priority from Japanese patent
application P2005-289941 filed on Oct. 3, 2005, the content of
which is hereby incorporated by reference into this
application.
BACKGROUND
[0002] This invention relates to a storage system that receives a
write request from a host computer and more specifically to a
technique for reducing power consumption of the storage system.
[0003] Storage systems are increasingly becoming larger and larger
in terms of storage area capacity. Such large-scale storage systems
have problems of increased power consumption and increased heat
generation.
[0004] As a countermeasure, techniques for reducing power
consumption of storage systems have been disclosed (see JP
2000-293314 A, for example). A storage system according to JP
2000-293314 A cuts off the power to a disk device which has not
been accessed by a host computer for a given period of time. The
storage system thus reduces power consumption of a disk device that
is not being accessed by a host computer.
SUMMARY
[0005] The prior art described above enables a storage system to
reduce power consumption of a disk device, but not the power
consumption of a controller that controls access to the disk
device. In other words, conventional controllers for a storage
system have a problem of keeping consuming power even when the
storage system is not being accessed by a host computer.
[0006] Also, conventionally, storage systems run all controllers
even when a load is far smaller than their processing abilities.
Conventional storage systems thus have a problem of constantly
consuming a given amount of power irrespective of the magnitude of
the load.
[0007] This invention has been made in view of the above, and it is
therefore an object of this invention to reduce power consumption
of a storage system.
[0008] According to an embodiment of this invention, there is
provided a method of saving power consumed by a storage system that
is connected to a host computer via a network, including a disk
device for storing to be written data requested by the host
computer, and controllers that control access to the disk device,
in which the controllers each have an interface connected to the
network, a processor connected to the interface, and a memory
connected to the processor, in which the processor measures a load
of the storage system, and in which the processor controls power to
the controllers in accordance with the measured load of the storage
system.
[0009] According to the embodiment of this invention described
above, the reduction of the power consumption of the storage system
can be attained.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The present invention can be appreciated by the description
which follows in conjunction with the following figures,
wherein:
[0011] FIG. 1 is a block diagram of a computer system according to
a first embodiment of this invention;
[0012] FIG. 2 is a block diagram of a controller of the storage
system according to the first embodiment of this invention;
[0013] FIG. 3 is a block diagram of the controller of the storage
system according to the first embodiment of this invention;
[0014] FIG. 4 is a configuration diagram of a mode management
table, which is included in the controller according to the first
embodiment of this invention;
[0015] FIG. 5 is a configuration diagram of a threshold management
table, which is included in the controller according to the first
embodiment of this invention;
[0016] FIG. 6 is a flow chart for power saving mode switching
processing of the controller according to the first embodiment of
this invention;
[0017] FIG. 7 is a block diagram of a controller of a storage
system according to a second embodiment of this invention;
[0018] FIG. 8 is a configuration diagram of a controller count
control table, which is included in the controller according to the
second embodiment of this invention;
[0019] FIG. 9 is a flow chart for operating controller count
changing processing according to the second embodiment of this
invention;
[0020] FIG. 10 is a block diagram of a computer system according to
a third embodiment of this invention;
[0021] FIG. 11 is a configuration diagram of a power saving mode
switching request, which is sent by a power instruction program
according to the third embodiment of this invention;
[0022] FIG. 12 is a block diagram of a computer system according to
a fourth embodiment of this invention;
[0023] FIG. 13 is a configuration diagram of a host computer-side
threshold management table, which is included in a host computer
according to the fourth embodiment of this invention; and
[0024] FIG. 14 is a flow chart for operating controller count
changing processing according to the fourth embodiment of this
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0025] Embodiments of this invention will be described below with
reference to the accompanying drawings.
First Embodiment
[0026] FIG. 1 is a block diagram of a computer system according to
a first embodiment of this invention.
[0027] The computer system includes a storage system 1, a host
computer 2, a management console 3 and a network 4.
[0028] The host computer 2 is a computer equipped with a CPU, a
memory, and an interface. The host computer 2 executes programs
stored in the memory, to thereby execute various types of
processing. For example, the host computer 2 stores data in the
storage system 1.
[0029] The storage system 1 has a controller 11, a disk device, and
a path 13. The controller 11 controls, as will be described later
with reference to FIG. 2, the storage system 1. The controller 11
also inputs and outputs data to and from the disk device. The disk
device stores data sent from the host computer. The path 13
connects the controller 11 and the disk device to each other.
[0030] The host computer 2 recognizes the storage area of the disk
device on a logical volume (LU) basis. One or more LUs, which are
denoted by 12, are built in the storage system 1.
[0031] The management console 3 is a computer equipped with a CPU,
a memory, and an interface. The management console 3 executes
programs stored in the memory, to thereby execute various types of
processing. One of the programs stored in the memory of the
management console 3 is a management program 31. The management
console 3 executes the management program 31 stored in the memory
to manage the storage system 1.
[0032] The management console 3 is connected to the storage system
1 via, for example, a LAN. The management console 3 which, in this
block diagram, is connected directly to the storage system 1, may
be connected via the network 4 to the storage system 1.
[0033] The network 4 is, for example, a SAN (Storage Area Network),
and connects the storage system 1 to the host computer 2.
[0034] FIG. 2 is a block diagram of the controller 11 of the
storage system 1 according to the first embodiment of this
invention.
[0035] The controller 11 has a memory 111, a CPU 112, a host
computer interface (host computer IF) 113, a disk interface (disk
IF) 114, a management interface (management IF) 115, a data
transfer control unit 116 and a cache memory 117.
[0036] The memory 111 stores a power control program 1110, a mode
management table 1111, a threshold management table 1112, a
performance monitoring program 1113 and an access control program
1115.
[0037] The power control program 1110 controls the power of the
controller 11. The power control program 1110 also causes the
controller 11 to switch from one power saving mode to another. A
power saving mode is a mode of operation adjusted to reduce power
consumption of the controller 11.
[0038] The mode management table 1111 manages, as will be described
later with reference to FIG. 4, the association between a power
saving mode of the controller 11 and how the components of the
controller 11 operates. The threshold management table 1112
manages, as will be described later with reference to FIG. 5, the
association between a power saving mode of the controller 11 and
the magnitude of the load applied to the components of the
controller 11.
[0039] The performance monitoring program 1113 monitors the load of
the storage system 1.
[0040] The access control program 1115 controls access to the LUs
12. For instance, the access control program 1115 changes which of
the controllers 11 accesses the LUs 12.
[0041] The CPU 112 executes programs stored in the memory 111, to
thereby execute various types of processing. The CPU 112 has one or
more cores 1121. The core 1121 is an arithmetic circuit. The more
cores 1121 the CPU 112 has, the more data the CPU 112 can process.
The controller 11 shown in FIG. 2 has one CPU 112, but may have
plural CPUs 112.
[0042] The host computer IF 113 is an interface connected to the
host computer 2. The controller 11 shown in FIG. 2 has two host
computer IFs 113, but may have as many host computer IFs 113 as
necessary. Each host computer IF 113 has one or more ports.
[0043] The disk IF 114 is an interface connected to the disk
device. The controller 11 shown in FIG. 2 has two disk IFs 114, but
may have as many disk IFs 114 as necessary. Each disk IF 114 has
one or more ports.
[0044] The management IF 115 is an interface connected to the
management console 3.
[0045] Examples of interfaces that are employable as the host
computer IF 113, the disk IF 114 and the management IF 115 include
Fibre Channel, SCSI (Small Computer System Interface), iSCSI
(Internet Small Computer System Interface), Infiniband, SATA
(Serial ATA), and SAS (Serial Attached SCSI).
[0046] The cache memory 117 temporarily stores data sent from the
host computer 2. Having the cache memory 117, the controller 11 can
access the LUs 12 at high speed. The cache memory 117 may be a part
of the storage area of the memory 111.
[0047] The data transfer control unit 116 controls data transfer
among the CPU 112, the host computer IF 113, the disk IF 114 and
the cache memory 117. An LSI, for example, can serve as the data
transfer control unit 116.
[0048] Next, a configuration for the controller 11 that is
different from the one shown in FIG. 2 will be described.
[0049] FIG. 3 is a block diagram of the controller 11 of the
storage system 1 according to the first embodiment of this
invention.
[0050] The control 11 shown in FIG. 3 is a modified example of the
controller 11 shown in FIG. 2. The storage system 1 of this
embodiment can have either the controller 11 of FIG. 2 or the
controller 11 of FIG. 3.
[0051] In the controller 11 of FIG. 3, the host computer IF 113 and
the disk IF 114 each have the CPU 112. Another difference is that a
connection control unit 118 controls data transfer among the memory
111, the host computer IF 113, the disk IF 114 and the cache memory
117. This way the memory 111 and the cache memory 117 are shared by
all the CPUs 112.
[0052] The rest of the configuration of the controller 11 shown in
FIG. 3 is the same as that of the controller 11 shown in FIG. 2,
and therefore will not be described here.
[0053] Whichever of the two configurations, one illustrated in FIG.
2 and the other illustrated in FIG. 3, the controller 11 takes,
power consumption is reduced by the same processing.
[0054] FIG. 4 is a configuration diagram of the mode management
table 1111 in the controller 11 according to the first embodiment
of this invention.
[0055] The mode management table 1111 includes a power saving mode
number 1111A and operation details 1111B.
[0056] The power saving mode number 1111A indicates an identifier
unique to each power saving mode of the controller 11. The
operation details 1111B describe how the components of the
controller 11 operate in this particular power saving mode
identified by the power saving mode number 1111A.
[0057] The mode management table 1111 shown in this configuration
diagram includes information concerning the CPU 112, the cache
memory 117, the host computer IF 113, the disk IF 114, and various
buses.
[0058] First, a description of power saving modes will be given
focusing on the CPU 112 in the controller 11.
[0059] When the power saving mode number 1111A is "0", every CPU
112 in the controller 11 uses all of its resources and operates at
its highest possible drive frequency and maximum possible drive
voltage.
[0060] When the power saving mode number 1111A is "1", the CPU 112
operates at a given drive frequency that is lower than the highest
possible drive frequency. When the power saving mode number 1111A
is "2", the CPU 112 operates while running only a given reduced
count of cores 1121. When the power saving mode number 1111A is
"3", a given count of CPUs 112 in the controller 11 stop operating.
When the power saving mode number 1111A is "4", all of the CPUs 112
in the controller 11 stop operating.
[0061] Additionally, the drive frequency of the CPU 112 may be
changed in stages in accordance with switching made from one power
saving mode to another.
[0062] A power saving mode may be defined by the combination of how
much change is made to the drive frequency of the CPU 112 and how
much change is made to the count of operating CPUs 112. Similarly,
a power saving mode may be defined by the combination of how much
change is made to the drive frequency of the CPU 112 and how much
change is made to the count of operating cores 1121.
[0063] Next, a description on power saving modes will be given
focusing on the cache memory 117 in the controller 11. When the
power saving mode number 1111A is "0", the cache memory 117
operates at its highest possible drive frequency.
[0064] When the power saving mode number 1111A is "1", the cache
memory 117 operates at a given drive frequency that is lower than
the highest possible drive frequency. When the power saving mode
number 1111A is "4", the cache memory 117 stops operating.
[0065] The drive frequency of the cache memory 117 may be changed
in stages in accordance with switching made from one power saving
mode to another.
[0066] Next, a description on power saving modes will be given
focusing on the host computer IF 113 in the controller 11. When the
power saving mode number 1111 A is "0", every host computer IF 113
in the controller 11 uses all of its resources and operates at its
highest possible transfer rate.
[0067] When the power saving mode number 1111A is "1", the host
computer IF 113 operates at a given transfer rate that is lower
than the highest possible transfer rate.
[0068] When the power saving mode number 1111A is "2", the host
computer IF 113 operates while reducing the count of operating
ports to a given count.
[0069] Specifically, the CPU 112 searches ports operating in the
host computer IF 113 for ports to which no LUs 12 are allocated. In
other words, the CPU 112 searches for ports that are not being used
by the host computer 2. In the case where the CPU 112 cannot find
ports that are not being used by the host computer 2, allocation of
the LUs 12 to ports is changed to create ports that are not
available for use by the host computer 2. The CPU 112 then shuts
off power to the ports that are not being used by the host computer
2.
[0070] When the power saving mode number 1111A is "3", a given
count of the host computers IF 113 in the controller 11 stop
operating.
[0071] Specifically, the CPU 112 searches host computer IF 113 in
the controller 11 for ports to which no LUs 12 are allocated. In
other words, the CPU 112 searches for host computer IF 113 that are
not being used by the host computer 2. In the case where the CPU
112 cannot find host computer IF 113 that are not being used by the
host computer 2, allocation of the LUs 12 to ports is changed to
create host computer IF 113 that are not available for use by the
host computer 2. The CPU 112 then shuts off power to the host
computer IF 113 that are not being used by the host computer 2.
[0072] When the power saving mode number 1111A is "4", every host
computer IF 113 in the controller 11 stops operating. Specifically,
the CPU 112 shuts off power to every host computer IF 113 in the
controller 11.
[0073] Next, a description on power saving modes will be given
focusing on the disc IF 114 in the controller 11. When the power
saving mode number 1111A is "0", every the disc IF 114 in the
controller 11 operates at its highest possible drive frequency by
using all its links.
[0074] When the power saving mode number 1111A is "1", the disc IF
114 operates at a given drive frequency that is lower than the
highest possible drive frequency.
[0075] When the power saving mode number 1111A is "2", the disc IF
114 reduces the number of links of transmission circuits to a
predetermined number and operates.
[0076] Specifically, the CPU 112 searches links in the disk IF 114
for links that are connected to only inactive disk devices. The CPU
112 then shuts off power to the found links.
[0077] When the power saving mode number 1111A is "3", a given
number of the disk IFs 114 in the controller 11 stops
operating.
[0078] Specifically, the CPU 112 searches disk IF 114 in the disk
IF 114that are connected to only inactive disk devices. The CPU 112
then shuts off power to the found disk IF 114.
[0079] When the power saving mode number 1111A is "4", every disc
IF 114 in the controller 11 stops operating. Specifically, the CPU
112 shuts off power to every disc IF 114 in the controller 11.
[0080] Next, a description on power saving modes will be given
focusing on the buses in the controller 11. When the power saving
mode number 1111A is "0", the data transfer control unit 116 in the
controller 11 operates at its highest possible drive frequency.
This raises the data transfer rate of the buses in the controller
11 to the maximum.
[0081] When the power saving mode number 1111A is "1", the data
transfer control unit 116 operates at a given drive frequency that
is lower than the highest possible drive frequency. This lowers the
data transfer rate of the buses in the controller 11.
[0082] When the power saving mode number 1111A is "4", the data
transfer control unit 116 stops operating.
[0083] A power saving mode may be defined by combining the
operation details mentioned above.
[0084] FIG. 5 is a configuration diagram of the threshold
management table 1112 in the controller 11 according to the first
embodiment of this invention.
[0085] The threshold management table 1112 includes a power saving
mode number 1112A and operation conditions 1112B.
[0086] The power saving mode number 1112A indicates an identifier
unique to each power saving mode of the controller 11. The
operation conditions 1112B describe conditions that the components
of the controller 11 fulfill in this particular power saving mode
identified by the power saving mode number 1112A. Specifically, the
magnitude of the load applied to the controller 11 and like other
conditions are stored as the operation conditions 1112B.
[0087] When the activity ratio of the CPU 112 is more than 60%, the
CPU 112 operates in a power saving mode that has a power saving
mode number "0" as the power saving mode number 1112A. When the
activity ratio of the CPU 112 is more than 40% and less than 60%,
the CPU 112 operates in a power saving mode that has a power saving
mode number "1" as the power saving mode number 1112A.
[0088] When the activity ratio of the CPU 112 is 20% or more and
less than 40%, the CPU 112 operates in a power saving mode that has
a power saving mode number "2" as the power saving mode number
1112A. When the activity ratio of the CPU 112 is more than 0% and
less than 20%, the CPU 112 operates in a power saving mode that has
a power saving mode number "3" as the power saving mode number
1112A. When the activity ratio of the CPU 112 is 0%, the CPU 112
operates in a power saving mode that has a power saving mode number
"4" as the power saving mode number 1112A.
[0089] Alternatively, a power saving mode in terms of the CPU 112
in the threshold management table 1112 may be defined by other
thresholds than the activity ratio of the CPU 112, for example, the
data processing rate of the controller 11.
[0090] When the activity ratio of the cache memory 117 is more than
50%, the cache memory 117 operates in a power saving mode that has
a power saving mode number "0" as the power saving mode number
1112A. When the activity ratio of the cache memory 117 is more than
0% and less than 50%, the cache memory 117 operates in a power
saving mode that has a power saving mode number "1", as the power
saving mode number 1112A. When the activity ratio of the cache
memory 117 is 0%, cache memory 117 operates in a power saving mode
that has a power saving mode number "4", as the power saving mode
number 1112A.
[0091] Alternatively, a power saving mode in terms of the cache
memory 117 in the threshold management table 1112 may be defined by
other thresholds than the activity ratio of the cache memory 117,
for example, the data processing rate of the controller 11.
[0092] In this threshold management table 1112, a power saving mode
in terms of the host computer IF 113 is defined in accordance with
the proportion of the maximum data transfer rate (data transferring
ability) of the host computer IF 113 to the data processing rate of
the controller 11.
[0093] A case in which the controller 11 has four host computer IFs
113 will be described as an example. The four host computer IFs 113
each has a data transfer ability of 1 GB/s. Accordingly, the
combined data transfer ability of all the host computer IFs 113 in
the controller 11 is 4 GB/s. The data processing rate of the
controller 11 in a certain period of time is 1 GB/s, meaning that
only 25% of the combined data transfer ability of the four host
computer IFs 113 is put to use. Therefore, it is sufficient that
one out of the four host computer IFs 113 operates. In other words,
the controller 11 can afford to stop the remaining three host
computer IFs 113 from operating.
[0094] To a power saving mode entailing these details, a user
assigns a power saving mode number "3". The user then enters
information about this power saving mode in the mode management
table 1111 and the threshold management table 1112.
[0095] Specifically, a record having "3" as the power saving mode
number 1112A is picked up from the threshold management table 1112,
and "25% or less" is stored in a host computer IF cell of the
operation conditions 1112B of the chosen record.
[0096] Next, a record having "3", as the power saving mode number
1111A is picked up from the mode management table 1111, and "IF
count=1" is stored in a host computer IF cell of the operation
details 1111B of the chosen record.
[0097] With the power saving mode thus defined, the CPU 112 shuts
off power to three of the host computer IFs 113 when the proportion
of the combined data transfer ability of all the host computer IFs
113 to the data processing rate of the controller 11 becomes 25% or
less.
[0098] Alternatively, a power saving mode in terms of the host
computer IF 113 in the threshold management table 1112 may be
defined by other thresholds such as the activity ratio of the host
computer IF 113.
[0099] A power saving mode in the threshold management table 1112
is defined in terms of the disk IF 114 and the various buses in
addition to the host computer IF 113.
[0100] Having the threshold management table 1112 as this, the
controller 11 can change the count of operating components, such as
host computer IFs and disk IFs, to suit the current data processing
rate.
[0101] Two types of thresholds, one for an increase in power
consumption and the other for a reduction in power consumption, may
be defined in the threshold management table 1112. This enables the
controller 11 to deal with rapid changes in data processing
amount.
[0102] In the mode management table 1111 and the threshold
management table 1112, a power saving mode is defined in terms of
the host computer IF 113 and in terms of the disk IF 114
separately. This is because the host computer IF 113 does not
always need the same data transfer rate as the disk IF 114. The
separate definition enables the controller 11 to stop some of the
disk IFs 114 from operating while running all of the host computer
IFs 113. Similarly, it enables the controller 11 to stop some of
the host computer IFs 113 from operating while running all of the
disk IFs 114. In short, the controller 11 can shut off power to one
type of interface independently of another type of interface, and
power consumption can thus be reduced even more.
[0103] FIG. 6 is a flow chart for power saving mode switching
processing of the controller 11 according to the first embodiment
of this invention.
[0104] The controller 11 periodically performs the power saving
mode switching processing.
[0105] The performance monitoring program 1113 periodically
measures the load of the controller 11 (Step 601). Specifically,
the performance monitoring program 1113 measures loads listed as
the operation conditions 1112B in the threshold management table
1112. For example, in the case where the controller 11 has the
threshold management table as shown in FIG. 5, the performance
monitoring program 1113 measures the activity ratio of the CPU 112,
the activity ratio of the cache memory 117, and the data processing
rate of the controller 11.
[0106] Then the power control program 1110 chooses from the
threshold management table 1112 a record entry whose operation
conditions 1112B match the results of the measurement by the
performance monitoring program 1113. From the chosen record entry,
the power saving mode number 1112A is extracted (Step 602). The
power control program 1110 extracts the power saving mode number
1112A for each component of the controller 11.
[0107] The extracted power saving mode number 1112A is compared
with a power saving mode number that is currently set to each
component of the controller 11, to thereby judge whether or not the
power saving mode set to the component needs to be switched to
another power saving mode (Step 603). The power control program
1110 judges, for each component of the controller 11, whether to
switch power saving modes.
[0108] Judging that there is no need to switch power saving modes,
the power control program 1110 ends the power saving mode switching
processing.
[0109] On the other hand, when it is judged that the current power
saving mode has to be switched, a switch is made to another power
saving mode. Specifically, the power control program 1110 chooses
from the mode management table 1111 a record entry whose power
saving mode number 111A matches the extracted power saving mode
number 1112A. From the chosen record entry, the operation details
1111B are extracted. The power control program 1110 then gives
instructions to the components of the controller 11 in accordance
with the extracted operation details 1111B (Step 604).
[0110] Receiving the instructions, the components of the controller
11 perform processing corresponding to the operation details 1111B,
to thereby execute their respective power saving modes (Step
S605).
[0111] The controller 11 thus switches power saving modes in
accordance with the magnitude of the load.
[0112] The power control program 1110 sets different power saving
modes to different types of component of the controller 11, but may
set the same power saving mode to every component of the controller
11. In this case, the power control program 1110 chooses the
smallest one out of the power saving mode numbers selected as the
power saving mode number 1112A in Step S602. The chosen power
saving mode number is set to every component of the controller
11.
Second Embodiment
[0113] In a second embodiment, the storage system 1 changes the
number of operating controllers 11 in accordance with the magnitude
of the load.
[0114] A computer system of the second embodiment has the same
configuration as the computer system of the first embodiment shown
in FIG. 1, except the controller 11. A description on the common
part of the configuration will be omitted here.
[0115] FIG. 7 is a block diagram of the controller 11 of the
storage system 1 according to the second embodiment of this
invention.
[0116] The controller 11 of this embodiment is the same as the
controller of the first embodiment shown in FIG. 2, except
information stored in the memory 111. The common components are
denoted by the same reference symbols to avoid repeating the
description.
[0117] The memory 111 stores the power control program 1110, a
controller count control table 1116, the performance monitoring
program 1113, and the access control program 1115.
[0118] The power control program 1110, the performance monitoring
program 1113, and the access control program 1115 are the same as
those stored in the memory 111 of the controller 11 according to
the first embodiment, and therefore descriptions thereof will be
omitted here.
[0119] The controller count control table 1116 manages, as will be
described later with reference to FIG. 8, the association between
the magnitude of the load applied to the controller 11 and how many
controllers 11 are operating.
[0120] FIG. 8 is a configuration diagram of the controller count
control table 1116 in the controller 11 according to the second
embodiment of this invention.
[0121] The controller count control table 1116 includes an
operating controller count 1116A and operation conditions 1116B.
This configuration diagram of the controller count control table
1116 shows a case in which the storage system 1 has four
controllers 11.
[0122] The operating controller count 1116A indicates how many
controllers 11 which are operating in a situation that is
represented by a record entry in question. The operation conditions
1116B describe conditions that have to be fulfilled to create the
situation represented by this record entry. Specifically, the
magnitude of the load applied to the storage system 1 and the like
are stored as the operation conditions 1116B.
[0123] In this configuration diagram of the controller count
control table 1116, conditions related to random performance and
sequential performance are stored as the operation conditions
1116B.
[0124] Random performance is expressed by the proportion of the
current IOPS (I/O per second) of the storage system 1 to the
maximum IOPS of the storage system 1. The IOPS of the storage
system 1 is the combined IOPS of all controllers 11 provided in the
storage system 1.
[0125] Sequential performance is expressed by the proportion of the
current data processing rate of the storage system 1 to the maximum
data processing rate of the storage system 1. The data processing
rate of the storage system 1 is the combined data transfer rate of
all controller 11 provided in the storage system 1.
[0126] Stored as the operation conditions 1116B may be one or
plural conditions. In the case where plural conditions are stored
as the operation conditions 1116B, the power control program 1110
extracts, for each of the conditions stored as the operation
conditions 1116B, a corresponding operating controller count 1116A.
The power control program 1110 then chooses the largest one out of
the operating controller counts extracted as the operating
controller count 1116A. The chosen largest count serves as the
operating controller count.
[0127] FIG. 9 is a flow chart for operating controller count
changing processing according to the second embodiment of this
invention.
[0128] The controller 11 periodically performs the operating
controller count changing processing.
[0129] First, the performance monitoring program 1113 periodically
measures the load of the storage system 1 (Step 701). Specifically,
the performance monitoring program 1113 measures loads listed as
the operation conditions 1116B in the controller count control
table 1116.
[0130] Then, the power control program 1110 chooses from the
controller count control table 1116 a record entry whose operation
conditions 111 6B match the results of the measurement by the
performance monitoring program 1113. From the chosen record entry,
the operating controller count 1116A is extracted (Step 702).
[0131] The power control program 1110 compares the extracted
operating controller count 111 6A with the count of the controllers
11 which are currently in operation, to thereby judge whether or
not it is necessary to change the current count of the operating
controllers 11 (Step 703).
[0132] Judging that there is no need to change the current count of
the operating controllers 11, the power control program 1110 ends
the operating controller count changing processing.
[0133] On the other hand, when it is judged that the current count
of the operating controllers 11 has to be changed, the power
control program 1110 judges whether or not it is necessary to
reduce the count of the operating controllers 11 (Step 704).
[0134] When it is judged that the current count of the operating
controllers 11 needs to be reduced, the power control program 1110
determines which of the operating controllers 11 is to stop
operating (Step 705). Specifically, the power control program 1110
chooses, from among the operating controllers 11, one where the
load is small. The chosen controller 11 is referred to as
shutdown-scheduled controller. A shutdown-scheduled controller is
the controller 11 that is planned to stop operating.
[0135] The power control program 1110 then judges whether
allocation of the LUs 12 needs to be changed or not (Step 706).
Specifically, a change of allocation of the LUs 12 is judged as
necessary when there are any LUs 12 which are allocated to the
shutdown-scheduled controller 11. In the case where no LUs 12 are
allocated to the shutdown-scheduled controller 11, it is judged
that change of allocation of the LUs 12 is not necessary.
[0136] In the case where a change of allocation of the LUs 12 is
unnecessary, there is no need to perform processing for changing
allocation of the LUs 12. The power control program 1110 therefore
advances directly to Step 709.
[0137] On the other hand, when allocation of the LUs 12 has to be
changed, the power control program 1110 determines which of the
operating controllers 11 the LUs 12 are to be re-allocated.
Specifically, the power control program 1110 chooses the controller
11 where the load is small from among the operating controllers 11
excluding the shutdown-scheduled controller. The thus chosen
controller is referred to as destination controller. A destination
controller is the controller 11 that takes over processing of the
LUs 12 formerly allocated to the shutdown-scheduled controller.
[0138] Next, the access control program 1115 instructs the
shutdown-scheduled controller and the destination controller, which
are determined by the power control program 1110, to re-allocate
the LUs 12 (Step 707). Specifically, the access control program
1115 gives an instruction to allocate the LUs 12 that have been
allocated to the shutdown-scheduled controller to- the destination
controller.
[0139] Receiving the instruction, the destination controller takes
over processing of the LUs 12 formerly allocated to the
shutdown-scheduled controller (Step 708).
[0140] Specifics of the processing vary depending on whether or not
all controllers 11 in the storage system 1 share the memory 111 and
the cache memory 117.
[0141] A case in which the memory 111 and the cache memory 117 are
shared among all the controllers 11 will be described first.
[0142] In this case, the shared cache memory stores user data that
have not been destaged to the LUs 12. The shared memory stores
configuration information or the like of the LUs 12. Thus, the
destination controller consults the configuration information of
the LUs 12 which is stored in the shared memory, and controls the
LUs 12 of which processing it has taken over. The destination
controller destages the user data that is stored in the shared
cache memory and is yet to be destaged to the LUs 12 of which
processing it has taken over.
[0143] Meanwhile, the shutdown-scheduled controller rejects a
request to access the formerly allocated LUs 12, and stops managing
the formerly allocated LUs 12. Then, a path switching program
switches access paths connecting the host computer 2 to the storage
system 1. Note that the path switching program is a program that
makes an appropriate switch of access paths upon detection of a
change of allocation of the LUs 12. The path switching program is
provided in, for example, a switch on the network or the host
computer 2.
[0144] A case in which the controllers 11 do not share the memory
and the cache memory will be described next.
[0145] In this case, each controller 11 stores, in the cache memory
117, user data that have not been destaged to its allocated LUs 12.
Also, each controller 11 stores configuration information of its
allocated LUs 12 and the like in the memory 111.
[0146] First, the shutdown-scheduled controller destages the user
data that are stored in its own cache memory 117 and yet to be
destaged to the LUs 12. During this destaging processing, every
write access to the LUs 12 allocated to the shutdown-scheduled
controller is write-through. This enables the shutdown-scheduled
controller to destage all user data stored in the cache memory 117
to the LUs 12, and the data consistency of the LUs 12 is thus
achieved. The shutdown-scheduled controller then writes the
configuration information of the LUs 12 which is stored in its own
memory 111 at given locations in these LUs 12.
[0147] Next, the destination controller obtains, from given
locations of the LUs 12 of which processing it has taken over, the
configuration information of these LUs 12. The obtained
configuration information is stored in the memory 111 of the
destination controller. Based on the configuration information of
the LUs 12 which is stored in the memory 111, the destination
controller controls these LUs 12.
[0148] Then, a path switching program switches access connecting
from the host computer 2 to the storage system 1. The path
switching program is a program that makes an appropriate switch of
access paths upon detection of a change of allocation of the LUs
12. The path switching program is provided in, for example, a
switch on the network or the host computer 2.
[0149] The destination controller thus takes over processing of the
LUs 12 formerly allocated to the shutdown-scheduled controller.
[0150] The power control program 1110 then shuts off power to the
shutdown-scheduled controller (Step 709), whereby ending the
operating controller count changing processing.
[0151] On the other hand, when it is judged in Step 704 that the
current count of the operating controller 11 has to be increased,
the power control program 1110 determines which of the controllers
11 that are not in operation is to start operating. Then, the power
control program 1110 turns on the power of the controller chosen to
start operating (operation-starting controller) (Step 710).
[0152] The power control program 1110 next balances the load of the
operating controllers 11.
[0153] Specifically, the power control program 1110 determines from
which controller the LUs 12 are to be re-allocated (Step 711). The
controller 11 formerly assigned to the LUs 12 that are handed over
to the operation-starting controller to be processed is referred to
as an original controller. For instance, the power control program
1110 chooses the controller 11 with the largest load out of the
operating controllers 11, and decides the thus chosen controller as
the original controller.
[0154] Next, the access control program 1115 instructs the
operation-starting controller and the original controller to
re-allocate the LUs 12 (Step 712). Specifically, an instruction is
given of allocating the LUs 12 formerly allocated to the original
controller to the operation-starting controller.
[0155] Receiving the instruction, the operation-starting controller
takes over processing of the LUs 12 formerly allocated to the
original controller (Step 713). The power control program 1110 then
ends the operating controller count changing processing.
[0156] After finishing the operating controller count changing
processing, the power control program 1110 may immediately start
the power saving mode switching processing of the first embodiment
which is shown in FIG. 6.
[0157] As has been described, the storage system 1 of this
embodiment changes the current count of the controllers 11 that are
in operation in accordance with the magnitude of the load, and thus
reduces power consumption.
Third Embodiment
[0158] In a third embodiment, the host computer 2 tells the storage
system 1 in which power saving mode is to be employed by the
controller 11.
[0159] FIG. 10 is a block diagram of a computer system according to
the third embodiment of this invention.
[0160] The computer system of the third embodiment is the same as
the computer system of the first embodiment shown in FIG. 1, except
the configuration of the host computer 2. The common components are
denoted by the same reference symbols to avoid repeating the
description.
[0161] The host computer 2 in this embodiment stores in its memory
a power instruction program 211. The power instruction program 211
is a program that instructs the storage system 1 to switch one
power saving mode of the controller 11 to another. The power
instruction program 211 may tell the storage system how many
controllers 11 are to be put into operation.
[0162] The power instruction program 211 may be stored in a memory
of the management console 3 instead of the memory of the host
computer 2. In this case, the management console 3 tells the
storage system 1 in which power saving mode is to be employed by
the controller 11.
[0163] When given conditions are met, the power instruction program
211 instructs the controller 11 to switch from the current power
saving mode. For instance, when the host computer 2 activates or
shuts down an application, the power instruction program 211
creates a power saving mode switching request.
[0164] FIG. 11 is a configuration diagram of a power saving mode
switching request 2110, which is sent by the power instruction
program 211 according to the third embodiment of this
invention.
[0165] The power saving mode switching request 2110 includes a
controller ID 2110A, a component name 2110B, and a power saving
mode number 2110C.
[0166] The controller ID 2110A indicates an identifier unique to
each controller 11. The component name 2110B indicates an
identifier unique to each component of the controller 11 that is
identified by the controller ID 2110A. The power saving mode number
2110C indicates an identifier unique to each power saving mode of
this controller 11.
[0167] The power instruction program 211 determines, based on, for
example, the type of an application activated or shut down by the
host computer 2, which controller needs switching of power saving
modes, which of the components of this controller is to switch from
the current power saving mode, and the number of the power saving
mode after the switch is made.
[0168] The power instruction program 211 then enters, in the power
saving mode switching request 2110, the identifier of the
determined controller as the controller ID 2110A, the identifier of
the determined component as the component name 2110B, and the
number of the power saving mode after the switch is made determined
to replace the current power saving mode as the power saving mode
number 2110C.
[0169] The power instruction program 211 can instruct every
component of the controller 11 to switch power saving modes by
leaving the field for the component name 2110B blank.
[0170] The power instruction program 211 sends the created power
saving mode switching request 2110 to the controller 11.
[0171] Receiving the power saving mode switching request 2110, the
controller 11 activates the power control program 1110.
[0172] The power control program 1110 extracts the component name
2110B and the power saving mode number 2110C from the power saving
mode switching request 2110. Then, the power control program 1110
chooses, from the mode management table 1111, a record entry whose
power saving mode number 1111A matches the extracted power saving
mode number 211C. From the chosen record entry, the operation
details 1111B are extracted. The power control program 1110 gives
instructions according to the extracted operation details 1111B to
the component that is identified by the extracted component name
2110B.
[0173] Receiving the instructions, the component of the controller
11 performs processing corresponding to the operation details
1111B.
[0174] The power instruction program 211 may include an operating
controller count changing request in the power saving mode
switching request 2110.
[0175] In this case, the controller 11 that has received the power
saving mode switching request 2110 performs the processing of Steps
704 to 713 of the operating controller count changing processing
shown in FIG. 9.
[0176] The power control program 1110 thus puts as many controllers
11 as requested by the power instruction program 211 of the host
computer 2 into operation.
[0177] According to this embodiment, the host computer 2 can
instruct the controller 11 to switch power saving modes in response
to activation or shutdown of application programs. Furthermore, the
host computer 2 can instruct to change the count of the operating
controllers 11 in response to activation or shutdown of application
programs.
Fourth Embodiment
[0178] FIG. 12 is a block diagram of a computer system according to
a fourth embodiment of this invention.
[0179] The computer system of the fourth embodiment is the same as
the computer system of the first embodiment shown in FIG. 1, except
the configuration of the host computer 2. The common components are
denoted by the same reference symbols to avoid repeating the
description.
[0180] The host computer 2 in this embodiment stores in its memory
a path switching program 21, the controller count control table
1116, and a host computer side threshold management table 22.
[0181] The path switching program 21 is a program that controls an
access path between the host computer 2 and the storage system 1.
The path switching program 21 includes the power instruction
program 211 and a performance management program 212.
[0182] The power instruction program 211 is a program that tells
the storage system 1 which power saving mode is to be employed by
the controller 11. The power instruction program 211 may tell the
storage system how many controllers 11 are to be put into
operation. The performance management program 212 is a program that
manages the load of an access path between the host computer 2 and
the storage system 1.
[0183] The controller count control table 1116 in this embodiment
is the same as the controller count control table that is shown in
FIG. 8 and stored is the control 11 of the second embodiment. A
description on the controller count control table 1116 is therefore
omitted here.
[0184] The host computer side threshold management table 22
manages, as will be described later with reference to FIG. 13, the
association between the magnitude of the load applied to the
controller 11 and a power saving mode of the controller 11.
[0185] FIG. 13 is a configuration diagram of the host computer side
threshold management table 22 in the host computer 2 according to
the fourth embodiment of this invention.
[0186] The host computer side threshold management table 22
includes a power saving mode number 22A and operation conditions
22B.
[0187] The power saving mode number 22A indicates an identifier
unique to each power saving mode of the controller 11. The
operation conditions 22B describe conditions met in the power
saving mode that is identified by the power saving mode number 22A.
Specifically, the magnitude of the load applied to the controller
11 and the like are stored as the operation conditions 22B.
[0188] In this configuration diagram of the host computer side
threshold management table 22, conditions related to random
performance and sequential performance are stored as the operation
conditions 22B.
[0189] Random performance is expressed by the proportion of the
current IOPS of the controller 11 to the maximum IOPS of the
controller 11. Sequential performance is expressed by the
proportion of the current data processing rate of the controller 11
to the maximum data processing rate of the controller 11.
[0190] Stored as the operation conditions 22B may be one condition
or plural conditions. In the case where plural conditions are
stored as the operation conditions 22B, the power instruction
program 211 extracts, for each of the conditions stored as the
operation conditions 22B, a corresponding power saving mode number
22A. The power instruction program 211 then chooses the smallest
one out of the power saving mode numbers extracted as the power
saving mode number 22A. The smallest number chosen serves as the
power saving mode number of the controller 11.
[0191] Described next is power saving mode switching processing of
the computer system according to this embodiment.
[0192] The performance management program 212 of the host computer
2 periodically measures the load of an access path from the host
computer 2 to the storage system 1.
[0193] Based on the load of the access path measured by the
performance management program 212, the power instruction program
211 calculates the load of each controller 11.
[0194] The power instruction program 211 then chooses, from the
host computer side threshold management table 22, a record entry
whose operation conditions 22B match the calculated load. From the
record entry chosen, the power saving mode number 22A is
extracted.
[0195] The extracted power saving mode number 22A is compared
against a power saving mode number that is currently set to the
controller 11, to thereby judge whether or not the power saving
mode set to the controller 11 needs to be switched to another power
saving mode.
[0196] When it is judged that a switch from the current power
saving mode has to be made, the power instruction program 211
sends, to the controller 11, the power saving mode switching
request 2110 that includes the extracted power saving mode number
22A.
[0197] Receiving the power saving mode switching request 2110, the
controller 11 activates the power control program 1110 to switch
the current power saving mode to another power saving mode.
[0198] The host computer 2 of this embodiment thus instructs the
controller 11 to switch power saving modes in accordance with the
magnitude of the load applied to an access path between the host
computer 2 and the storage system 1.
[0199] FIG. 14 is a flow chart for operating controller count
changing processing according to the fourth embodiment of this
invention.
[0200] The performance management program 212 of the host computer
2 periodically measures the load of each access path from the host
computer 2 to the storage system 1 (Step 801).
[0201] Based on the load of the access path measured by the
performance management program 212, the power instruction program
211 of the host computer 2 calculates the load of each controller
11.
[0202] The power instruction program 21i then chooses, from the
controller count control table 1116, a record entry whose operation
conditions 1116B match the calculated load. From the record entry
chosen, the power saving mode number 1116A is extracted (Step
802).
[0203] The power instruction program 211 compares the extracted
operating controller count 111 6A against the count of the
controllers 11 that are currently in operation, to thereby judge
whether or not it is necessary to change the current count of the
operating controllers 11 (Step 803).
[0204] Judging that there is no need to change the current count of
the operating controllers 11, the power instruction program 211
ends the operating controller count changing processing.
[0205] On the other hand, when it is judged that the current count
of the operating controllers 11 has to be changed, the power
instruction program 211 judges whether the necessary change is for
reduction of the count of the operating controllers 11 or not (Step
804).
[0206] When it is judged that the current count of the operating
controllers 11 needs to be reduced, the power instruction program
211 determines which of the operating controllers 11 is to stop
operating (Step 805). Specifically, the power instruction program
211 chooses, from among the operating controllers 11, one where the
load is small. The chosen controller 11 is referred to as
shutdown-scheduled controller. A shutdown-scheduled controller is
the controller 11 that is planned to stop operating.
[0207] The power instruction program 211 next instructs the
shutdown-scheduled controller to turn off the power. In response to
the instruction, the shutdown-scheduled controller activates the
power control program 1110 and the access control program 1115. The
power control program 1110 and the access control program 1115
perform the processing of Steps 706 to 709 of the operating
controller count changing processing described in the second
embodiment with reference to FIG. 9. Then the operating controller
count changing processing is ended.
[0208] On the other hand, when it is judged in Step 804 that the
current count of the operating controller 11 has to be increased,
the power instruction program 211 determines which of the
controllers 11 that are not in operation is to start operating.
Then the power instruction program 211 instructs the thus chosen
controller (operation-starting controller) to turn on the power
(Step 810).
[0209] Receiving the instruction to turn the power on, the
operation-starting controller turns on the power, and activates the
power control program 1110 and the access control program 1115.
[0210] The power control program 1110 and the access control
program 1115 perform the processing of Steps 711 to 713 of the
operating controller count changing processing described in the
second embodiment with reference to FIG. 9. Then the operating
controller count changing processing is ended.
[0211] According to this embodiment, the host computer 2 instructs
to change the count of the operating controllers 11 in accordance
with the load of an access path between the host computer 2 and the
storage system 1. The storage system 1 can thus reduce power
consumption.
[0212] While the present invention has been described in detail and
pictorially in the accompanying drawings, the present invention is
not limited to such detail but covers various obvious modifications
and equivalent arrangements, which fall within the purview of the
appended claims.
* * * * *