U.S. patent application number 11/244955 was filed with the patent office on 2007-03-29 for strained-induced mobility enhancement nano-device structure and integrated process architecture for cmos technologies.
This patent application is currently assigned to Semiconductor Manufacturing International (Shanghai) Corporation. Invention is credited to John Chen, Simon Yang.
Application Number | 20070072376 11/244955 |
Document ID | / |
Family ID | 37894627 |
Filed Date | 2007-03-29 |
United States Patent
Application |
20070072376 |
Kind Code |
A1 |
Chen; John ; et al. |
March 29, 2007 |
Strained-induced mobility enhancement nano-device structure and
integrated process architecture for CMOS technologies
Abstract
A CMOS semiconductor integrated circuit device. The CMOS device
includes an NMOS device comprising a gate region, a source region,
and a drain region and an NMOS channel region formed between the
source region and drain region. A silicon carbide material is
formed within the source region and formed within the drain region.
The silicon carbide material causes the channel region to be in a
tensile mode. The CMOS device also has a PMOS device comprising a
gate region, a source region, and a drain region. The PMOS device
has a PMOS channel region formed between the source region and the
drain region. A silicon germanium material is formed within the
source region and formed with in the drain region. The silicon
germanium material causes the channel region to be in a compressive
mode.
Inventors: |
Chen; John; (Shanghai,
CN) ; Yang; Simon; (Shanghai, CN) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW, LLP
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Assignee: |
Semiconductor Manufacturing
International (Shanghai) Corporation
Shanghai
CN
|
Family ID: |
37894627 |
Appl. No.: |
11/244955 |
Filed: |
October 5, 2005 |
Current U.S.
Class: |
438/275 ;
257/315; 257/E21.43; 257/E21.431; 257/E21.633; 257/E21.634;
257/E29.085; 438/287 |
Current CPC
Class: |
H01L 21/823814 20130101;
H01L 29/7843 20130101; H01L 29/66636 20130101; H01L 29/7848
20130101; H01L 21/77 20130101; H01L 29/165 20130101; H01L 21/823807
20130101; H01L 29/66628 20130101 |
Class at
Publication: |
438/275 ;
438/287; 257/315 |
International
Class: |
H01L 21/8234 20060101
H01L021/8234; H01L 21/336 20060101 H01L021/336; H01L 29/788
20060101 H01L029/788 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 29, 2005 |
CN |
200510030311.3 |
Claims
1. A method for forming a CMOS semiconductor integrated circuit
device comprising: providing a semiconductor substrate forming a
dielectric layer overlying the semiconductor substrate; forming a
gate layer overlying the dielectric layer; patterning the gate
layer to form a gate structure including edges; forming a
dielectric layer overlying the gate structure to protect the gate
structure including the edges, the dielectric layer having a
thickness of less than 1000 A nanometers; patterning the dielectric
layer overlying the gate structure; etching a source region and a
drain region adjacent to the gate structure using the patterned
dielectric layer as a protective layer; depositing silicon
germanium material into the source region and the drain region to
fill the etched source region and the etched drain region; and
causing a channel region between the source region and the drain
region to be strained in compressive mode from at least the silicon
germanium material formed in the source region and the drain
region.
2. The method of claim 1 wherein the dielectric layer is less than
300 Angstroms.
3. The method of claim 1 wherein the effective channel region has a
length of a width of the gate structure.
4. The method of claim 1 wherein the semiconductor substrate is
essential silicon material.
5. The method of claim 1 wherein the silicon germanium material is
single crystalline.
6. The method of claim 1 wherein the silicon germanium has a ratio
of silicon/germanium of 10% to 20%.
7. The method of claim 1 further comprising forming a spacer layer
overlying the semiconductor substrate including silicon germanium,
gate structure, and edges.
8. The method of claim 7 further comprising anisotropic etching the
spacer layer to form sidewall spacers on edges of the gate
layer.
9. The method of claim 1 wherein the depositing is provided using
an epitaxial reactor.
10. The method of claim 1 wherein the compressive mode increases a
mobility of holes in the channel region.
11. A CMOS semiconductor integrated circuit device, the device
comprising: an NMOS device comprising a gate region, a source
region, and a drain region; an NMOS channel region formed between
the source region and drain region; a silicon carbide material
formed within the source region and formed within the drain region;
whereupon the silicon carbide material causes the channel region to
be in a tensile mode; and a PMOS device comprising a gate region, a
source region, and a drain region; a PMOS channel region formed
between the source region and the drain region; a silicon germanium
formed within the source region and formed with in the drain
region; and whereupon the silicon germanium material causes the
channel region to be in a compressive mode.
12. The device of claim 11 wherein the semiconductor substrate is
essentially silicon material.
13. The device of claim 11 wherein the NMOS channel region has a
length of less than 90 nanometers.
14. The device of claim 11 wherein the PMOS channel region has a
length of less than 90 nanometers.
15. The device of claim 11 wherein the silicon carbide material is
single crystal material.
16. The device of claim II wherein the silicon germanium material
is single crystal material.
17. The device of claim 11 wherein the NMOS channel region has a
length that. is substantially equal to a width of the gate region
of the NMOS device.
18. The device of claim 17 wherein the length is exactly equal to
the width of the gate region.
19. The device of claim 11 wherein the PMOS channel region has a
length that is substantially equal as a width of the gate region of
the PMOS device.
20. The device of claim 19 wherein the length is exactly equal to
the width of the gate region.
21. A method for forming a CMOS integrated circuit device, the
method comprising: providing a semiconductor substrate; forming a
gate layer overlying the semiconductor substrate; patterning the
gate layer to form an NMOS gate structure including edges and a
PMOS gate structure including edges; forming a dielectric layer
overlying the NMOS gate structure to protect the NMOS gate
structure including the edges and overlying the PMOS gate structure
to protect the PMOS gate structure including the edges;
simultaneously etching a first source region and a first drain
region adjacent to the NMOS gate structure and second source region
and second drain region adjacent to the PMOS gate structure using
the dielectric layer as a protective layer; depositing silicon
germanium material into the first source region and the first drain
region to cause a channel region between the first source region
and the first drain region of the NMOS gate structure to be
strained in a compressive mode; depositing silicon carbide material
into the second source region and second drain region to cause the
channel region between the second source region and the second
drain region of the PMOS gate structure to be strained in a tensile
mode.
22. The method of claim 21 wherein the tensile mode increases an
electron mobility.
23. The method of claim 21 wherein the compressive mode increases a
hole mobility.
24. The method of claim 21 wherein the channel region of the PMOS
device has a length of 90 nanometers and less.
25. The method of claim 21 wherein the channel region of the NMOS
device has a length of 90 nanometers and less.
26. The method of claim 21 wherein the silicon germanium material
is an epitaxial material.
27. The method of claim 21 wherein the silicon carbide material is
an epitaxial material.
28. The method of claim 21 wherein the silicon germanium material
has a thickness ranging from about 200 Angstroms to 1000
Angstroms.
29. The method of claim 21 wherein the silicon carbide material has
a thickness ranging from about 200 Angstroms to 1000 Angstroms.
30. The method of claim 21 further comprising forming sidewall
spacers on the edges of the NMOS gate structure and the edges of
the PMOS gate structure.
31. The method of claim 21 wherein the depositing the silicon
germanium material is an in-situ doped process using a boron
species, the boron species having a concentration ranging from
about 10.sup.19 to 10.sup.20 atoms/cm.sup.3.
32. The method of claim 21 wherein the depositing the silicon
carbide material is an in-situ doped process using a phosphorus
species, the phosphorus species having a concentration ranging from
about 10.sup.19 to 10.sup.20 atoms/cm.sup.3.
33. The method of claim 21 further comprising forming a refractory
metal layer overlying the first source region and first drain
region and the second source region and the second drain
region.
34. The method of claim 21 wherein the first source region is an
elevated first source region and the first drain region is an
elevated first drain region; the second source region is an
elevated second source region and the second drain region is an
elevated second drain region.
35. A PMOS integrated circuit device, the device comprising: a
semiconductor substrate comprising a surface region; an isolation
region formed within the semiconductor substrate; a gate dielectric
layer overlying the surface region of the semiconductor substrate;
a PMOS gate layer, the PMOS gate layer including a first edge and a
second edge; a first lightly doped region formed within a vicinity
of the first edge; a second lightly doped region formed within a
vicinity of the second edge; a first sidewall spacer formed on the
first edge and on a portion of the first lightly doped region; a
second sidewall spacer formed on the second edge and on a portion
of the second lightly doped region; a first etched region of
semiconductor substrate formed adjacent to the first sidewall
spacer; a second etched region of semiconductor substrate formed
adjacent to the second sidewall spacer; a first silicon germanium
material formed within the first etched region to form a first
source/drain region; a second silicon germanium material formed
within the second etched region to form a second source/drain
region; and a PMOS channel region formed between the first silicon
germanium material and the second silicon germanium layer.
36. The device of claim 35 wherein the first silicon germanium
material comprises a first surface that has a height above the
surface region and the second silicon germanium material comprises
a second surface that has a height above the surface region.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention is directed to integrated circuits and
their processing for the manufacture of semiconductor devices. More
particularly, the invention provides a method and structures for
manufacturing MOS devices using strained silicon structures for
advanced CMOS integrated circuit devices. But it would be
recognized that the invention has a much broader range of
applicability.
[0002] Integrated circuits have evolved from a handful of
interconnected devices fabricated on a single chip of silicon to
millions of devices. Conventional integrated circuits provide
performance and complexity far beyond what was originally imagined.
In order to achieve improvements in complexity and circuit density
(i.e., the number of devices capable of being packed onto a given
chip area), the size of the smallest device feature, also known as
the device "geometry", has become smaller with each generation of
integrated circuits.
[0003] Increasing circuit density has not only improved the
complexity and performance of integrated circuits but has also
provided lower cost parts to the consumer. An integrated circuit or
chip fabrication facility can cost hundreds of millions, or even
billions, of U.S. dollars. Each fabrication facility will have a
certain throughput of wafers, and each wafer will have a certain
number of integrated circuits on it. Therefore, by making the
individual devices of an integrated circuit smaller, more devices
may be fabricated on each wafer, thus increasing the output of the
fabrication facility. Making devices smaller is very challenging,
as each process used in integrated fabrication has a limit. That is
to say, a given process typically only works down to a certain
feature size, and then either the process or the device layout
needs to be changed. Additionally, as devices require faster and
faster designs, process limitations exist with certain conventional
processes and materials.
[0004] An example of such a process is the manufacture of MOS
devices themselves. Such device has traditionally became smaller
and smaller and produced faster switching speeds. Although there
have been significant improvements, such devices still have many
limitations. As merely an example, these devices must become
smaller and smaller but still provide clear signals for switching,
which become more difficult as the device becomes smaller. That is,
switching power becomes about the same order of magnitude as
undesirable noise influences. Additionally, these devices are often
difficult to manufacture and generally require complex
manufacturing processes and structures. These and other limitations
will be described in further detail throughout the present
specification and more particularly below.
[0005] From the above, it is seen that an improved technique for
processing semiconductor devices is desired.
BRIEF SUMMARY OF THE INVENTION
[0006] According to the present invention, techniques for
processing integrated circuits for the manufacture of semiconductor
devices are provided. More particularly, the invention provides a
method and structures for manufacturing MOS devices using strained
silicon structures for CMOS advanced integrated circuit devices.
But it would be recognized that the invention has a much broader
range of applicability.
[0007] In a specific embodiment, the present invention provides a
method for forming a CMOS semiconductor integrated circuit devices.
The method includes providing a semiconductor substrate, e.g.,
silicon wafer, silicon on insulator. The method includes forming a
dielectric layer (e.g., gate oxide or nitride) overlying the
semiconductor substrate and forming a gate layer (e.g.,
polysilicon, metal) overlying the dielectric layer. The method
includes patterning the gate layer to form a gate structure
including edges (e.g., a plurality of sides or edges) and forming a
dielectric layer or multi-layers overlying the gate structure to
protect the gate structure including the edges. The dielectric
layer has a thickness of less than 100 nanometers. The method
includes etching a source region and a drain region adjacent to the
gate structure using the dielectric layer as a protective layer and
depositing silicon germanium material into the source region and
the drain region to fill the etched source region and the etched
drain region. Preferably, the method causes a channel region
between the source region and the drain region to be strained in
compressive mode from at least the silicon germanium material
formed in the source region and the drain region.
[0008] In an alternative specific embodiment, the invention
provides a CMOS semiconductor integrated circuit device. The CMOS
device includes an NMOS device comprising a gate region, a source
region, and a drain region and an NMOS channel region formed
between the source region and drain region. A silicon carbide
material is formed within the source region and formed within the
drain region. The silicon carbide material causes the channel
region to be in a tensile mode. The CMOS device also has a PMOS
device comprising a gate region, a source region, and a drain
region. The PMOS device has a PMOS channel region formed between
the source region and the drain region. A silicon germanium
material is formed within the source region and formed with in the
drain region. The silicon germanium material causes the channel
region to be in a compressive mode.
[0009] In yet an alternative specific embodiment, the present
invention provides a method for forming a CMOS integrated circuit
device. The method includes providing a semiconductor substrate,
e.g., silicon wafer, silicon on insulator. The method includes
forming a gate layer overlying the semiconductor substrate and
patterning the gate layer to form an NMOS gate structure including
edges and a PMOS gate structure including edges. The method
includes forming a dielectric layer overlying the NMOS gate
structure to protect the NMOS gate structure including the edges
and overlying the PMOS gate structure to protect the PMOS gate
structure including the edges. Preferably, the method
simultaneously etches a first source region and a first drain
region adjacent to the NMOS gate structure and etches a second
source region and a second drain region adjacent to the PMOS gate
structure using the dielectric layer as a protective layer. The
method deposits silicon germanium material into the first source
region and the first drain region to cause a channel region between
the first source region and the first drain region of the PMOS gate
structure to be strained in a compressive mode. The method also
deposits silicon carbide material into the second source region and
second drain region to cause the channel region between the second
source region and the second drain region of the NMOS gate
structure to be strained in a tensile mode.
[0010] In yet an alternative specific embodiment, the present
invention provides a PMOS integrated circuit device. The device has
a semiconductor substrate comprising a surface region and an
isolation region formed within the semiconductor substrate. A gate
dielectric layer is formed overlying the surface region of the
semiconductor substrate. A PMOS gate layer is formed overlying a
portion of the surface region. The PMOS gate layer includes a first
edge and a second edge. The device has a first lightly doped region
formed within a vicinity of the first edge and a second lightly
doped region formed within a vicinity of the second edge. The
device also has a first sidewall spacer formed on the first edge
and on a portion of the first lightly doped region and a second
sidewall spacer formed on the second edge and on a portion of the
second lightly doped region. A first etched region of semiconductor
substrate is formed adjacent to the first sidewall spacer and a
second etched region of semiconductor substrate is formed adjacent
to the second sidewall spacer. The device has a first silicon
germanium material formed within the first etched region to form a
first source/drain region and a second silicon germanium material
formed within the second etched region to form a second
source/drain region. A PMOS channel region is formed between the
first silicon germanium material and the second silicon germanium
layer. Preferably, the first silicon germanium material comprises a
first surface that has a height above the surface region and the
second silicon germanium material comprises a second surface that
has a height above the surface region. Preferably, the PMOS channel
region exhibits a strained characteristic in compressive mode
according to a specific embodiment.
[0011] Many benefits are achieved by way of the present invention
over conventional techniques. For example, the present technique
provides an easy to use process that relies upon conventional
technology. In some embodiments, the method provides higher device
yields in dies per wafer. Additionally, the method provides a
process that is compatible with conventional process technology
without substantial modifications to conventional equipment and
processes. Preferably, the invention provides for an improved
process integration for design rules of 90 nanometers and less.
Additionally, the invention provides for increased mobility of
holes using a strained silicon structure for CMOS devices.
Depending upon the embodiment, one or more of these benefits may be
achieved. These and other benefits will be described in more
throughout the present specification and more particularly
below.
[0012] Various additional objects, features and advantages of the
present invention can be more fully appreciated with reference to
the detailed description and accompanying drawings that follow.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 is a simplified cross-sectional view diagram of a
CMOS device according to an embodiment of the present
invention.
[0014] FIG. 2 is a simplified flow diagram illustrating a method
for fabricating a CMOS device according to an embodiment of the
present invention.
[0015] FIGS. 3 through 6 are simplified cross-sectional view
diagrams illustrating a method for fabricating a CMOS device
according to an embodiment of the present invention.
[0016] FIG. 7 is a simplified cross-sectional view diagram of an
alternative CMOS device according to an alternative embodiment of
the present invention.
[0017] FIGS. 8-13 are simplified cross-sectional view diagrams
illustrating an alternative method for fabricating a CMOS device
according to an alternative embodiment of the present
invention.
[0018] FIGS. 14-19 are simplified cross-sectional view diagrams
illustrating yet an alternative method for fabricating a CMOS
device according to an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0019] According to the present invention, techniques for
processing integrated circuits for the manufacture of semiconductor
devices are provided. More particularly, the invention provides a
method and structures for manufacturing MOS devices using strained
silicon structures for CMOS advanced integrated circuit devices.
But it would be recognized that the invention has a much broader
range of applicability.
[0020] FIG. 1 is a simplified cross-sectional view diagram of a
CMOS device 100 according to an embodiment of the present
invention. This diagram is merely an example, which should not
unduly limit the scope of the claims herein. One of ordinary skill
in the art would recognize many variations, alternatives, and
modifications. As shown, the CMOS device includes an NMOS device
107 comprising a gate region 109, a source region 111, a drain
region 113 and an NMOS channel region 115 formed between the source
region and drain region. Preferably, the channel region has width
of less than 90 microns in a preferred embodiment. Of course, there
can be other variations, modifications, and alternatives.
[0021] A silicon carbide material is formed within the source
region 111 and is formed within the drain region 113. That is, the
silicon carbide material is epitaxially grown within etched regions
of the source and drain regions to form a multilayered structure.
The silicon carbide material is preferably doped using an N type
impurity. In a specific embodiment, the impurity is phosphorous and
has a concentration ranging from about 1.times.10.sup.19 to about
1.times.10.sup.20 atoms/cm.sup.3. The silicon carbide material
causes the channel region to be in a tensile mode. The silicon
carbide material has a lattice contact that is less than the
lattice constant for single crystal silicon. Since the lattice
constant is smaller for silicon carbide, it causes the NMOS channel
region to be in a tensile mode. The channel region is longer than
for single crystal silicon by about 0.7-0.8 percent in a specific
embodiment. The NMOS device is formed in a P-type well region. Of
course, there can be other variations, modifications, and
alternatives.
[0022] The CMOS device also has a PMOS device 105 comprising a gate
region 121, a source region 123, and a drain region 125. The PMOS
device has a PMOS channel region 127 formed between the source
region and the drain region. Preferably, the channel region has
width of less than 90 microns in a preferred embodiment. The PMOS
device is also formed in N-type well regions. The N-type well
region is preferably doped using an N type impurity. Of course,
there can be other variations, modifications, and alternatives.
[0023] A silicon germanium material is formed within the source
region and formed with in the drain region. That is, the silicon
germanium material is epitaxially grown within etched regions of
the source and drain regions to form a multilayered structure. The
silicon germanium material is preferably doped using a P type
impurity. In a specific embodiment, the impurity is boron and has a
concentration ranging from about 1.times.10.sup.19 to about
1.times.10.sup.20 atoms/cm.sup.3. The silicon germanium material
causes the channel region to be in a compressive mode. The silicon
germanium material has a lattice contact that is larger than the
lattice constant for single crystal silicon. Since the lattice
constant is larger for silicon germanium, it tends to cause the
PMOS channel region to be in a compressive mode. The channel region
is shorter than for single crystal silicon by about 0.7-0.8 percent
in a specific embodiment.
[0024] As further shown, the device has isolation regions 103,
which are formed between active transistor devices, such as the MOS
devices. The isolation regions are preferably made using shallow
trench isolation techniques. Such techniques often use patterning,
etching, and filling the trench with a dielectric material such as
silicon dioxide or like material. Of course, one of ordinary skill
in the art would recognize other variations, modifications, and
alternatives. Further details of a method for fabricating the CMOS
device can be found throughout the present specification and more
particularly below.
[0025] Referring to FIG. 2 a method 200 for fabricating a CMOS
integrated circuit device according to an embodiment of the present
invention may be outlined as follows:
[0026] 1. Provide a semiconductor substrate (step 201), e.g.,
silicon wafer, silicon on insulator;
[0027] 2. Form shallow trench isolation regions (step 203);
[0028] 3. Form a gate dielectric layer (step 205) overlying the
surface of the substrate;
[0029] 4. Form a gate layer overlying the semiconductor
substrate;
[0030] 5. Pattern the gate layer to form an NMOS gate structure
including edges and pattern a PMOS gate structure including
edges;
[0031] 6. Form lightly doped drain regions and sidewall spacers
(step 207) on edges of patterned gate layer;
[0032] 7. Form a dielectric layer overlying the NMOS gate structure
to protect the NMOS gate structure including the edges and
overlying the PMOS gate structure to protect the PMOS gate
structure including the edges;
[0033] 8. Simultaneously etch a first source region and a first
drain region adjacent to the NMOS gate structure and etch a second
source region and a second drain region adjacent to the PMOS gate
structure using the dielectric layer as a protective layer (step
209);
[0034] 9. Pretreat etched source/drain regions;
[0035] 10. Mask NMOS regions;
[0036] 11. Deposit silicon germanium material into the first source
region and the first drain region to cause a channel region between
the first source region and the first drain region of the PMOS gate
structure to be strained in a compressive mode (step 211);
[0037] 12. Strip Mask from NMOS regions;
[0038] 13. Mask PMOS regions;
[0039] 14. Deposit silicon carbide material into the second source
region and second drain region to cause the channel region between
the second source region and the second drain region of the NMOS
gate structure to be strained in a tensile mode (step 213);
[0040] 15. Form silicide layer overlying gate layer and
source/drain regions (step 215);
[0041] 16. Form interlayer dielectric layer overlying NMOS and PMOS
transistor devices (step 217);
[0042] 17. Form contacts (step 219);
[0043] 18. Perform back end processes (step 221); and
[0044] 19. Perform other steps, as desired.
[0045] The above sequence of steps provides a method according to
an embodiment of the present invention. As shown, the method uses a
combination of steps including a way of forming a CMOS integrated
circuit device. Other alternatives can also be provided where steps
are added, one or more steps are removed, or one or more steps are
provided in a different sequence without departing from the scope
of the claims herein. Further details of the present method can be
found throughout the present specification and more particularly
below.
[0046] FIGS. 3-6 are simplified diagrams illustrating a method for
fabricating a CMOS device according to an embodiment of the present
invention. These diagrams are merely examples, which should not
unduly limit the scope of the claims herein. One of ordinary skill
in the art would recognize many variations, alternatives, and
modifications. As shown, the method provides a semiconductor
substrate 301, e.g., silicon wafer, silicon on insulator. The
semiconductor substrate is single crystalline silicon. The silicon
has been oriented in the 100 direction on the face of the wafer. Of
course, there can be other variations, modifications, and
alternatives. Preferably, the method forms isolation regions within
the substrate. In a specific embodiment, the method forms a shallow
trench isolation region or regions 303 within a portion of the
semiconductor substrate. The shallow trench isolation regions are
formed using patterning, etching, and deposition of a dielectric
fill material within the trench region. The dielectric fill
material is often oxide or a combination of oxide and nitride
depending upon the specific embodiment. The isolation regions are
used to isolate active regions within the semiconductor
substrate.
[0047] The method forms a gate dielectric layer 305 overlying the
surface of the substrate. Preferably, the gate dielectric layer is
oxide or silicon oxynitride depending upon the embodiment. The gate
dielectric layer is preferably 10-20 nanometers and less depending
upon the specific embodiment. The method forms a gate layer 307
overlying the semiconductor substrate. The gate layer is preferably
polysilicon that has been doped using either in-situ doping or
ex-situ implantation techniques. The impurity for doping is often
boron, arsenic, or phosphrous having a concentration ranging from
about 1.times.10.sup.19 to about 1.times.10.sup.20 atoms/cm.sup.3.
Of course, one of ordinary skill in the art would recognize many
variations, modifications, and alternatives.
[0048] Referring to FIG. 4, the method patterns the gate layer to
form an NMOS gate structure 401 including edges and patterns a PMOS
gate structure 403 including edges. The method forms lightly doped
drain regions 405 407 and optionally sidewall spacers on edges of
patterned gate layer. Depending upon the embodiment, there may also
be no sidewall spacers. The lightly doped drain regions are often
formed using implantation techniques. For the PMOS device, the
lightly doped drain region uses Boron or BF.sub.2 impurity having a
concentration ranging from about 1.times.10.sup.18 to about
1.times.10.sup.19 atoms/cm.sup.3. For the NMOS device, the lightly
doped drain region uses arsenic impurity having a concentration
ranging from about 1.times.10.sup.18 to about 1.times.10.sup.19
atoms/cm.sup.3. The method forms a dielectric layer overlying the
NMOS gate structure to protect the NMOS gate structure including
the edges. The method also forms a dielectric protective layer
overlying the PMOS gate structure to protect the PMOS gate
structure including the edges. Preferably, the dielectric
protective layer is the same layer for PMOS and NMOS devices.
Alternatively, another suitable material can be used to protect the
NMOS and PMOS gate structures, including lightly doped drain
regions.
[0049] Referring to FIG. 5, the method simultaneously etches a
first source region and a first drain region adjacent to the NMOS
gate structure 501 and etches a second source region and a second
drain region adjacent to the PMOS gate structure 503 using the
dielectric layer as a protective layer. The method uses reactive
ion etching techniques including a SF.sub.6 or CF.sub.4 bearing
species and plasma environment. In a preferred embodiment, the
method performs a pre-treatment process on etched source/drain
regions. According to a specific embodiment, the each of the etched
regions has a depth of ranging from about 100 Angstroms (A) to
about
[0050] A and a length of about 0.1 um to about 10 um, and a width
of about 0.1 um to about 10 um for a 90 nanometer channel length.
Each of the etched regions has a depth of ranging from about 100 A
to about 1,000 A and a length of about 0.1 um to about 10 um, and a
width of about 0.1 um to about 10 um for a 65 nanometer channel
length according to an alternative specific embodiment.
[0051] The method masks NMOS regions, while exposing the PMOS
etched regions. The method deposits silicon germanium material into
the first source region and the first drain region to cause a
channel region between the first source region and the first drain
region of the PMOS gate structure to be strained in a compressive
mode. The silicon germanium is epitaxially deposited using in-situ
doping techniques. That is, impurities such as boron are introduced
while the silicon germanium material grows. A concentration ranges
from about 1.times.10.sup.19 to about 1.times.10.sup.20
atoms/cm.sup.3 of boron according to a specific embodiment. Of
course, there can be other variations, modifications, and
alternatives.
[0052] The method strips the mask from NMOS regions. The method
masks PMOS regions, while exposing the NMOS etched regions. The
method deposits silicon carbide material into the second source
region and second drain region to cause the NMOS channel region
between the second source region and the second drain region of the
NMOS gate structure to be strained in a tensile mode. The silicon
carbide is epitaxially deposited using in-situ doping techniques.
That is, impurities such as phosphorous (P) or arsenic (As) are
introduced while the silicon carbide material grows. A
concentration ranges from about 1.times.10.sup.19 to about
1.times.10.sup.20 atoms/cm.sup.3 of the above impurities according
to a specific embodiment. Of course, there can be other variations,
modifications, and alternatives.
[0053] To finish the device according to an embodiment of the
present invention, the method forms a silicide layer 601 overlying
gate layer and source/drain regions. Preferably, the silicide layer
is a nickel bearing layer such as nickel silicide overlying the
exposed source/drain regions and upper surface of the patterned
gate layer. Other types of silicide layers can also be used. Such
silicide layers include titanium silicide, tungsten silicide,
nickel silicide, and the like. The method forms an interlayer
dielectric layer overlying NMOS and PMOS transistor devices. The
method then provides contact regions, CT. Other steps include
performing a back end processes and other steps, as desired.
[0054] The above sequence of steps provides a method according to
an embodiment of the present invention. As shown, the method uses a
combination of steps including a way of forming a CMOS integrated
circuit device. Other alternatives can also be provided where steps
are added, one or more steps are removed, or one or more steps are
provided in a different sequence without departing from the scope
of the claims herein.
[0055] FIG. 7 is a simplified cross-sectional view diagram of an
alternative CMOS device according to an alternative embodiment of
the present invention. This diagram is merely an example, which
should not unduly limit the scope of the claims herein. One of
ordinary skill in the art would recognize many variations,
alternatives, and modifications. As shown, the device is a PMOS
integrated circuit device. Alternatively, the device may also be
NMOS or the like. The device has a semiconductor substrate 701
(e.g., silicon, silicon on insulator) comprising a surface region
and an isolation region 703 (e.g., trench isolation) formed within
the semiconductor substrate. A gate dielectric layer 705 is formed
overlying the surface region of the semiconductor substrate. A PMOS
gate layer 707 is formed overlying a portion of the surface region.
The gate layer is preferably doped polysilicon that has been
crystallized according to a specific embodiment. The doping is
often an impurity such as boron having a concentration ranging from
about 1.times.10.sup.19 to about 1.times.10.sup.20 depending upon
the specific embodiment.
[0056] The PMOS gate layer includes a first edge 709 and a second
edge 711. The device has a first lightly doped region 713 formed
within a vicinity of the first edge and a second lightly doped
region 715 formed within a vicinity of the second edge. The device
also has a first sidewall spacer 721 formed on the first edge and
on a portion of the first lightly doped region and a second
sidewall spacer 723 formed on the second edge and on a portion of
the second lightly doped region. A first etched region of
semiconductor substrate is formed adjacent to the first sidewall
spacer and a second etched region of semiconductor substrate is
formed adjacent to the second sidewall spacer. The device has a
first silicon germanium material 717 formed within the first etched
region 716 to form a first source/drain region and a second silicon
germanium 719 material formed within the second etched region 718
to form a second source/drain region. The silicon germanium layer
has been grown using an epitaxial process. The silicon germanium is
also doped using an impurity such as boron having a concentration
ranging from about 1.times.10.sup.19 to about 1.times.10.sup.20
depending upon the specific embodiment.
[0057] A PMOS channel region 720 is formed between the first
silicon germanium material and the second silicon germanium layer.
Preferably, the first silicon germanium material comprises a first
surface 725 that has a height above the surface region and the
second silicon germanium material comprises a second surface 727
that has a height above the surface region. The device has a
silicide layer overlying gate layer and source/drain regions.
Preferably, the silicide layer is a nickel bearing layer such as
nickel silicide overlying the exposed source/drain regions and
upper surface of the patterned gate layer, as shown. Of course,
there can be other variations, modifications, and alternatives.
Further details of the present device can be found throughout the
present specification and more particularly below.
[0058] A method for fabricating a CMOS integrated circuit device
according to an embodiment of the present invention may be outlined
as follows:
[0059] 1. Provide a semiconductor substrate, e.g., silicon wafer,
silicon on insulator;
[0060] 2. Form a dielectric layer (e.g., gate oxide or nitride)
overlying the semiconductor substrate;
[0061] 3. Form a gate layer (e.g., polysilicon, metal) overlying
the dielectric layer;
[0062] 4. Pattern the gate layer to form a gate structure including
edges (e.g., a plurality of sides or edges);
[0063] 5. Form a dielectric layer or multi-layers overlying the
gate structure to protect the gate structure including the edges,
wherein the dielectric layer being less than 1000 A;
[0064] 6. Etch a source region and a drain region adjacent to the
gate structure using the dielectric layer as a protective
layer;
[0065] 7. Deposit silicon germanium material into the source region
and the drain region to fill the etched source region and the
etched drain region;
[0066] 8. Cause a channel region between the source region and the
drain region to be strained in compressive mode from at least the
silicon germanium material formed in the source region and the
drain region, wherein the channel region is about the same width as
the patterned gate layer;
[0067] 9. Form sidewall spacers overlying the patterned gate layer;
and
[0068] 10. Perform other steps, as desired.
[0069] The above sequence of steps provides a method according to
an embodiment of the present invention. As shown, the method uses a
combination of steps including a way of forming a CMOS integrated
circuit device. Other alternatives can also be provided where steps
are added, one or more steps are removed, or one or more steps are
provided in a different sequence without departing from the scope
of the claims herein.
[0070] FIGS. 8-13 are simplified cross-sectional view diagrams
illustrating an alternative method for fabricating a CMOS device
according to an alternative embodiment of the present invention.
These diagrams are merely examples, which should not unduly limit
the scope of the claims herein. One of ordinary skill in the art
would recognize many variations, modifications, and
alternatives.
[0071] A method illustrating an alternative method for fabricating
a CMOS device according to an alternative embodiment of the present
invention is briefly outlined below.
[0072] 1. Provide semiconductor substrate including trench region
(shallow trench isolation) 805, including PMOS 801 and NMOS 803
devices thereon (see, FIG. 8);
[0073] 2. Form overlying oxide layer 807 and overlying silicon
nitride layer 809;
[0074] 3. Form masking layer 811 overlying NMOS devices;
[0075] 4. Form spacer regions 901 on PMOS devices using masking
layer 811 to protect NMOS devices, as illustrated by FIG. 9;
[0076] 5. Form etched source/drain regions 903 for PMOS devices
using the masking layer to product the NMOS devices;
[0077] 6. Remove masking layer, as illustrated by FIG. 10;
[0078] 7. Deposit silicon germanium fill material 1101 into the
etched source/drain region, as illustrated by FIG. 10, to cause
strain region within the channel region of the PMOS devices;
[0079] 8. Form spacer regions 1105 for NMOS devices, as illustrated
by FIG. 11;
[0080] 9. Form silicide material 1201 (e.g., nickel, platinum,
titanium) overlying portions of the NMOS and PMOS gate regions, as
illustrated by FIG. 12;
[0081] 10. Form silicon nitride layer 1203 overlying surface
regions of the spacer regions, NMOS, and PMOS devices;
[0082] 11. Cause strain region within NMOS devices using the
silicon nitride layer, as illustrated by FIG. 12;
[0083] 12. Form interlayer dielectric layer or layers overlying the
NMOS and PMOS devices;
[0084] 13. Form contact regions 1301 to source/drain regions of
each of the NMOS and PMOS devices; and
[0085] 14. Perform other steps, as desired.
[0086] The above sequence of steps provides a method according to
an embodiment of the present invention. As shown, the method uses a
combination of steps including a way of forming a CMOS integrated
circuit device. Other alternatives can also be provided where steps
are added, one or more steps are removed, or one or more steps are
provided in a different sequence without departing from the scope
of the claims herein.
[0087] FIGS. 14-19 are simplified cross-sectional view diagrams
illustrating yet an alternative method for fabricating a CMOS
device according to an embodiment of the present invention. These
diagrams are merely examples, which should not unduly limit the
scope of the claims herein. One of ordinary skill in the art would
recognize many variations, modifications, and alternatives.
[0088] A method illustrating an alternative method for fabricating
a CMOS device according to an alternative embodiment of the present
invention is briefly outlined below.
[0089] 1. Provide semiconductor substrate including trench region
(shallow trench isolation), including PMOS and NMOS devices thereon
(see, FIG. 14);
[0090] 2. Form overlying oxide layer and overlying silicon nitride
layer, as also shown in FIG. 14;
[0091] 3. Form masking layer 1511 overlying NMOS devices;
[0092] 4. Form spacer regions 1501 on PMOS devices using masking
layer 1511 to protect NMOS devices, as illustrated by FIG. 15;
[0093] 5. Form etched source/drain regions for PMOS devices using
the masking layer to product the NMOS devices;
[0094] 6. Remove masking layer;
[0095] 7. Deposit silicon germanium fill material 1503 into the
etched source/drain region, as illustrated by FIG. 15, to cause
strain region within the channel region of the PMOS devices;
[0096] 8. Form silicon nitride layer overlying the NMOS and PMOS
devices, including a portion of the silicon nitride layer and the
oxide layer overlying the NMOS devices, as illustrated by FIG.
16;
[0097] 9. Form mask 1701 overlying PMOS devices, as illustrated by
FIG. 17;
[0098] 10. Form spacer regions 1703 for NMOS devices, as
illustrated by FIG. 17;
[0099] 11. Form etched source/drain regions 1705 for NMOS
devices;
[0100] 12. Form silicon carbide fill material 1801 within the
etched source/drain regions to cause strain region (e.g., tensile)
within the channel region of the NMOS devices;
[0101] 13. Optionally, form silicide material (e.g., nickel,
platinum, titanium) overlying portions of the NMOS and PMOS gate
regions, as illustrated by FIG. 18;
[0102] 14. Form silicon nitride layer 1901 overlying surface
regions of the spacer regions, NMOS, and PMOS devices, as
illustrated by FIG. 19;
[0103] 15. Cause additional strain (e.g., tensile) to the strain
region within NMOS devices using the silicon nitride layer;
[0104] 16. Form interlayer dielectric layer or layers overlying the
NMOS and PMOS devices;
[0105] 17. Form contact regions to source/drain regions of each of
the NMOS and PMOS devices; and
[0106] 18. Perform other steps, as desired.
[0107] The above sequence of steps provides a method according to
an embodiment of the present invention. As shown, the method uses a
combination of steps including a way of forming a CMOS integrated
circuit device. Other alternatives can also be provided where steps
are added, one or more steps are removed, or one or more steps are
provided in a different sequence without departing from the scope
of the claims herein.
[0108] Depending upon the embodiment, there can be various recipes
for forming nigh tensile or high compressive stress silicon nitride
material depending upon the application. As merely an example,
Table 1 lists certain recipes for high tensile (HT) and high
compressive (HC) silicon nitride. TABLE-US-00001 DEP CONDITIONS FOR
HIGH TENSILE AND HIGH COMPRESSIVE STRESS SIN Parameters HT SIN HC
SIN Max Time/s 100 67 Servo/Torr 6 6 HF RF Pwr/W 40 450
SiH4-Lo/sccm 30 30 NH3/sccm 80 80 N2/sccm 9000 9000 Htr
1/2(wafer.about.)/T 400 400 Lift Pos/mils 480 480 Stress/THK = 2K
948 -1483
[0109] Of course, one of ordinary skill in the art would recognize
various modifications, alternatives, and variations.
[0110] It is also understood that the examples and embodiments
described herein are for illustrative purposes only and that
various modifications or changes in light thereof will be suggested
to persons skilled in the art and are to be included within the
spirit and purview of this application and scope of the appended
claims.
* * * * *