U.S. patent application number 11/605272 was filed with the patent office on 2007-03-29 for methods for manufacturing capacitors for semiconductor devices.
Invention is credited to Dong-Woo Kim, Jae-Hee Oh.
Application Number | 20070069271 11/605272 |
Document ID | / |
Family ID | 27656381 |
Filed Date | 2007-03-29 |
United States Patent
Application |
20070069271 |
Kind Code |
A1 |
Kim; Dong-Woo ; et
al. |
March 29, 2007 |
Methods for manufacturing capacitors for semiconductor devices
Abstract
Capacitors for semiconductor devices and methods of fabricating
such capacitors are provided The disclosed capacitor comprises an
interlayer dielectric layer (ILD) pattern having an opening
exposing a portion of the underlying semiconductor substrate, a
silicide pattern formed on the exposed substrate, and a lower
electrode covering an inner wall and bottom of the opening. A
dielectric layer is formed on the lower electrode, and an upper
electrode is disposed on the dielectric layer. The dielectric layer
preferably comprises a high k-dielectric layer such as tantalum
oxide. The disclosed method comprises forming an ILD pattern with
an opening that exposes a portion of a semiconductor substrate
forming an optional silicide pattern on the exposed substrate,
forming a lower electrode on the inner wall of the opening and
sequentially forming a dielectric layer and an upper electrode on
the resulting structure.
Inventors: |
Kim; Dong-Woo; (Yongin-City,
KR) ; Oh; Jae-Hee; (Seongnam-City, KR) |
Correspondence
Address: |
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON
VA
20195
US
|
Family ID: |
27656381 |
Appl. No.: |
11/605272 |
Filed: |
November 29, 2006 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10357383 |
Feb 4, 2003 |
7163859 |
|
|
11605272 |
Nov 29, 2006 |
|
|
|
Current U.S.
Class: |
257/308 ;
257/E21.019; 257/E21.649; 257/E27.086 |
Current CPC
Class: |
H01L 27/10808 20130101;
H01L 27/10855 20130101; H01L 28/91 20130101 |
Class at
Publication: |
257/308 |
International
Class: |
H01L 27/108 20060101
H01L027/108 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 5, 2002 |
KR |
2002-06436 |
Claims
1-12. (canceled)
13. A capacitor of a semiconductor device comprising: an interlayer
dielectric pattern disposed on a semiconductor substrate, the
interlayer dielectric pattern having an opening, the opening
exposing a surface region of the semiconductor substrate; a
silicide pattern formed on the surface region of the semiconductor
substrate exposed through the opening; a lower electrode covering
an inner wall of the opening and the silicide pattern; a dielectric
layer covering an inner wall and a top surface of the lower
electrode; and an upper electrode disposed on the dielectric
layer.
14. A capacitor of a semiconductor device according to claim 13,
wherein the silicide pattern comprises at least one material
selected from a group consisting of titanium silicide and cobalt
silicide.
15. A capacitor of a semiconductor device according to claim 13,
wherein the lower electrode comprises at least one conductive
material selected from a group consisting of titanium nitride,
tungsten and ruthenium.
16. A capacitor of a semiconductor device according to claim 13,
further comprising a heavily doped region formed in the
semiconductor substrate under the opening.
17. A capacitor of a semiconductor device according to claim 13,
wherein the dielectric layer comprises at least one dielectric
material selected from the group consisting of tantalum oxide,
aluminum oxide, titanium oxide, silicon oxide, silicon nitride,
hafnium oxide, BST (Barium Strontium Titanate), and PZT (Lead
Zirconium Titanate).
18. A method of fabricating a capacitor on a semiconductor device
comprising: providing a semiconductor substrate; forming a
interlayer dielectric layer on the semiconductor substrate; forming
a interlayer dielectric pattern, the interlayer dielectric pattern
comprising an opening, the opening comprising an inner wall and
exposing a predetermined surface region of the semiconductor
substrate; forming a metal layer on the interlayer dielectric
pattern; forming a lower electrode layer on the metal layer;
forming a lower electrode on the inner wall of the opening and the
predetermined surface region of the semiconductor substrate;
forming a dielectric layer on the lower electrode; and forming an
upper electrode layer on the dielectric layer.
19. A capacitor of a semiconductor device comprising: an interlayer
dielectric pattern disposed on a semiconductor substrate, the
interlayer dielectric pattern having an opening that exposes a
surface region of the semiconductor substrate, wherein an upper
surface of the interlayer dielectric pattern defines a first plane
and the opening has an inner surface and a depth D.sub.o; a
silicide pattern formed on the exposed surface region of the
semiconductor substrate; a lower electrode covering the inner
surface of the opening and the silicide pattern with an upper
portion of the lower electrode projecting above the first plane by
a height H.sub.e, wherein a ratio of D.sub.o:H.sub.e is no greater
than 10:1; a dielectric layer having a first portion covering
exposed surfaces of the lower electrode and a second portion
extending across the upper surface of the dielectric pattern; and
an upper electrode covering the first portion of the dielectric
layer and a region of the second portion of the dielectric layer
adjacent the opening.
Description
RELATED APPLICATION
[0001] This application claims priority from Korean Patent
Application No. 2002-06436, filed on, Feb. 5, 2002, the contents of
which are herein incorporated by reference in their entirety.
[0002] 1. Field of the Invention
[0003] The present invention relates to semiconductor devices and
methods of fabricating such devices. More specifically, the present
invention is directed to semiconductor devices having utilizing a
metal-insulator-metal (MIM) capacitor structure (hereinafter
referred as an MINI capacitor), and methods of fabricating the
same.
[0004] 2. Background of the Invention
[0005] To reduce fabrication costs of semiconductor devices, it is
necessary to increase the level of integration of the semiconductor
devices and minimize the number of fabricating steps. In the
meantime, as portable electronic devices like cellular phones,
camcorders, and game machines have become popular, a need for
embedded memory logic (EML) semiconductor devices having both
memories and logic circuits has been gradually increasing. In most
such cases, the EML semiconductor devices incorporate DRAM elements
as the memories for high-speed operations.
[0006] FIG. 1 is a cross-sectional view illustrating a method of
fabricating a capacitor of atypical DRAM semiconductor device.
[0007] Referring to FIG. 1, a first interlayer dielectric layer
(ILD) is formed on the semiconductor substrate 10. The first ILD is
then patterned and etched to form a first interlayer dielectric
pattern (ILD pattern) 20 with a first opening 25. The first opening
25 exposes a predetermined region of the semiconductor substrate
10. A conductive contact plug 30 is formed in the first opening 25
to contact the exposed region of the semiconductor substrate
10.
[0008] A second ILD is then formed on an entire surface of the
semiconductor substrate including the contact plug 30. The second
ILD is then patterned and etched to form a second ILD pattern 40
having a second opening 45. The second opening 45 exposes a top
surface of the contact plug 30.
[0009] A lower electrode layer and a sacrificial layer (not shown)
are formed on the entire surface of the semiconductor substrate
including the second ILD pattern 40. Thereafter, an upper portion
of the sacrificial layer and the lower electrode layer are etched
to expose a top surface of the second ILD pattern 40 and leave a
lower electrode 50 and a sacrificial pattern (not shown) filling
the second opening 45. The sacrificial pattern is then removed to
expose an inner wall of the lower electrode 50.
[0010] A dielectric layer 60 and an upper electrode layer are then
sequentially formed on an entire surface of the semiconductor
substrate including the exposed lower electrode 50. The upper
electrode layer is then patterned and etched to expose a portion of
a top surface of the dielectric layer 60 and form an upper
electrode 70 that fills the remaining portion of the second opening
45.
[0011] Fabrication of a DRAM capacitor according to the
conventional method comprises repeatedly performing a series of
photolithographic and etching processes in order to form the first
opening 25, the second opening 45, and the upper electrode 70. The
present invention is directed to a method for decreasing the number
of these photolithographic and etching processes to simplify the
process and reduce the fabrication costs associated with producing
such semiconductor devices.
[0012] In addition, a DRAM cell capacitor typically includes a
lower electrode 50 having a height h.sub.1 of at least about 10,000
.ANG. to realize highly integrated devices and secure a sufficient
capacitance. However, as a result of the relatively extreme height
h.sub.1 of the lower electrode 50, DRAM fabrication processes are
generally not compatible with those of more planar logic circuits.
As a result, attempts to combine these processes makes it difficult
to simplify the fabrication of EML semiconductor devices, and this
may actually increase the fabrication costs and complexity.
Summary of the Invention
[0013] The present invention provides capacitors for semiconductor
devices that are both adequate for incorporation in EML
semiconductor devices and may be produced more simply and less
expensively.
[0014] The present invention also provides methods for fabricating
capacitors for semiconductor devices that allow for fabricating EML
semiconductor devices more simply and/or less expensively.
[0015] The present invention provides a capacitor for a
semiconductor device that is disposed in an interlayer dielectric
layer (ILD) covering a gate pattern and uses a high k-dielectric
insulation layer as a capacitor dielectric layer. The capacitor
comprises an interlayer dielectric layer (ILD) pattern disposed on
a semiconductor substrate and having an opening exposing a top
surface of the semiconductor substrate a silicide pattern formed on
the semiconductor substrate exposed through the opening and a lower
electrode covering an inner wall of the opening where the silicide
pattern is formed. In addition, a dielectric layer covers an inner
wall and a top surface of the lower electrode, and an upper
electrode is disposed on at least a portion of the dielectric
layer.
[0016] At this time the silicide pattern is preferably composed of
titanium silicide (TiSi) or cobalt: silicide (CoSi), and the lower
electrode is preferably composed of at least one conductive
material selected from the group consisting of titanium nitride.
(TiN) tungsten (W), and ruthenium (Ru). Also, the dielectric layer
is composed of at least one insulating material selected from the
group consisting of tantalum oxide (Ta.sub.2O.sub.5) aluminum oxide
(Al.sub.2O.sub.3), titanium oxide (TiO.sub.2), silicon oxide
(SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), hafnium oxide.
(HfO.sub.2) BST(Barium Strontium Titanate), and PZT(Lead Zirconium
Titanate).
[0017] Also, it is preferable that a heavily doped region is
further disposed in the semiconductor substrate under the
opening.
[0018] Another feature of the present invention can be achieved by
a method of fabricating a capacitor of a semiconductor device that
comprises forming a lower electrode of a capacitor in an ILD
covering a gate pattern, such that the lower electrode of the
capacitor contacts the semiconductor substrate. The method
comprises forming an ILD pattern with an opening on a semiconductor
substrate. The opening exposes a predetermined region of the
semiconductor substrate. A silicide pattern is then formed on the
exposed region of the semiconductor substrate. A lower electrode is
formed to cover an inner wall of the opening where the silicide
pattern is formed. Thereafter, a dielectric layer and an upper
electrode layer are sequentially formed on the entire surface of
the semiconductor substrate including the lower electrode.
[0019] Preferably, before forming the first ILD pattern, a heavily
doped region is formed in the semiconductor substrate in a region
below where the opening will be formed in the ILD.
[0020] Forming the silicide pattern comprises forming a metal
layer, preferably titanium or cobalt; on the entire surface of the
semiconductor substrate, including those regions of the exposed by
openings in the ILD pattern, and heating the resulting structure to
react metal and silicon to form of the silicide pattern. Next, the
uncreated portion of metal layer is removed, leaving the silicide
pattern. The uncreated portion of the metal layer is preferably
removed using an etch progress having an etch selectivity; with
respect to the silicide pattern and the ILD pattern.
[0021] Forming the lower electrode comprises sequentially forming a
lower electrode layer and a sacrificial layer on the entire surface
of the semiconductor substrate where the silicide pattern is
formed. The sacrificial layer and the lower electrode layer are
then etched until a top surface of the ILD pattern is exposed,
thereby forming a lower electrode and the sacrificial pattern
filling the openings. The sacrificial pattern is then removed. The
lower electrode is preferably formed from at least one conductive
material selected from the group consisting of titanium nitride
(TiN), tungsten (W), and ruthenium (Ru). Also the sacrificial layer
is preferably formed from at least one material selected from the
group consisting of silicon oxide, SOG materials, and photoresist
materials. The sacrificial pattern is preferably removed using an
etch recipe having an etch selectivity with respect to the ILD
pattern and the lower electrode. The sacrificial pattern may be
removed using an isotropic etch process.
[0022] A dielectric layer and an upper electrode can then be formed
on the lower electrode. The dielectric layer is preferably formed
of at least one material selected from the group consisting of
tantalum oxide (Ta.sub.2O.sub.5), aluminum oxide (A1.sub.20.sub.3),
titanium oxide (TiO.sub.2), silicon oxide (SiO.sub.2), silicon
nitride (Si.sub.3N.sub.4), hafnium oxide (HfO.sub.2), BST (Barium
Strontium Titanate), and PZT (Lead Zirconium Titanate).
Brief Description of the Drawings
[0023] FIG. 1 is a cross-sectional view illustrating a method of
fabricating a capacitor of a conventional DRAM semiconductor
device.
[0024] FIGS. 2 through 7 are cross-sectional views illustrating a
method of fabricating a capacitor for a semiconductor device
according to a first preferred embodiment of the present
invention.
[0025] FIG. 8 is a cross-sectional view illustrating a method of
fabricating a capacitor of a semiconductor device according to a
second preferred embodiment of the present invention;
[0026] FIG. 9 is a graph showing leakage current characteristics of
capacitors formed with varying lower electrode materials.
[0027] FIG. 10 is a perspective view illustrating the capacitor of
the semiconductor device according to the first preferred
embodiment of the present, invention.
[0028] FIG. 11 is a cross-sectional view illustrating a capacitor
according to an exemplary embodiment of the invention.
Description of the Preferred Embodiment
[0029] The present invention is described more fully below with
reference to the accompanying drawings in which preferred
embodiments of the invention are shown. The invention may, however,
be embodied in different forms and should not be construed as
limited to the embodiments set forth or illustrated herein. Rather,
these embodiments are provided so that this disclosure will be
thorough and complete, and will fully convey the scope of the
invention to those skilled in the art. In the drawings, the
thickness of layers and regions are exaggerated for clarity. It
will also be understood that when a layer is referred to as being
"on" another layer or substrate, it can be directly on the other
layer or substrate, or intervening layers may also be present.
[0030] The present invention relates to embedded memory logic,
(EML), semiconductor devices in which capacitors for logic circuits
and cell capacitors for DRAMs comprise similar structures on a
single device. As a result of similarities in the structures, the
following description manufacture and structure of the DRAM of the
cell capacitors may be applied to the capacitors formed for the
corresponding logic circuits.
[0031] FIGS. 2 through 7 are cross-sectional views illustrating a
method of fabricating a capacitor of a semiconductor device
according to a first preferred embodiment of the present
invention.
[0032] Referring to FIG. 2, a device isolation layer (not shown) is
formed at a predetermined region of a semiconductor substrate 100
to define an active region. A gate pattern 110 is formed on the
semiconductor substrate including the device isolation layer, and a
spacer 120 is formed on a sidewall of the gate pattern 110. An ion
implantation process is then conducted using the spacer 120 as a
mask, to form a heavily doped region 130 in the active region. An
etch stop layer and an ILD are then formed on the entire surface of
the semiconductor substrate including the heavily doped region 130.
Thereafter, the ILD and the etch stop layer are successively
patterned and etched to form an ILD pattern 150 and an etch stop
pattern 140, which have an opening 155. In this case, the opening
155 exposes a top surface of the heavily doped region 130.
[0033] The ILD pattern 150 is preferably formed from a silicon
oxide layer. The etch stop pattern 140 is formed of a material
having an etch selectivity (i.e., a lower etch rate) with respect
to the material used to form the ILD pattern 150. The etch stop
pattern 140 is preferably formed from a silicon nitride layer or a
silicon oxynitride layer
[0034] The etching process for forming the opening 155 preferably
comprises etching the ILD using an etch recipe having an etch
selectivity with respect to the etch stop layer. The etch stop
layer is then etched using an etch recipe having an etch
selectivity of at least 2:1 with respect to the semiconductor
substrate 100.
[0035] Referring to FIG. 3, a metal layer (not illustrated) is
formed on the entire surface of the semiconductor substrate
including the opening 155 and the top surface of region 30.
Thereafter, a silicide (self-aligned silicide) process is performed
to selectively form a silicide only where the metal layer is in
contact with silicon. Thus a silicide pattern 160 is formed on the
regions of the semiconductor substrate 100 exposed by opening
155.
[0036] More specifically the silicide process comprises applying a
thermal process to the semiconductor substrate in contact with the
metal layer. During the thermal process, metal atoms from the metal
layer covering the silicon at the bottom of opening 155 react with
silicon atoms from the semiconductor substrate 100 to form the
suicide pattern 160. During this silicide process the portion of
the metal layer which is not in contact with the semiconductor
substrate 100 remains uncreated and does not form silicide. For
example, the portion of the metal layer covering the ILD pattern
150 and the sidewalls of the opening 155 does not form silicide.
After the thermal process, the uncreated portion of the metal layer
is selectively removed leaving as illustrated in FIG. 3, the
silicide pattern 160 on the substrate at the bottom of the opening
155.
[0037] The metal layer is preferably formed of titanium (Ti) or
cobalt (Co). The metal layer is preferably removed using an
isotropic etch process with an etch recipe having an etch
selectivity with respect to the materials used to form the ILD
pattern 150 and the silicide pattern 160.
[0038] Referring, to FIG.4 a lower electrode layer 170 and a
sacrificial layer 180 are sequentially formed on the entire surface
of the semiconductor substrate including the silicide pattern
160.
[0039] To realize process simplification, the capacitor of the
present invention includes the lower electrode formed in direct
contact with the heavily doped region 130 without a contact plug 30
as illustrated in FIG. 1 and described in the Background of the
Invention. The width of the opening 155 is preferably as narrow as
possible so as to achieve a high level of integration of the
semiconductor devices. As a result, the opening 155 has a high,
e.g., at least about 10:1, aspect ratio. Thus, the lower electrode
layer 170 is preferably formed of titanium nitride (TiN) or similar
material that exhibits good step coverage characteristics. The
titanium nitride (TiN; layer is preferably formed by chemical vapor
deposition (CVD), or atomic layer deposition (ALD). If the titanium
nitride layer is formed in direct contact with the heavily doped
region 130, contact resistance may become excessive. According to
the present invention, the silicide pattern 160 is formed to reduce
or eliminate such contact resistance problems.
[0040] The sacrificial layer 180 is formed to facilitate subsequent
planarizing. processes. Thus the sacrificial layer 180 preferably
exhibits good gap-filling characteristics in order to fill the
opening 155 completely despite the high aspect ratio described
above. In addition, the sacrificial layer 180 is removed after the
planarizing etch process. And this may cause the ILD pattern 150 to
be recessed. Accordingly, the material used to form the sacrificial
layer 180 should also exhibit a good etch selectivity with respect
to the ILD pattern 150. For these reasons the sacrificial layer 180
is preferably formed of at least one material selected from silicon
oxide with a high etch rate, SOG materials, and photoresist
materials.
[0041] Referring to FIG. 5, a lower electrode separation process is
performed to expose a top surfaces of the ILD pattern 150. Thus,
the lower electrode layer 170 is etched to form a lower electrode
175 covering an inner wall of the opening 155 and contacting the
silicide pattern. The sacrificial layer 180 is also etched during
the lower electrode separation process to form a sacrificial
pattern 185 that fills the space between portion of opening 155 the
inner walls of the lower electrode 175.
[0042] The lower electrode separation process is preferably a
planarizing etch process using chemical mechanical polishing (CMP).
As a result, top surfaces of the lower electrode 175, the
sacrificial pattern 185, and the ILD pattern 150 are exposed and
planarized.
[0043] Referring to FIG. 6, the exposed sacrificial pattern 185 is
then removed to expose the inner wall of the lower electrode 175.
The sacrificial pattern 185 is preferably removed using an etch
recipe having a good etch selectivity, i.e., a selectivity ratio of
at least 10, with respect to both the lower electrode 175 and the
ILD pattern 150. The sacrificial pattern 185 is preferably removed
using an isotropic etch process and more preferably, a wet etch
process.
[0044] In general, the sacrificial pattern 185 has a nearly
complete etch selectivity (e.g., a selectivity greater than about
20) with respect to the metal materials used to form the lower
electrode 175. However, the sacrificial pattern 185 may not have a
nearly complete etch selectivity with respect to the materials,
*such as oxide, used to form the ILD pattern 150. Thus, the surface
of the ILD pattern 150 may become recessed while the sacrificial
pattern 185 is being removed. As a result, the ILD pattern 150 may
have a top surface lower than the upper portion of the lower
electrode 175 as illustrated in FIG. 6.
[0045] Referring to FIG. 7, a dielectric layer 190 and an upper
electrode layer 200 are conformally formed on the entire surface of
the semiconductor substrate after the sacrificial pattern 185 has
been removed. Thereafter, a gap fill layer 210 is formed on the
entire surface of the semiconductor substrate including the upper
electrode layer 200.
[0046] The incompatibility of the processes for fabricating DRAMs
and logic circuits, which is a problem in the conventional method,
results from the high relative height of the DRAM cell capacitor.
However, if the height of the DRAM cell capacitor is reduced in
order to render the process more compatible with logic circuit
structures, the surface area of the capacitor electrode is
similarly reduced affecting the capacitance of the cell capacitor
and increasing the likelihood of soft errors.
[0047] As is well known to those skilled in the art, the
capacitance of a capacitor is proportional to the dielectric
constant of a dielectric layer and the surface area of the
capacitor electrode, and inversely proportional to the distance
between capacitor electrodes. Thus, if the surface area of the
capacitor electrode is reduced, the distance between the capacitor
electrodes should be reduced and/or the capacitor dielectric layer
should be formed from a material with a higher dielectric constant
in order to maintain sufficient capacitance. However, techniques
for reducing the distance between the capacitor electrodes have
reached the technical limits due to an increase in a leakage
current resulting from such reductions. For this reason, it is
preferred that the capacitor dielectric layer be formed of a high-k
dielectric material so that the height of the capacitor may be
reduced while maintaining the necessary capacitance.
[0048] Thus, the dielectric layer 190 is preferably formed from at
least one material selected from the group consisting of tantalum
oxide (Ta.sub.2O.sub.5), aluminum oxide (Al.sub.20.sub.3), titanium
oxide (TiO.sub.2), silicon oxide (SiO.sub.2), silicon nitride,
(Si.sub.3N.sub.4), and hafnium oxide (HfO.sub.2) Alternatively,;
the dielectric layer 190 may be formed of one material selected
from the group consisting of ZrO.sub.2, Nb.sub.2Q.sub.5, CeO.sub.2,
Y.sub.2O.sub.3, InO.sub.3, IrO.sub.2, SrTiO.sub.3, PbTiO.sub.3,
SrRuO.sub.3, CaRuO.sub.3, (Ba,Sr)TiO.sub.3, (BST),
Pb(Zr,Ti)O.sub.3, (PET) (Pb,La)(Zr,Ti)O.sub.3, and
(Sr,Ca)RuO.sub.3.
[0049] The upper electrode 200 is preferably formed of at least one
material selected from titanium nitride (TiN), titanium (Ti),
cobalt (Co), tungsten (W), and ruthenium (Ru). Also, the gap fill
layer 210 is formed to fill the remaining inner space of the
opening 155 where the upper electrode 200 is formed. Preferably,
the gap fill layer 210 is tungsten (W) or silicon oxide
(SiO.sub.2).
[0050] The gap fill layer 210 and the upper electrode layer 200 are
then patterned and etched to form an upper electrode (not shown)
and a gap fill pattern (not shown), which extend over the opening
155. In an alternative embodiment, the gap fill layer 210 may be
formed after the upper electrode layer 200 has been patterned and
etched.
[0051] FIG. 8 is a cross-sectional view illustrating a method of
fabricating a capacitor of a semiconductor device according to a
second preferred embodiment of the present invention. Since the
second preferred embodiment includes fabricating steps in FIG. 2,
the description of those steps will be omitted here for
brevity.
[0052] Referring to FIGS 2 and 8, after forming the ILD pattern,
150, with the opening 155, a metal layer, a lower electrode layer,
and a sacrificial layer are sequentially formed on the resultant
structure. It is preferred that a rapid thermal process (RTP) is
further performed after forming the metal layer, to produce an
ohmic contact between the metal layer and the heavily doped region
130.
[0053] By performing the lower electrode separating on process
illustrated in FIG. 5 and described above a metal pattern 165, a
lower electrode 175, and a sacrificial pattern (not shown) are
sequentially formed to fill the opening 155. Thereafter, the same
fabricating steps, illustrated in FIG. 6 and described above are
performed to expose an inner wall of the lower electrode 175. Next,
as described in FIG. 7, a dielectric layer 190, an upper electrode
layer 200, and a gap fill layer 210 are sequentially formed on the
entire surface of the resultant structure after the sacrificial
pattern is removed.
[0054] In the second preferred embodiment, the silicide process
illustrated in FIG. 3 and described above is omitted. Thus, the
metal pattern 165 has a top surface higher than the ILD pattern 150
at top surface of the ILD pattern 150 (see 99). As illustrated in
FIG.8, because the metal pattern 165 is formed of titanium, the
leakage current of the capacitor may increase.
[0055] FIG. 9 is a graph showing the leakage current
characteristics of the capacitor according to type, of materials
used to form lower electrode of the capacitor. Reference numeral 1
identifies the leakage current results of an experiment on the
capacitor in which the titanium layer has a top surface higher than
the ILD pattern as illustrated in FIG. 8. Reference numeral 2
identifies the leakage current results of an experiment on the
capacitor, in which the titanium layer is not exposed on the ILD
pattern. The horizontal and vertical axes of the graph in FIG.9 r t
o the applied voltages and the measured leakage currents,
respectively.
[0056] Referring to FIG. 9 under an applied voltage of 1.0V, the
leakage current 1 of the capacitor where titanium layer is exposed
on the ILD pattern 150 was measured to be about 10.sup.-12
A/.mu..sup.2. By comparison, under the same voltage conditions, the
leakage current 2 of the capacitor where the titanium layer has a
top surface lower than the ILD pattern 150 was measured to be about
10.sup.-5 A/.mu.m.sup.2. That is, the capacitor (corresponding to
FIG. 7) where the titanium layer is not exposed enables the leakage
current to be reduced more than, 1,000 times compared to the
capacitor (corresponding to FIG. 8) where the titanium layer is
exposed.
[0057] Consequently, the first preferred embodiment may minimize
the leakage current more effectively than the second preferred
embodiment.
[0058] Moreover, in both of the preferred embodiments of the
present invention, a photolithographic etching process need be
performed only twice to form the opening 155 and the upper
electrode. In contrast, when a capacitor is formed according to the
conventional method, a photolithographic etching process must be
performed three times. The number of the photolithographic etching
processes directly affects the fabrication costs. Therefore, the
present invention has the advantage of markedly reducing
fabrication costs when compared to the conventional method.
[0059] FIG. 10 is a perspective view illustrating the capacitor of
the semiconductor device according to the first preferred
embodiment of the present invention. Referring to FIG. 10, a device
isolation layer 105 is disposed at a predetermined region of a
semiconductor substrate 100 to define an active region. A gate
pattern 110 is disposed on the active region to cross the device
isolation layer 105 and the active region. Spacers 120 are disposed
on both sidewalls of the gate pattern 110. A heavily doped region
130 is disposed in the active region between the spacers 120.
[0060] An ILD pattern 150 preferably silicon dioxide, with an
opening 155 is disposed on the entire surface of the semiconductor
substrate including the gate pattern 110 and the spacer 120. The
opening 155 exposes a predetermined region of the heavily doped
region 130. An etch stop pattern 140 is preferably disposed under
the ILD pattern 150. The etch stop pattern 140 is preferably formed
of a material that exhibits a good etch selectivity with respect to
the material used to form the ILD pattern 150.
[0061] A silicide pattern 160 is disposed on the heavily doped
region 130 under the opening 155. A lower electrode 175, a
dielectric layer 190, and an upper electrode 205 are sequentially
stacked on an inner wall of the opening 155 where the silicide
pattern 160 is disposed. The upper electrode 205 and the dielectric
layer 190 are extended, from the inner wall of the opening 155 to
cover the ILD pattern 150.
[0062] The silicide pattern 160 is preferably formed of titanium
silicide or cobalt silicide. The lower electrode 175 is preferably
formed of at least one material selected from the group consisting
of titanium nitride (TiN), tungsten (W), and ruthenium (Ru).
[0063] The upper electrode 205 is preferably formed of at least one
conductive material selected from the group consisting of titanium
nitride (TiN), titanium (Ti), cobalt (Co),tungsten (W), and
ruthenium (Ru). The dielectric layer 190 is preferably formed from
at least one insulating material selected from the group consisting
of tantalum oxide (Ta.sub.2O.sub.5), an aluminum oxide
(Al.sub.2O.sub.3), titanium oxide (TiO.sub.2), silicon oxide layer
(SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), hafnium oxide
(HfO.sub.2) material ZrO.sub.2, Nb.sub.2O.sub.5, CeO.sub.2,
Y.sub.2O.sub.3, InO.sub.3, IrO.sub.2, SrTiO.sub.3, PbTiO.sub.3,
SrRuO.sub.3, CaRuO.sub.3(Ba,Sr)TiO.sub.3 (BST), Pb(Zr,Ti)O.sub.3
(PZT), (Pb,La)(Zr,Ti)O.sub.3 and (Sr,Ca)RuO.sub.3.
[0064] If the opening 155 is not completely filled with the upper
electrode 205, a gap fill pattern (not shown) for filling the
remainder of opening 155 may be used.
[0065] In the present invention, it is assumed that the cell
capacitors for DRAMs and the capacitors for logic circuits exhibit
the same basic structure, so descriptions are limited to the cell
capacitors for DRAMs and methods of fabricating such capacitors.
However, the dielectric layer of capacitors for logic circuits may
be thicker than and/or formed from a different material, then the
dielectric used in a DRAM capacitor. Since such an alternative is
believed apparent to those skilled in the art, a detailed
description of this variation is considered unnecessary.
[0066] According to the present invention, a capacitor of a
semiconductor device may be formed by performing a
photolithographic etching process only twice. Thus, the present
invention is more effective than conventional methods requiring the
same basic processes to be performed three times. Also according to
the present invention a capacitor dielectric layer may be formed,
from a high k-dielectric layer to maintain a desired capacitance
level while lowering the height of the capacitor. As a result,
embedded memory logic (EML) semiconductor devices having both logic
circuits and DRAMS can be effectively fabricated using a simplified
process.
* * * * *