Method for producing a memory with high coupling ratio

Abstract

A method for producing a memory with high coupling ratio is provided. First, a shallow trench isolation is formed on a substrate to define an active area. Second, a spacer is formed at the sidewall of the shallow trench isolation. Third, the shallow trench isolation is etched such that the top of the spacer is higher than the surface of the shallow trench isolation. Fourth, a tunnel oxide is formed on the active area. Finally, a floating gate is formed on the tunnel oxide.

Description

RELATED APPLICATIONS

[0001] The present application is based on, and claims priority from, Taiwan Application Serial Number 94130391, filed Sep. 5, 2005, the disclosure of which is hereby incorporated by reference herein in its entirety.

BACKGROUND

[0002] 1. Field of Invention

[0003] The present invention relates to a method for producing a memory. More particularly, the present invention relates to a method for producing a memory with high coupling ratio.

[0004] 2. Description of Related Art

[0005] Memory-related technology is progressing rapidly. Because of the high market demand for lighter, thinner and smaller products, flash memory is extensively used and has become a main nonvolatile memory nowadays. Because the physical size of the memory is becoming smaller and smaller, the size of each memory cell within the memory structures also must be made smaller, which results in decreasing the overlapping area of a floating gate and a control gate in each memory cell. Therefore, the coupling ratio of the floating gate and the control gate decreases. Because of low coupling ratio, the memory requires a higher voltage applied on its control gate to function. Not only the efficiency of the memory but also the reliability of the memory becomes less over a long time. Moreover, the conventional memory has a serious parasitic transistor effect that is described in detail below.

[0006] FIG. 1 to FIG. 3 show a conventional nonvolatile memory cell at different steps of the manufacturing process. In FIG. 1, a shallow trench isolation 106 in a substrate 102 can be used to define an active area 111 of a memory cell. A pad oxide 103 is located on the substrate 102. A liner oxide 104 is located around the shallow trench isolation 106. The pad oxide 103 functions as a buffer layer between a hard mask and the substrate 102. After the hard mask is removed, the surface of the shallow trench isolation 106 is apparently higher than that of the substrate 102.

[0007] Reference is made to FIG. 2. A wet etching process is performed to remove the pad oxide 103 from the substrate 102, and the upper surface of the shallow trench isolation 106 is lowered to approximate to the upper surface of the substrate 102. Then, a tunnel oxide 105 is formed at the same place where the pad oxide 103 originally is. Since the wet etching process used to remove the pad oxide 103 is isotropic, the side of the shallow trench isolation 106 is usually etched to form a concave portion 109.

[0008] In FIG. 3, a polysilicon layer is deposited on the substrate 102. Then, lithography and etching processes are performed on the polysilicon layer to form a floating gate 108. When the polysilicon layer is deposited on the substrate 102, some polysilicon material also fills in the concave portion 109 at the side of the shallow trench isolation 106. The presence of the polysilicon in the concave portion 109 causes difficulties in performing the subsequent etching process. Furthermore, there is likely an electric leakage in the region of the concave portion 109, which adversely effects the operation and reliability of the memory.

SUMMARY

[0009] It is therefore an aspect of the present invention to provide a method for producing a memory. The memory has high coupling ratio, the memory thus can read and write data faster.

[0010] Another aspect of the present invention relates to a method for producing a memory structure, wherein a concave portion is not formed on the edge of shallow trench isolation during wet etching process, and thus electric leakage is reduced.

[0011] In accordance with the foregoing aspects, one embodiment of the present invention provides a method for producing a memory. First, a shallow trench isolation is formed on a substrate to define an active area. Second, a spacer is formed at the sidewall of the shallow trench isolation. Third, the shallow trench isolation is etched such that the top of the spacer is higher than the surface of the shallow trench isolation. Fourth, a tunnel oxide is formed on the active area. Finally, a floating gate is formed on the tunnel oxide.

[0012] Since the spacer protects the edge of the shallow trench isolation from being etched and from being concave portiond in the etching process, electric leakage does not occur when the memory is functioning. Furthermore, the fact that the top of the spacer is higher than the surface of the shallow trench isolation results in a curvature on the surface of the floating gate when the floating gate is formed on the substrate. The surface area of the floating gate is therefore increased, which allows a greater overlapping area between the floating gate and the control gate and increases the coupling ratio of the memory structure. Accordingly, the memory of the present invention can function more efficiently and is more reliable.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings as follows:

[0014] FIG. 1 to FIG. 3 are cross-sectional side views of a conventional nonvolatile memory cell at different steps of the manufacturing process.

[0015] FIG. 4 to FIG. 8 are cross-sectional side views of a nonvolatile memory cell at different steps of the manufacturing process according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The memory structure described herein is mainly a nonvolatile memory, particularly a flash memory. A flash memory is exemplified below to illustrate the characteristics and the concept of the present invention.

[0017] A flash memory is composed of a plurality of memory cells. Each of the memory cells is isolated by an isolation structure. In a preferred embodiment of the present invention, the isolation structure is a shallow trench isolation. Since each memory cell has the same structure, the description below only describes the structure of a single memory cell.

[0018] FIG. 4 is a cross-sectional side view of a memory cell when shallow trench isolations are formed. A shallow trench isolation 206 located in a substrate 202 is for defining an active area 211 of a memory cell. Furthermore, a pad oxide 203 is on the surface of the substrate 202 and serves as a buffer layer between a hard mask and the substrate 202. Around the shallow trench isolation 206 is a liner layer, e.g. a liner oxide 204. In a preferred embodiment of the present invention, the substrate 202 comprises silicon. To form the structure shown in FIG. 4, a pad oxide 203 is first formed on the substrate 202 by oxidation at high temperature. Next, a silicon nitride layer is deposited thereon as a hard mask for a subsequent etching process. Before the etching process is performed, the pattern on a photoresist is transferred to the hard mask by lithography and etching. The patterned hard mask is used as an etch mask in the etching process, so as to form a shallow trench 207 in the substrate 202. A liner oxide 204 is then formed on the shallow trench 207. Finally, the shallow trench 207 is filled with an isolation material, such as silicon oxide, to form a shallow trench isolation 206. The shallow trench 207 is generally formed by an anisotropic etching process.

[0019] Reference is made to FIG. 5, which is a cross-sectional side view showing a structure after forming a spacer at the sidewall of the shallow trench isolation. First, a spacer material layer is deposited on the substrate 202. The spacer material layer is then etched by anisotropic etching to form a spacer 210 at the sidewall of the shallow trench isolation 206. The material of the spacer material layer is a dielectric material like silicon nitride, silicon oxynitride, doped polysilicon, or silicon oxide having an etching rate slower than the material of the shallow trench isolation. The deposition method can be, for example, chemical vapor deposition (CVD) or high temperature oxidation (HTO). As shown in FIG. 5, the spacer 210 covers the sidewall of the shallow trench isolation 206, thereby preventing a concave portion from forming.

[0020] FIG. 6 shows a cross-sectional side view of a memory cell when forming a tunnel oxide. First, the pad oxide 203 is removed. At the same place where the pad oxide 203 is originally, a tunnel oxide 205 is formed. When removing the pad oxide 203, the upper surface of the shallow trench isolation 206 is lowered approximate to the upper surface of the substrate 202, and the spacer 210 therefore protrudes from the surface of the substrate 202 and the shallow trench isolation 206. The tunnel oxide 205 is formed by, for instance, a thermal oxidation process.

[0021] In a preferred embodiment of the present invention, the removal of the pad oxide 203 and the reduction of the height of the shallow trench isolation 206 are performed by isotropic etching, preferably by a wet etching. The solution for the wet etching can be hydrofluoric acid, diluted hydrofluoric acid or buffered hydrofluoric acid, which is determined according to the required quality and etching rate.

[0022] FIG. 7 is a cross-sectional side view of a memory cell when forming a floating gate. The material of the floating gate 208 can be polysilicon, amorphous silicon, silicon nitride or other materials that can store electrical charges. In this embodiment, the material of the floating gate is polysilicon. The floating gate 208 is formed by depositing polysilicon and subsequently performing lithography and etching processes.

[0023] FIG. 8 shows a cross-sectional side view of a memory cell when forming a gate dielectric and a control gate. In a preferred embodiment, the gate dielectric 212 is formed on the floating gate 208. Preferably, the gate dielectric is silicon oxide/silicon nitride/silicon oxide, and the material of the control gate is polysilicon. Finally, a control gate 214 is formed by depositing polysilicon on the substrate 202 and then performing lithography and etching processes.

[0024] In another embodiment of the present invention, the memory cell is formed by sequentially depositing a polysilicon layer, a gate dielectric layer and a polysilicon layer, and then performing lithography and etching processes to define the floating gate 208, the gate dielectric 212, and the control gate 214.

[0025] The term "coupling ratio" is used to indicate the overlapping area of the control gate 214 with the floating gate 208. As the coupling ratio increases, the operation efficiency of memory is improved and the memory can be erased at a higher speed. Generally, the coupling ratio can be increased by the thickness reduction of the gate dielectric 212. However, increasing the coupling ratio by this method is limited since the thickness of the gate dielectric 212 generally ranges from a minimum of 80 .ANG. to 90 .ANG..

[0026] In the memory structure of the preferred embodiment, the top of the spacer 210 is higher than the upper surface of the shallow trench isolation 206. When the floating gate 208 is formed on the spacer, the surface of the floating gate 208 is rippled and thus the surface areas of the floating gate 208, the gate dielectric 212 and the control gate 214 thereon are also increased. Therefore, the overlapping area between the floating gate 208 and the control gate 214 is increased, and the coupling ratio is increased.

[0027] Accordingly, the present invention has the following advantages.

[0028] (1) The memory of the embodiment comprises a spacer to protect the edge of the shallow trench isolation so that a problem of corner oxide thinning that usually occurs in the concave portion at the sidewall of the shallow trench isolation can be avoided. Also, no unwanted materials are left in the concave portion, and thus electric leakage is reduced.

[0029] (2) The memory of the embodiment has high coupling ratio, and thus has better efficiency and higher reliability.

[0030] The preferred embodiments of the present invention described above should not be regarded as limitations to the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the scope or spirit of the invention. The scope of the present invention is as defined in the appended claims.

Claims

1. A method for producing a memory cell, the method comprising: forming a shallow trench isolation in a substrate to define an active area; forming a spacer at a sidewall of the shallow trench isolation; etching the shallow trench isolation such that a top of the spacer is higher than an upper surface of the shallow trench isolation; forming a tunnel oxide on the active area; and forming a floating gate on the tunnel oxide.

2. The method for producing a memory cell of claim 1, wherein the step of forming the spacer comprises: depositing a spacer material layer on the substrate; and anisotropically etching the spacer material layer to form the spacer.

3. The method for producing a memory cell of claim 2, wherein the step of depositing a spacer material layer is performed by a chemical vapor deposition process or a high temperature oxidation process.

4. The method for producing a memory cell of claim 2, wherein the anisotropic etching is a dry etching.

5. The method for producing a memory cell of claim 2, wherein the spacer material layer is silicon nitride.

6. The method for producing a memory cell of claim 2, wherein the spacer material layer is silicon oxynitride.

7. The method for producing a memory cell of claim 2, wherein the spacer material layer is silicon oxide having an etching rate slower than the shallow trench isolation.

8. The method for producing a memory cell of claim 2, wherein the spacer material layer is doped polysilicon.

9. The method for producing a memory cell of claim 1, further comprising: forming a gate dielectric on the floating gate; and forming a control gate on the gate dielectric.

10. A method for producing a memory, the method comprising: forming a shallow trench isolation in a substrate; forming a spacer at a sidewall of the shallow trench isolation, wherein a top of the spacer is higher than an upper surface of the shallow trench isolation; forming a tunnel oxide on the substrate; forming a floating gate on the tunnel oxide and the spacer; forming a gate dielectric on the floating gate; and forming a control gate on the gate dielectric.

11. The method for producing a memory of claim 10, wherein the step of forming the spacer comprises: depositing a spacer material layer on the substrate; etching the spacer material layer to form the spacer at the sidewall of the shallow trench isolation; and lowering a height of the shallow trench isolation such that the top of the spacer is higher than the upper surface of the shallow trench isolation

12. The method for producing a memory of claim 11, wherein the step of lowering the height of the shallow trench isolation comprises performing a wet etching process to remove the material on the top of the shallow trench isolation.

13. The method for producing a memory of claim 10, wherein the material of the spacer is silicon nitride.

14. The method for producing a memory of claim 10, wherein the material of the spacer is silicon oxide with an etching rate slower than the material of the shallow trench isolation.

15. The method for producing a memory of claim 10, wherein the step of forming a shallow trench isolation comprises: forming a shallow trench in a substrate; forming a liner layer on an inner surface of the shallow trench; and filling a dielectric material in the shallow trench.