U.S. patent application number 11/594536 was filed with the patent office on 2007-03-08 for non-contact etch annealing of strained layers.
This patent application is currently assigned to Silicon Genesis Corporation. Invention is credited to Francois Henley, Igor Malik, Philip Ong.
Application Number | 20070051299 11/594536 |
Document ID | / |
Family ID | 32042210 |
Filed Date | 2007-03-08 |
United States Patent
Application |
20070051299 |
Kind Code |
A1 |
Ong; Philip ; et
al. |
March 8, 2007 |
Non-contact etch annealing of strained layers
Abstract
The present invention provides a method of forming a strained
semiconductor layer. The method comprises growing a strained first
semiconductor layer, having a graded dopant profile, on a wafer,
having a first lattice constant. The dopant imparts a second
lattice constant to the first semiconductor layer. The method
further comprises growing a strained boxed second semiconductor
layer having the second lattice constant on the first semiconductor
layer and growing a sacrificial third semiconductor layer having
the first lattice constant on the second semiconductor layer. The
method further comprises etch annealing the third and second
semiconductor layer, wherein the third semiconductor layer is
removed and the second semiconductor layer is relaxed. The method
may further comprises growing a fourth semiconductor layer having
the second lattice constant on the second semiconductor layer,
wherein the fourth semiconductor layer is relaxed, and growing a
strained fifth semiconductor layer having the first semiconductor
lattice constant on the fourth semiconductor layer. The method
controls the surface roughness of the semiconductor layers. The
method also has the unexpected benefit of reducing dislocations in
the semiconductor layers.
Inventors: |
Ong; Philip; (Milpitas,
CA) ; Henley; Francois; (Aptos, CA) ; Malik;
Igor; (Palo Alto, CA) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW, LLP
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Assignee: |
Silicon Genesis Corporation
San Jose
CA
|
Family ID: |
32042210 |
Appl. No.: |
11/594536 |
Filed: |
November 7, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10701723 |
Nov 4, 2003 |
7147709 |
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11594536 |
Nov 7, 2006 |
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10264393 |
Oct 4, 2002 |
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11594536 |
Nov 7, 2006 |
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Current U.S.
Class: |
117/43 ;
257/E21.102; 257/E21.12; 257/E21.129 |
Current CPC
Class: |
H01L 21/02532 20130101;
H01L 21/0251 20130101; H01L 21/0243 20130101; C30B 33/00 20130101;
H01L 21/02658 20130101; H01L 21/02381 20130101; H01L 21/0245
20130101; H01L 21/02573 20130101; H01L 21/3065 20130101; H01L
21/02505 20130101 |
Class at
Publication: |
117/043 |
International
Class: |
C30B 13/00 20060101
C30B013/00 |
Claims
1-15. (canceled)
16. A method comprising: forming over a strained semiconductor
layer having a lattice constant, a second strained semiconductor
layer also having the lattice constant; forming a sacrificial
semiconductor layer having a second lattice constant on said second
semiconductor layer; annealing the sacrificial semiconductor layer
and the second strained semiconductor layer in an etching ambient
to remove the sacrificial semiconductor layer and reduce strain in
a second semiconductor layer; forming a relaxed semiconductor layer
having the lattice constant on the second semiconductor layer; and
forming a third strained semiconductor layer having the lattice
constant on the relaxed semiconductor layer.
17. The method of claim 17 wherein at least one of the strained
semiconductor layer, the second strained semiconductor layer, the
sacrificial semiconductor layer, the relaxed semiconductor layer,
and the third strained semiconductor layer are formed by epitaxial
deposition of graded silicon germanium.
18. The method of claim 17 wherein the epitaxial deposition is
performed in a hydrogen-chloride ambient.
19. The method of claim 16 further comprising: providing a
substrate having the second lattice constant; and forming the
strained semiconductor layer with a graded dopant profile on the
substrate.
20. The method of claim 19 wherein the graded dopant profile
imparts the lattice constant to the strained semiconductor
layer.
21. The method of claim 16 wherein the etching ambient comprises a
halogen bearing etchant.
22. The method of claim 21 wherein said halogen bearing etchant is
hydrogen chloride.
23. The method of claim 21 wherein said halogen bearing etchant is
hydrogen fluoride.
24. The method of claim 21 wherein etching ambient further
comprises hydrogen.
25. The method of claim 21 wherein the annealing increases a
temperature of the sacrificial semiconductor layer. to between
about 700-1200.degree. C.
26. A method of controlling the surface roughness of a strained
semiconductor material comprising: forming a first strained
semiconductor layer having a graded dopant profile on a wafer
having a first lattice constant, the dopant imparting a second
lattice constant to the first semiconductor layer; forming a second
strained semiconductor layer having said second lattice constant on
the first semiconductor layer; forming a sacrificial semiconductor
layer having the first lattice constant on the second semiconductor
layer; and etch annealing the third and second semiconductor layer,
wherein said third semiconductor layer is removed and said second
semiconductor layer is relaxed.
27. The method of claim 26 wherein the etch annealing comprises
exposing the third semiconductor layer to an etch ambient
comprising a halogen bearing etchant.
28. The method of claim 27 wherein said halogen bearing etchant is
hydrogen chloride.
29. The method of claim 27 wherein said halogen bearing etchant is
hydrogen fluoride.
30. The method of claim 26 wherein etch annealing said surface of
the third semiconductor layer further comprises exposing the third
semiconductor layer to hydrogen.
31. The method of claim 26, wherein etch annealing said third
semiconductor layer further comprises increasing a temperature of
said third semiconductor layer. to between 700 and 1200 degrees
Celsius.
32. The method of claim 26 wherein at least one of the first
strained semiconductor layer, the second strained semiconductor
layer, and the sacrificial semiconductor layer are formed by
epitaxial deposition of graded silicon germanium.
33. The method of claim 32 wherein the epitaxial deposition is
performed in a hydrogen-chloride ambient.
34. A method of reducing dislocations in a semiconductor material
comprising relaxing a strained semiconductor layer having a first
lattice constant by etch annealing to remove an overlying
sacrificial semiconductor layer having a second lattice constant,
the strained semiconductor layer formed over a second strained
second semiconductor layer having a second lattice constant
imparted by a graded dopant profile.
35. The method of claim 34 wherein the etch annealing comprises
exposing the strained semiconductor layer and the sacrificial
semiconductor layer to an etch ambient comprising a halogen bearing
etchant.
36. The method of claim 34 wherein said halogen bearing etchant is
hydrogen chloride.
37. The method of claim 34 wherein said halogen bearing etchant is
hydrogen fluoride.
38. The method of claim 34 wherein the etch annealing further
comprises exposing the strained semiconductor layer and the
sacrificial semiconductor layer to hydrogen.
Description
RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional
Application No. 60/484,181; filed Jun. 30, 2003, and is a
continuation-in-part of U.S. application Ser. No. 10/264,393, filed
Oct. 4, 2002.
FIELD OF THE INVENTION
[0002] Embodiments of the present invention relate to controlling
the growth and morphology of surface roughness during an annealing
and relaxation process of strained films, and more particularly to
decreasing surface crystalline dislocations during a relaxation
process.
BACKGROUND OF THE INVENTION
[0003] In the conventional art, many semiconductor device
fabrication processes utilize planar surfaces. Furthermore, as
semiconductor fabrication technology progresses, increasing carrier
mobility and decreasing lattice dislocation density become
increasingly critical. Improving device yields by reducing
dislocations provides for improved manufacturing efficiencies and
cost.
[0004] In the conventional art, a silicon layer is used as the
active device medium upon which semiconductor devices are
fabricated. Single-crystal silicon has a specific carrier mobility
value that is fundamental to the material. The mobility value is a
key parameter in many active semiconductor devices. Often, it is
desired to enhance or increase the device carrier mobility value to
increase the switching speed and therefore the performance of the
fabricated devices such as transistors. Because of the many
fundamental and specific advantages in utilizing silicon as the
semiconductor material, it is highly desirable to adopt methods to
enhance silicon mobility instead of utilizing higher mobility
materials that are harder to process such as Germanium or Gallium
Arsenide.
[0005] One practical method of enhancing silicon mobility is by
straining the silicon layer. By placing the active silicon under
tension, significantly higher mobility resulting in higher device
switching speed and drive currents can be achieved.
[0006] A method of generating such tensile strained silicon
involves growing the silicon layer epitaxially above a relaxed
silicon germanium film of a specific composition. This effect
occurs because the silicon lattice constant, about 5.43 Angstroms,
is smaller than the lattice constant of a fully relaxed silicon
germanium alloy film. Such alloys can be engineered to have a
lattice spacing linearly varying from 5.43 Angstroms (100% silicon)
to 5.65 Angstroms (100% germanium). For the pure germanium film,
the lattice spacing is about 4% larger than pure silicon. Thus for
example, a Si.sub.0.75Ge.sub.0.25 alloy (25% germanium content)
would have a lattice constant about 1% larger than silicon.
[0007] The strained silicon film could therefore be advantageously
fabricated by epitaxially growing the device silicon film on a
relaxed silicon Germanium (SiGe) alloy film of the requisite
composition.
[0008] A fundamental complication of this mobility enhancement
approach is the requirement of a relaxed SiGe film. If the SiGe
film is grown onto a base silicon wafer, the film will first grow
in a lattice-matched manner as a compressive layer. This means that
the SiGe alloy will be compressed to the natural silicon lattice
spacing and will be strained. Since the function of the alloy film
requires a relaxation of the compressive strain, there must be a
step where the SiGe alloy is relaxed to its unstrained state. Such
a step necessarily introduces numerous dislocations in the SiGe
layer to accommodate the lattice spacing and volume increase. The
film also usually "buckles" and roughens significantly during this
relaxation process.
[0009] The major parameters characterizing a practical relaxed SiGe
alloy film include the amount that the film has been relaxed from
its strained state (i.e. 50% relaxation would mean that the film
has relaxed half of its strain), the roughness of the film, and the
dislocation defect density that would be affecting the subsequent
growth of the strained silicon device film.
[0010] The surface dislocation density is a critical parameter
affecting the electrical properties of semiconductor materials
since they are highly dependent upon crystalline defects.
Dislocations can comprise insertion of an extra half-plane of atoms
into a regular crystal structure, displacement of whole rows of
atoms from their regular lattice position, and/or displacement of
one portion of the crystal relative to another portion of the
crystal. Dislocations present on the device layer can tend to
short-circuit p-n junctions and also scatter electrons in a uniform
n-type crystal, impeding their motion and reducing their mobility.
Dislocations also cause highly localized distortion of the crystal
lattice leading to the formation of "trapping" sites where the
recombination of positive (holes) and negative (electrons) carriers
is enhanced. This may cause, for example, the electrons from the
n-p-n transistor emitter to recombine with holes in the p-type base
regions before they can be collected at the n-type collector
region, reducing the transistor current gain. This electron
"lifetime" may be significantly reduced by recombination when as
few as one out of 10.sup.11 atoms/cm3 of silicon are removed from
their normal lattice sites. Although some dislocations can be
removed from a semiconductor material by thermal annealing, many
dislocations are permanent and thermally stable. Many of the
relaxation approaches are therefore tuned to minimize the defect
density of the type that can be translated to the device layer and
cause device performance degradation, failure and yield losses.
[0011] In one method according to the conventional art, the SiGe
alloy is grown with a slowly varying grade from 0% germanium to the
required alloy composition at a sufficiently low temperature to
grow a dislocation free initial film and through subsequent
annealing, the slow gradient helps to accommodate film relaxation
through the generation of dislocations that are buried within the
SiGe layer. This technology is explained in Legoues & al. (U.S.
Pat. No. 5,659,187 "Low defect density/arbitrary lattice constant
heteroepitaxial layers"). To limit the production of dislocations
threading to the surface, the SiGe grade is usually less than 2%
composition increase per 1000 Angstroms of SiGe film growth. This
shallow gradient approach is lower in productivity due to its
relatively thick SiGe layer composition and may require numerous
growth/anneal cycles to achieve roughness and dislocation
goals.
[0012] In yet another method according to the conventional art, the
surface roughness or the SiGe alloy layer can be reduced using a
chemical mechanical polishing (CMP) process such as taught by
Fitzgerald (U.S. Pat. No. 6,291,321 "Controlling threading
dislocation densities in Ge on Si using graded GeSi layers and
planarization" and U.S. Pat. No. 6,107,653, "Controlling threading
dislocation densities in Ge on Si using graded GeSi layers and
planarization"). CMP utilizes a combination of vertical force
between a wafer and an abrasive pad as well as a chemical action of
a slurry, to polish the surface of the wafer to a highly planar
state. The roughness of the resulting semiconductor surface can
typically be reduced to approximately 1 Angstrom RMS when measured
by an Atomic Force Microscope (AFM). However, CMP is relatively
costly as a result of the slurry and the amount of time it takes to
perform the process. Furthermore, the CMP process does not
generally reduce the dislocation density in the wafer. Finally,
this linear growth/anneal/CMP sequence is costly as it requires
numerous sequential process and wafer handling steps.
[0013] Another method uses miscut wafers to help the grown film to
relax as much as possible and accommodate the lattice mismatches.
See for example Fitzgerald & al. (U.S. Pat. No. 6,039,803,
"Utilization of miscut substrates to improve relaxed graded
silicon-germanium and germanium layers on silicon") that teaches
the improvement of using base wafers having 1 to about 8 degrees of
miscut from a true [100] orientation to help grow a less defective,
relaxed layer of a second semiconductor material. Although the base
substrate miscut can improve the relaxed defect density to some
extent, the improvements are generally considered insufficient for
leading edge applications.
[0014] Referring to FIG. 1, a flow diagram of a process according
to the conventional art is shown. This process produces a relaxed
film of SiGe alloy material by first growing a strained film on a
base wafer 110, subjecting the strained film to an anneal step to
relax the film and concurrent generation of surface roughening
(buckling) and dislocations 120, followed by a planarization
smoothing step such as CMP 130. The use of an epitaxial step such
as CVD (Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy)
followed by a planarization step such as CMP significantly
complicates the film relaxation preparation process since multiple
equipment, cleans, and wafer handling are required. This in turn
would increase the manufacturing cost of the relaxed film
fabrication process.
[0015] Referring now to FIGS. 2A-2C, various sectional views of a
semiconductor layer are shown to illustrate the anneal/CMP
conventional art such as disclosed by Fitzgerald in more detail. As
depicted in FIG. 2A, a single crystalline semiconductor surface
formed by an epitaxial process wherein a strained SiGe film 210 is
grown onto a base silicon wafer 220. The semiconductor layer is
comprised of single crystalline silicon-germanium having a surface
roughness 230 of approximately 1-2 Angstrom RMS. The
silicon-germanium layer typically was grown at a sufficiently low
temperature where the film is supercritically stressed but no
relaxation has taken place. The dislocation defect density 240 is
therefore very low, on the order of 1 dislocations/cm.sup.2 or
less.
[0016] As depicted in FIG. 2B, an anneal is performed on the
substrate to relax the SiGe alloy film which generates substantial
surface roughening 250 and dislocation defects 260. The resulting
surface may have a buckled roughening 250 exceeding 200-300
Angstroms RMS and a dislocation defect density 260 exceeding
approximately 10.sup.7 dislocations/cm.sup.2.
[0017] As depicted in FIG. 2C, a separate CMP process generally
reduces surface roughness 270 to approximately 1-5 Angstroms RMS.
However, the CMP process generally does not decrease dislocations
260 in the silicon-germanium layer 310 and must be accompanied by
comprehensive clean processes.
[0018] Thus, the conventional art is disadvantageous in that
planarizing processes are relatively costly and time-consuming
processes. The conventional art also suffers from relatively high
levels of dislocations. A better and less costly approach that can
fully relax strained SiGe alloy films while controlling surface
roughness and dislocation defect levels is highly desirable.
SUMMARY OF THE INVENTION
[0019] A method for etch annealing a semiconductor layer is
disclosed. In addition to its significant effect in controlling the
roughness increases during the relaxation process, the method has
the unexpected benefit of substantially reducing dislocations. The
reduced dislocation density is advantageous in that carrier
mobility and yield are increased.
[0020] In one embodiment, a method of forming a strained
semiconductor layer is provided. The method comprises growing a
strained first semiconductor layer, having a graded dopant profile,
on a wafer, having a first lattice constant. The dopant imparts a
second lattice constant to the first semiconductor layer. The
method further comprises growing a strained boxed second
semiconductor layer having the second lattice constant on the first
semiconductor layer and growing a sacrificial third semiconductor
layer having the first lattice constant on the second semiconductor
layer. The method further comprises etch annealing the third and
second semiconductor layer, wherein the third semiconductor layer
is removed and the second semiconductor layer is relaxed. The
method may further comprises growing a fourth semiconductor layer
having the second lattice constant on the now relaxed second
semiconductor layer, wherein the fourth semiconductor layer is
relaxed, and growing a strained fifth semiconductor layer having
the first semiconductor lattice constant on the fourth
semiconductor layer. The method controls the surface roughness of
the semiconductor layers. The method also has the added benefit of
reducing dislocations in the semiconductor layers.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The present invention is illustrated by way of example and
not by way of limitation, in the figures of the accompanying
drawings and in which like reference numerals refer to similar
elements and in which:
[0022] FIG. 1 shows a flow diagram of a conventional art process
for controlling the surface roughness and dislocations of a
semiconductor material.
[0023] FIG. 2A shows a sectional view of a strained semiconductor
layer having an initial surface roughness, according to the
conventional art.
[0024] FIG. 2B shows a sectional view of a relaxed semiconductor
layer having a substantially higher surface roughness and
dislocation density after an annealing step, according to the
conventional art.
[0025] FIG. 2C shows a sectional view of a semiconductor layer
having a planar surface after a CMP process is performed on the
conventionally annealed surface, according to the convention
art.
[0026] FIG. 3 shows a flow diagram of a process for controlling the
surface roughness and reducing dislocations of a strained
semiconductor layer, in accordance with one embodiment of the
present invention.
[0027] FIGS. 4A-4B show sectional views of a strained semiconductor
structure having reduced surface roughness and reduced
dislocations, in accordance with one embodiment of the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0028] Reference will now be made in detail to the embodiments of
the invention, examples of which are illustrated in the
accompanying drawings. While the invention will be described in
conjunction with the preferred embodiments, it will be understood
that they are not intended to limit the invention to these
embodiments. On the contrary, the invention is intended to cover
alternatives, modifications and equivalents, which may be included
within the spirit and scope of the invention as defined by the
appended claims. Furthermore, in the following detailed description
of the present invention, numerous specific details are set forth
in order to provide a thorough understanding of the present
invention. However, it will be obvious to one of ordinary skill in
the art that the present invention may be practiced without these
specific details. In other instances, well-known methods,
procedures, components, and circuits have not been described in
detail as not to unnecessarily obscure aspects of the present
invention.
[0029] Referring to FIG. 3, a flow diagram of a process for
controlling the surface roughness and reducing dislocations of a
strained semiconductor layer, in accordance with one embodiment of
the present invention, is shown. As depicted in FIG. 3, the process
begins with growing a strained graded first semiconductor layer, on
a wafer, at 310. The wafer comprises a semiconductor having a first
lattice constant. The strained graded first semiconductor layer
comprises a semiconductor having a graded dopant profile, wherein
the dopant imparts a second lattice constant. The first lattice
constant is less than the second lattice constant. The term
"lattice constant" is intended to mean the lattice structure in a
normally relaxed single crystalline state.
[0030] In one implementation, the strained graded first
semiconductor layer comprises a strained SiGe alloy having a graded
doping profile. The stained graded SiGe layer of approximately
4000-20,000 angstroms (.ANG.) is formed by an epitaxial deposition
process. The doping profile of the germanium (Ge) increases from
approximately 0% at the wafer to 25% at the surface of the strained
SiGe layer. In one implementation, the epitaxial deposition process
is performed in a hydrogen-chloride (HCl) ambient. The as-grown
strained graded SiGe layer has a roughness of approximately 2
Angstroms root-mean-square (RMS), and less than approximately 1
dislocations/cm.sup.2.
[0031] At 320, a strained boxed second semiconductor layer is grown
on the strained graded first semiconductor layer. The strained
boxed second semiconductor layer is grown having the second lattice
constant. The term "boxed" is intended to indicate that the doping
profile of the layer is substantially constant. The roughness of
the strained boxed second semiconductor layer is low because the
as-grown semiconductor is close to being or is fully strained and
has not been subjected to thermal cycles that would have started
the relaxation process. In one implementation, the strained boxed
second semiconductor layer comprises a strained SiGe layer having a
constant Ge doping profile. The strained boxed SiGe layer of
approximately 500-5000 .ANG. is formed by an epitaxial deposition
process. The doping profile of the Ge is approximately 25%
throughout the first strained boxed SiGe layer. In one
implementation, the epitaxial process if performed in an HCl
ambient.
[0032] At 330, a sacrificial third semiconductor layer is grown on
the strained boxed second semiconductor layer. The sacrificial
third semiconductor layer is grown having the first lattice
constant. In one implementation, the sacrificial third
semiconductor layer comprises a silicon (Si) layer. The sacrificial
Si layer of approximately 100-300 .ANG. is formed by an epitaxial
deposition process. It is also appreciated that the growth of the
sacrificial third semiconductor layer may be omitted.
[0033] At 340, an etch anneal is performed upon the sacrificial
third semiconductor layer and the boxed second semiconductor layer.
The surface is "etch annealed" utilizing, for example, an epitaxial
chamber subjecting the wafer to a high temperature anneal in an
etching ambient. The etch anneal etches away the sacrificial third
semiconductor layer, formed at 330, and relaxes the boxed strained
second semiconductor layer, formed at 320. The etch anneal may also
relax the graded strained first semiconductor layer, formed at 310.
This etch anneal produces a smoother surface than a simple anneal
performed in a non-etching ambient.
[0034] A similar process has been shown to smooth unstrained films
in a process referred to as an "epi-smoothing" process. The
epi-smoothing process is disclosed in U.S. Pat. No. 6,287,941,
granted Sep. 11, 2001, entitled "Surface Finishing of SOI
Substrates Using an EPI Process," which is incorporated by
reference herein. Since the etching process applied to relaxing
strained films controls the overall roughness rather than smooths
the surface, it will hereinafter called "etch annealing".
[0035] In one implementation, the etch annealing process comprises
subjecting the sacrificial Si layer to an etchant including a
halogen bearing compound such as HCl, HF, HI, HBr, SF.sub.6,
CF.sub.4, NF.sub.3, CCl.sub.2F.sub.2, or the like. The etch
annealing process is performed at an elevated temperature of
700-1200.degree. C., or greater. For example, the surface of the
sacrificial Si layer and the strained boxed SiGe layer is exposed
to a HCl containing gas, at an elevated temperature of
700-1200.degree. C., in an etch annealing process, such that:
SiGe(solid)+4HCl(gas).fwdarw.SiCl.sub.4(gas)+2H.sub.2(gas)+Ge This
process is substantially the reversal of an epitaxial deposition
process for growing a silicon-germanium layer. The difference being
that if the concentration of hydrogen chloride is too high, the
surface is etched instead of silicon-germanium being deposited. The
etch annealing process removes silicon and silicon-germanium
concurrently with the strain relaxation process and has been shown
to help mitigate the undesirable emergence of dislocations and
surface roughening. Thus, the etch annealing process acts to
control surface roughening and lower dislocation density while
achieving substantially complete film relaxation.
[0036] Accordingly, the etchant removes the sacrificial Si layer.
Furthermore, the concurrent use of the etchant and a temperature
sufficient to relax the strained boxed SiGe or the strained boxed
SiGe and strained graded SiGe layers has been found to help reduce
or eliminate the generation of dislocations with a concurrent
reduction in relaxation roughening of the surface. This favorable
effect is believed linked to a reduction of the stress inducing
cycloidic cusp tips present during a non-etch anneal (H. Gao &
W. D. Nix, "Surface Roughening of Heteroepitaxial Thin Films",
Annu. Rev. Mater. Sci. 1999, 29, pg. 173-209). In the work by Gao
and Nix, it is explained that the strain caused by the lattice
mismatch drives the generation of an undulating profile on the
surface that has periodic sharp cusp tips that favor the creation
of dislocations at these highly stressed locations. The concurrent
etching process during lattice relaxation is believed to
significantly blunt or round the cusp tips that reduce the stress
concentration and thus reduces the surface dislocation density by
affecting its creation kinetics. The surface roughening is also
disfavored by the etch ambient.
[0037] The etch annealing process may be performed at a range of
elevated temperatures that would favor the concentration of the
dislocations away from the surface to relax the lattice structure
of the boxed SiGe layer. The thermal treatment may be from a
resistance heater, RF heater, high intensity lamps, or the like.
The thermal treatment means should be capable of heating the
semiconductor material at a rate of approximately 10-20.degree.
C./sec, or more.
[0038] Because the strained graded SiGe layer, strained boxed SiGe
layer, and the sacrificial Si layer are performed within an
epitaxial reactor and the etch annealing is also performed within
the same system, repetition of these steps is straightforward and
the general economy of the process can be fully appreciated since
no cleans, external anneals or CMP planarization steps are
needed.
[0039] The etch annealing process removes strained semiconductor
material in a manner that blunts sharpening (roughening) features
that form on the surface upon film relaxation. The rate of etching
is a function of time, temperature, and the etchant type and
concentration. Therefore, controlling these parameters during the
etch annealing process controls the amount of etching. The etch
annealing process is performed until the process reduces surface
roughness by approximately fifty percent or more compared to an
anneal without the etchant. Thus, the etch annealing process acts
to control surface roughening during film relaxation sufficient for
subsequent semiconductor device fabrication processes. The method
also provides the added benefit of reducing dislocations by up to
two orders of magnitudes or more.
[0040] Furthermore, unlike convention CMP processes that are
limited to removing a few tens of nano-meters or less, the etch
annealing process can be used to remove as much as a few hundreds
of nano-meters or more of semiconductor material.
[0041] It is also appreciated that the etch anneal may be performed
partway through the growth of the strain graded first semiconductor
layer formed at 310. Furthermore, the etch anneal may be performed
more than once at during various processes, such as 310, 320 and/or
330.
[0042] At 350, a boxed fourth semiconductor layer is grown on the
relaxed boxed second semiconductor layer. The boxed fourth
semiconductor layer is grown having the second lattice constant and
has a relaxed structure. In one implementation, the boxed fourth
semiconductor layer comprises a relaxed SiGe layer having a
constant Ge doping profile. The boxed SiGe layer of approximately
1000-10,000 .ANG. is formed by an epitaxial deposition process. The
doping profile of the Ge is approximately 25% throughout the boxed
SiGe layer. In one implementation, the epitixial process if
performed in an HCl ambient.
[0043] At 360, a fifth semiconductor layer is grown on the boxed
fourth semiconductor layer. The fifth semiconductor layer is grown
having the first lattice constant. Accordingly, the fifth
semiconductor layer is formed as a strained semiconductor layer. In
one implementation, the fifth semiconductor layer comprises a
silicon (Si) layer. The second Si layer of approximately 100-200
.ANG. is formed by an epitaxial deposition process.
[0044] The fifth semiconductor layer may be utilized for
fabricating additional layers thereupon or device regions therein.
The reduced dislocation density of the resulting strained fifth
semiconductor layer advantageously results in higher carrier
mobility. The higher carrier mobility improves characteristics of
devices, such as field effect transistors, bipolar transistors, and
the like.
[0045] Referring now to FIGS. 4A-4B, sectional views of a strained
semiconductor structure having reduced surface roughness and
reduced dislocations, in accordance with one embodiment of the
present invention, is shown. As depicted in FIG. 4A, an
intermediate semiconductor structure comprises a wafer 410. A
strained graded first semiconductor layer 420 is formed upon the
wafer 410. A strained boxed second semiconductor layer 430 is
formed upon the strained graded first semiconductor layer 420. A
sacrificial third semiconductor layer 440 is formed upon the
strained boxed second semiconductor layer 430.
[0046] As depicted in FIG. 4B, the strained semiconductor structure
after an etch anneal process is shown. The graded first
semiconductor layer 420 and the boxed second semiconductor layer
have been relaxed by the etch anneal process. The sacrificial third
semiconductor layer 440 has been removed. A boxed fourth
semiconductor layer 450 is formed upon the relaxed boxed second
semiconductor layer 430 and is relaxed. A fifth semiconductor layer
460 is formed upon the relaxed boxed fourth semiconductor layer
450. The fifth semiconductor layer 460 has a first lattice
constant, and the relaxed boxed fourth semiconductor layer 450 has
a second lattice constant. Therefore, the fifth semiconductor layer
460 comprises a strained semiconductor layer.
[0047] The etch annealing process yields a less costly alternative
than the conventional art by allowing for a usable strained silicon
device layer without costly external planarization steps.
Furthermore, one skilled in the art would expect that etch
annealing would not affect the generation of the dislocation
process. However, the etch annealing process results in the
unexpected benefit of decreasing the dislocation density to
approximately 10.sup.5 dislocations/cm.sup.2, as compared to an
anneal made without an etch ambient of approximately 10.sup.7
dislocations/cm.sup.2. The etch annealing process is also highly
effective in fully relaxing the film, rendering it suitable as a
base to grow a strained silicon device film.
[0048] The resulting strained fifth semiconductor layer 460 can be
utilized for fabricating semiconductor layers thereupon or device
regions therein. The reduced dislocation nature of the
semiconductor layer advantageously results in higher carrier
mobility. The high carrier mobility in the fifth semiconductor
layer 460 improves characteristics of the devices formed
therein.
[0049] The foregoing descriptions of specific embodiments of the
present invention have been presented for purposes of illustration
and description. They are not intended to be exhaustive or to limit
the invention to the precise forms disclosed, and obviously many
modifications and variations are possible in light of the above
teaching. The embodiments were chosen and described in order to
best explain the principles of the invention and its practical
application, to thereby enable others skilled in the art to best
utilize the invention and various embodiments with various
modifications as are suited to the particular use contemplated. It
is intended that the scope of the invention be defined by the
Claims appended hereto and their equivalents.
* * * * *