U.S. patent application number 11/591750 was filed with the patent office on 2007-03-01 for method for fabricating semiconductor component having conductors and bonding pads with wire bondable surfaces and selected thickness.
Invention is credited to Warren M. Farnworth.
Application Number | 20070048999 11/591750 |
Document ID | / |
Family ID | 32392187 |
Filed Date | 2007-03-01 |
United States Patent
Application |
20070048999 |
Kind Code |
A1 |
Farnworth; Warren M. |
March 1, 2007 |
Method for fabricating semiconductor component having conductors
and bonding pads with wire bondable surfaces and selected
thickness
Abstract
A method for fabricating a semiconductor component includes the
step of providing a semiconductor die having a die contact and at
least one integrated circuit in electrical communication with the
die contact. The method also includes the steps of forming a first
polymer layer on the die, forming a conductor on the polymer layer
in electrical communication with the die contact, and forming a
wire bonding pad on the conductor. The method also includes the
steps of forming a metal layer on the wire bonding pad configured
to form the wire bonding pad with a selected thickness, forming a
non-oxidizing metal layer on the metal layer, and then wire bonding
a wire to the wire bonding pad.
Inventors: |
Farnworth; Warren M.;
(Nampa, ID) |
Correspondence
Address: |
STEPHEN A GRATTON;THE LAW OFFICE OF STEVE GRATTON
2764 SOUTH BRAUN WAY
LAKEWOOD
CO
80228
US
|
Family ID: |
32392187 |
Appl. No.: |
11/591750 |
Filed: |
November 2, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10924010 |
Aug 23, 2004 |
7132750 |
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11591750 |
Nov 2, 2006 |
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10183705 |
Jun 25, 2002 |
6784544 |
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10924010 |
Aug 23, 2004 |
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Current U.S.
Class: |
438/612 ;
257/E21.508; 257/E23.02; 257/E23.021; 257/E23.039; 438/617 |
Current CPC
Class: |
H01L 24/85 20130101;
H01L 2924/00014 20130101; H01L 2924/1433 20130101; H01L 2224/05644
20130101; H01L 2224/05666 20130101; H01L 2224/85399 20130101; H01L
2225/0651 20130101; H01L 2924/01033 20130101; H01L 2924/01082
20130101; H01L 24/05 20130101; H01L 2224/1308 20130101; H01L
2924/01042 20130101; H01L 2224/1308 20130101; H01L 2924/00013
20130101; H01L 2224/05644 20130101; H01L 2224/13144 20130101; H01L
2224/45099 20130101; H01L 2924/01073 20130101; H01L 24/13 20130101;
H01L 2224/05611 20130101; H01L 2224/05655 20130101; H01L 2224/13144
20130101; H01L 2924/01022 20130101; H01L 2224/05647 20130101; H01L
24/11 20130101; H01L 2225/06572 20130101; H01L 2924/01028 20130101;
H01L 2224/05611 20130101; H01L 2224/04042 20130101; H01L 2224/13
20130101; H01L 2924/01019 20130101; H01L 2924/01023 20130101; H01L
2224/13124 20130101; H01L 2924/01029 20130101; H01L 2224/1308
20130101; H01L 2924/01043 20130101; H01L 2224/05083 20130101; H01L
2224/48477 20130101; H01L 2924/01047 20130101; H01L 2224/32245
20130101; H01L 2224/05624 20130101; H01L 2924/01079 20130101; H01L
2224/05647 20130101; H01L 2224/1134 20130101; H01L 2224/1308
20130101; H01L 2924/00014 20130101; H01L 2924/01006 20130101; H01L
2924/01013 20130101; H01L 2224/13147 20130101; H01L 2924/14
20130101; H01L 2924/181 20130101; H01L 2224/05655 20130101; H01L
24/48 20130101; H01L 2224/13 20130101; H01L 2924/01046 20130101;
H01L 2924/181 20130101; H01L 2224/05082 20130101; H01L 2224/48247
20130101; H01L 2924/01024 20130101; H01L 2224/85051 20130101; H01L
2224/0401 20130101; H01L 2924/00014 20130101; H01L 2924/01065
20130101; H01L 2924/30105 20130101; H01L 2224/13147 20130101; H01L
2224/73215 20130101; H01L 2224/05639 20130101; H01L 2224/73215
20130101; H01L 24/03 20130101; H01L 2224/114 20130101; H01L
2224/116 20130101; H01L 2224/13082 20130101; H01L 2224/13124
20130101; H01L 2224/85399 20130101; H01L 2924/0103 20130101; H01L
23/49827 20130101; H01L 23/147 20130101; H01L 2224/05639 20130101;
H01L 2924/00013 20130101; H01L 24/06 20130101; H01L 23/3114
20130101; H01L 2224/11 20130101; H01L 2224/05082 20130101; H01L
2224/16 20130101; H01L 2924/01039 20130101; H01L 2224/05624
20130101; H01L 23/4951 20130101; H01L 2224/05671 20130101; H01L
2224/11 20130101; H01L 2924/01078 20130101; H01L 2924/01005
20130101; H01L 2924/01074 20130101; H01L 2224/48227 20130101; H01L
2924/00014 20130101; H01L 2224/45015 20130101; H01L 2924/00014
20130101; H01L 2924/00012 20130101; H01L 2924/207 20130101; H01L
2924/00014 20130101; H01L 2924/00014 20130101; H01L 2224/45099
20130101; H01L 2224/4826 20130101; H01L 2224/05681 20130101; H01L
2924/00014 20130101; H01L 2924/00 20130101; H01L 2224/4826
20130101; H01L 2224/32245 20130101; H01L 2924/00014 20130101; H01L
2924/00014 20130101; H01L 2224/05155 20130101; H01L 2924/00014
20130101; H01L 2224/13099 20130101; H01L 2924/00014 20130101; H01L
2924/00 20130101; H01L 2924/00014 20130101; H01L 2224/13144
20130101; H01L 2224/13124 20130101; H01L 2224/05144 20130101; H01L
2224/13147 20130101; H01L 2224/05647 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
438/612 ;
438/617 |
International
Class: |
H01L 21/44 20060101
H01L021/44 |
Claims
1. A method for fabricating a semiconductor component comprising:
providing a semiconductor die comprising a die contact and at least
one integrated circuit in electrical communication with the die
contact; forming a first polymer layer on the die; forming a
conductor on the polymer layer in electrical communication with the
die contact; forming a wire bonding pad on the conductor; forming a
metal layer on the wire bonding pad configured to form the wire
bonding pad with a selected thickness; forming a non-oxidizing
metal layer on the first metal layer; and wire bonding a wire to
the wire bonding pad.
2. The method of claim 1 further comprising forming a second
polymer layer on the conductor and the wire bonding pad having an
opening aligned with the wire bonding pad.
3. The method of claim 1 wherein the forming the metal layer step
and the forming the non-oxidizing metal layer step comprise
electroless deposition.
4. The method of claim 1 wherein the forming the metal layer step
forms the conductor with the selected thickness.
5. A method for fabricating a semiconductor component comprising:
providing a semiconductor die including a circuit side, a plurality
of integrated circuits, and at least one die contact on the circuit
side in electrical communication with at least one integrated
circuit; forming a first polymer layer on the circuit side; forming
a conductor on the first polymer layer in electrical communication
with the die contact having a wire bonding pad; forming a metal
layer on the wire bonding pad configured to adjust a thickness of
the wire bonding pad; forming a non-oxidizing layer on the metal
layer to provide a wire bondable surface; and wire bonding to the
wire bonding pad.
6. The method of claim 5 further comprising forming a second
polymer layer on the conductor and the wire bonding pad having an
opening aligned with the wire bonding pad.
7. The method of claim 5 wherein the thickness of the wire bonding
pad is selected to achieve an electrical characteristic for the
wire bonding pad.
8. The method of claim 5 further comprising forming the metal layer
on the conductor.
9. The method of claim 8 wherein the thickness of the metal layer
is selected to achieve a second electrical characteristic for the
conductor.
10. The method of claim 5 wherein the non-oxidizing layers comprise
a metal selected from the group consisting of Au, Pt and Pd.
11. The method of claim 5 wherein the metal layer comprises a metal
selected from the group consisting of Ni, V, Cr, CrCu and Cu.
12. The method of claim 5 wherein the forming the metal layer step
comprises electroless deposition.
13. The method of claim 5 wherein the forming the conductor step
comprises forming a seed layer and then electrolessly depositing a
second metal layer on the seed layer.
14. A method for fabricating a semiconductor component comprising:
providing a semiconductor die including a circuit side, a plurality
of integrated circuits, and at least one die contact on the circuit
side in electrical communication with at least one integrated
circuit; forming a first polymer layer on the circuit side; forming
a conductor on the first polymer layer in electrical communication
with the die contact having a wire bonding pad; forming a metal
layer on the conductor and on the wire bonding pad configured to
adjust a thickness and an electrical characteristic of the
conductor and the wire bonding pad; forming a second polymer layer
on the conductor and the wire bonding pad having an opening aligned
with the wire bonding pad forming a non-oxidizing layer on the
metal layer to provide a wire bondable surface; and wire bonding to
the wire bonding pad.
15. The method of claim 14 wherein the first polymer layer and the
second polymer layer comprise a low k material.
16. The method of claim 14 wherein the non-oxidizing layer seals
edges of the wire bonding pad.
17. The method of claim 14 wherein the non-oxidizing layer seals
edges of the conductor.
18. The method of claim 14 further comprising forming a metal bump
on the die contact, and the forming the conductor step forms the
conductor in electrical communication with the bump.
19. The method of claim 14 wherein the metal layer comprises
electrolessly deposited nickel.
20. The method of claim 14 wherein the non-oxidizing layer
comprises an electrolessly deposited noble metal.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of Ser. No. 10/924,010,
filed Nov. 07, 2006, U.S. Pat. No. 7,132,750, which is a
continuation of Ser. No. 10/183,705, filed Jun. 25, 2002, U.S. Pat.
No. 6,784,544.
[0002] This application is related to Ser. No. 10/617,936, filed
Jul. 10, 2003, U.S. Pat. No. 6,887,787.
FIELD OF THE INVENTION
[0003] This invention relates generally to semiconductor
manufacture and packaging. More particularly, this invention
relates to improved semiconductor components having conductors with
wire bondable metallization layers, to methods for fabricating the
components, and to electronic assemblies incorporating the
components.
BACKGROUND OF THE INVENTION
[0004] Redistribution circuits are widely used in fabricating
semiconductor components such as packages, dice, wafers,
interconnects and interposers. Typically, redistribution circuits
are used to provide specific electrical paths on a semiconductor
component. For example, a semiconductor package can include a
single die having bond pads in electrical communication with the
integrated circuits contained on the die. Redistribution circuits
can be formed on the circuit side of the die to provide electrical
paths between the bond pads and terminal contacts for the
package.
[0005] A typical redistribution circuit includes an insulating
polymer layer on the die, and a pattern of redistribution
conductors on the insulating layer. Typically, the insulating layer
comprises a low dielectric constant polymer material, such as
polyimide, benzocyclobutene (BCB) or polybenzoxazole (PBO). The
redistribution conductors typically comprise a highly conductive
metal such as Al or Cu.
[0006] One problem occurs if the redistribution conductors must be
wire bonded to contacts on a mating component such as another
package, a module substrate or a printed circuit board. Although
the redistribution conductors can comprise a wire bondable metal,
it is difficult to form reliable wire bonds to the redistribution
conductors. In general, wire bonds are affected by the power,
duration and force used to form the wire bonds. If insufficient
power, duration or force is used, the wire bonds do not bond to the
redistribution conductors (i.e., "no stick"). The inventor has
theorized that this may be due to the resiliency and energy
dissipating characteristics of the underlying polymer insulating
layer. However, if too much power, duration or force is used to
compensate for the affects of the polymer layer, the redistribution
conductors and the polymer layer can be damaged (i.e.,
"cratering"). The process window for wire bonding to the
redistribution conductors is thus very small or non-existent.
[0007] The present invention is directed to improved components
having redistribution conductors with a wire bondable layer formed
thereon. This invention also relates to methods for fabricating the
components, and to systems incorporating the components.
SUMMARY OF THE INVENTION
[0008] In accordance with the present invention, an improved
semiconductor component, a wafer level method for fabricating the
component, and electronic assemblies incorporating the component,
are provided.
[0009] The component includes a semiconductor die having die
contacts, such as bond pads, in electrical communication with
integrated circuits thereon. The component also includes a low k
polymer layer on the circuit side of the die, and a pattern of
conductors and bonding pads on the polymer layer in electrical
communication with the die contacts. The conductors are configured
to redistribute or fan out the die contacts to the pattern of the
bonding pads. The conductors and the bonding pads comprise metal
stacks including conductive layers, barrier/adhesion layers, and
non-oxidizing layers. The barrier/adhesion layers and the
non-oxidizing layers protect the conductors and the bonding pads,
and allow wire bonding to the component without damage to the
conductors or the bonding pads. In addition, the bonding pads can
optionally include terminal contacts such as stud bumps configured
for flip chip bonding, or alternately double bump wire bonding to
the component.
[0010] The component can be used to fabricate any electronic
assembly that requires wire bonding to a mating substrate such as a
module substrate, a package substrate or a printed circuit
board.
[0011] The method for fabricating the component includes the step
of providing multiple dice on a common substrate such as a
semiconductor wafer. The method also includes the steps of forming
the polymer layer on the substrate, forming the conductors and the
bonding pads on the polymer layer, and forming the barrier/adhesion
layers and the non-oxidizing layers on the conductors and bonding
pads. In the illustrative embodiment the conductors, the
barrier/adhesion layers and the non-oxidizing layers are formed
using electroless deposition. The method also includes a
singulating step in which the components are singulated from the
substrate.
[0012] An alternate embodiment component comprises an interposer
configured to electrically connect semiconductor components to one
another, or to supporting substrates.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIGS. 1A-1G are schematic cross sectional views illustrating
steps in a method for fabricating a semiconductor component in
accordance with the invention;
[0014] FIG. 1H is an enlarged view taken along line 1H of FIG.
1E;
[0015] FIG. 1I is an enlarged view taken along line 1I of FIG.
1F;
[0016] FIG. 1J is an enlarged view taken along line 1J of FIG. 1G
illustrating the component;
[0017] FIG. 2A is a cross sectional view taken along section line
2A-2A of FIG. 1A illustrating a wafer level substrate for
fabricating multiple components;
[0018] FIG. 2B is a cross sectional view taken along section line
2B-2B of FIG. 1B illustrating a polymer layer on the
components;
[0019] FIG. 2C is a cross sectional view taken along section line
2C-2C of FIG. 1C illustrating conductors on the components;
[0020] FIG. 2D is a cross sectional view taken along section line
2D-2D of FIG. 1D illustrating barrier layers on the conductors;
[0021] FIG. 2E is a cross sectional view taken along section line
2E-2E of FIG. 1E illustrating wire bonding layers on the
conductors;
[0022] FIG. 2F is a cross sectional view taken along section line
2F-2F of FIG. 2F illustrating an outer polymer layer on the
components;
[0023] FIG. 2G is an enlarged cross sectional view taken along
section line 2G-2G of FIG. 2A illustrating a component contact and
a metal bump on the component contact;
[0024] FIG. 3A is a schematic plan view of a module assembly that
includes components fabricated in accordance with the
invention;
[0025] FIG. 3B is a cross sectional view taken along section line
3B-3B of FIG. 3A illustrating wire bonds on the module
assembly;
[0026] FIG. 4A is a schematic cross sectional view of a package
assembly that includes a component fabricated in accordance with
the invention;
[0027] FIG. 4B is a cross sectional view taken along section line
4B-4B of FIG. 4A illustrating wire bonds on the package
assembly;
[0028] FIG. 5A is a plan view of an alternate embodiment component
having terminal contacts;
[0029] FIG. 5B is a side elevation view of the alternate embodiment
component;
[0030] FIG. 5C is an enlarged view of a terminal contact on the
alternate embodiment component;
[0031] FIG. 6A is a schematic side elevation view of a stacked
assembly that includes an alternate embodiment interposer component
constructed in accordance with the invention; and
[0032] FIG. 6B is a plan view taken along line 6B-6B of FIG.
6A.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0033] As used herein, the term "semiconductor component" refers to
an electronic element that includes a semiconductor die. Exemplary
semiconductor components include bare dice, such as bumped die and
flip chip devices. Other exemplary semiconductor components include
semiconductor packages, such as chip scale packages, BGA devices,
BOC packages, COB packages, stacked packages and lead on chip (LOC)
packages. Semiconductor component also refers to an electronic
element, such as an interposer, configured to make electrical
connections with a semiconductor die or a semiconductor
package.
[0034] Referring to FIGS. 1A-1G, steps in the method for
fabricating a semiconductor component 10 (FIG. 1G) in accordance
with the invention are illustrated.
[0035] Initially, as shown in FIGS. 1A and 2A, a plurality of
semiconductor dice 12 are provided on a semiconductor substrate 14.
The dice 12 can comprise conventional semiconductor dice having a
desired configuration, and the substrate 14 can comprise a
semiconductor wafer or portion thereof. For example, each die 12
can comprise a dynamic random access memory (DRAM), a static random
access memory (SRAM), a flash memory, a microprocessor, a digital
signal processor (DSP) or an application specific integrated
circuit (ASIC).
[0036] Each die 12 includes a circuit side 16 and a back side 18.
Each die 12 also includes a pattern of die contacts 20 formed on
the circuit side 16 thereof. In the illustrative embodiment, the
die contacts 20 are the bond pads for the die 12. The die contacts
20 can be formed in any conventional pattern such as a center
pattern, an edge pattern or a grid pattern. In addition, the die
contacts 20 can comprise a conventional metal such as Al, Au, Cu,
Ni or alloys of these metals.
[0037] As shown in FIG. 2G, the die contacts 20 are embedded in a
die insulating layer 24, and are in electrical communication with
integrated circuits 26 contained on the die 12. For simplicity, the
die insulating layer 24 and the integrated circuits 26 are not
shown in FIGS. 1A-1G. The die insulating layer 24 can comprise any
electrically insulating material including glasses such as BPSG,
polymers such as polyimide and resist, and oxides such as
SiO.sub.2. In addition, the die insulating layer 24 includes
openings 28 aligned with the die contacts 20.
[0038] As also shown in FIGS. 1A and 2A, metal bumps 22 are formed
on the die contacts 20. The metal bumps 22 can be formed on the die
contacts 20 using a deposition process, such as electroless or
electrolytic deposition. For example, the metal bumps 22 can
comprise Ni deposited on the die contacts 20 using an electroless
deposition process. With an electroless process the substrate 14
can be dipped in a zincate activation solution, such as ZnO.sub.2
or Zn(OH.sub.4) to activate the surface of the die contacts 20.
Following activation, the substrate 14 can be dipped in a nickel
solution such as NiCl.sub.2, at a temperature of about 85 to
90.degree. C., for a time period sufficient to form the metal bumps
22. Zincate and nickel solutions are commercially available from
Lea Ronal of Freeport, N.Y. One suitable nickel solution is
commercially available under the trademark "PALLAMERSE Ni".
[0039] As shown in FIG. 2G, a diameter D of the metal bumps 22 is
about equal to the width of the die contacts 20, with a range of
from about 25 .mu.m to 100 .mu.m being representative. In addition,
a height H of the metal bumps 22 can be selected as required, with
from about 20 .mu.m to 125 .mu.m being representative.
[0040] Referring to FIGS. 1B and 2B, following forming of the metal
bumps 22, a first polymer layer 30 is blanket deposited on the
substrate 14. The first polymer layer 30 and the metal bumps 22 are
then planarized such that the first polymer layer 30 and the metal
bumps 22 have a same planar surface. The polymer layer 30
preferably comprises a low dielectric constant (low k) polymer such
as polyimide, polybenzoxazole (PBO), or benzocyclobutene (BCB). As
used herein, the term "low k" refers to a material with a
dielectric constant of less than about 3.9.
[0041] In addition, the polymer layer 30 can be initially blanket
deposited to a desired thickness using a suitable deposition
process such as spin on, positive displacement through a nozzle,
screen printing and stenciling. Systems are commercially available
for performing each of these processes in the context of
semiconductor packaging. For example, material dispensing systems
are manufactured by Asymtek of Carlsbad, Calif., and by Camalot of
Cookson, UK.
[0042] Following deposition, the polymer layer 30 can be cured.
Depending on the polymer, curing can be performed by placing the
substrate 14 in an oven at a required temperature (e.g., 90.degree.
to 165.degree. C.) for a required time (e.g., 30 to 60 minutes).
Following curing of the polymer layer 30, the polymer layer 30 and
the bumps 22 can be planarized to a same planar surface. Following
planarization, a representative thickness T of the polymer layer 30
and height H of the metal bumps 22 can be from 20 .mu.m to 100
.mu.m.
[0043] The planarization step can be performed using a mechanical
planarization apparatus, such as a grinder. One suitable mechanical
planarization apparatus is manufactured by Okamoto, and is
designated a model no. VG502. The planarization step can also be
performed using a chemical mechanical planarization (CMP)
apparatus. A suitable CMP apparatus is commercially available from
a manufacturer such as Westech, SEZ, Plasma Polishing Systems, or
TRUSI. The planarization step can also be performed using an etch
back process, such as a wet etch process, a dry etch process or a
plasma etching process.
[0044] In addition to providing an end point for the polymer layer
30, the metal bumps 22 protect the die contacts 20 from corrosion,
increase the surface areas of the die contacts 20, and improve the
reliability of subsequent electrical connections with the die
contacts 20. As another alternative, the metal bumps 22 can be
omitted and the polymer layer 30 can comprise a photoimageable
material, such as a low k resist. In this case, exposure and
development of the polymer layer 30 forms openings aligned with the
die contacts 20. In addition, a planarization step is not
required.
[0045] Next, as shown in FIGS. 1C and 2C, conductors 32 are formed
on the first polymer layer 30 in electrical communication with the
metal bumps 22 and the die contacts 20. As shown in FIG. 2C, the
conductors 32 redistribute or "fan out" the pattern of the die
contacts 20 from the centers to the edges of the dice 12 (i.e.,
redistributed from a first pattern to a second pattern). In
addition, the conductors 32 include wire bonding pads 34, which in
the illustrative embodiment are enlarged, generally planar segments
with hemispherical edges located at the terminal ends of the
conductors 32. The conductors 32 can be laid out such that the wire
bonding pads 34 are configured in a desired pattern, such as a
dense area array (e.g., grid array). As such, the wire bonding pads
34 have a pattern that is different that the pattern of the die
contacts 20. In addition, the conductors 32 have a width W (FIG.
2C), a length L (FIG. 2C) and a thickness T (FIG. 1C). As will be
further explained, these dimensions can be adjusted to achieve
required electrical characteristics such as capacitance and
resistivity.
[0046] The conductors 32 and the bonding pads 34 preferably
comprise a highly conductive metal layer such as copper (Cu). In
addition, the conductors 32 and the bonding pads 34 can be formed
using the same process and materials, or alternately can be formed
separately. For example, copper can be electrolessly plated on the
polymer layer 30 in a required pattern and with desired dimensions
using techniques that are known in the art. To perform the
electroless plating, the polymer layer 30 can be initially cleaned
and the substrate 14 dipped in an aqueous bath containing a
catalyst configured to form a copper seed layer. Catalyst systems
are commercially available from Lea Ronal of Freeport, N.Y. under
the trademark "UMT CATALYST SYSTEM".
[0047] Following formation of the copper seed layer, a resist layer
can be formed on the copper seed layer, and patterned to define the
conductors 32 in electrical contact with the metal bumps 22 and the
bonding pads 34 in the required pattern. Suitable resists, such as
electro deposited resists, are available from Shipley Corporation
of Newton, Mass. Next, the substrate 14 can be dipped in an
electroless or an electrolytic copper plating solution, such that
copper is applied to areas of the seed layer not covered by the
resist. One suitable plating solution can include "RONADEP"
manufactured by Lea Ronal and DI water. The copper can be
electrolessly plated to form the conductors 32 and the bonding pads
34 with a thickness of from about 1 .mu.m to 4 .mu.m.
[0048] Following electroless copper plating, the resist can be
stripped by plasma etching or other suitable process. In addition,
the exposed copper seed layer can be removed by etching, such that
just the conductors 32 and the bonding pads 34 remain in the
required pattern.
[0049] The outlined process for forming the conductors 32 and the
bonding pads 34 by electroless plating is merely exemplary, and
other processes known in the art can be employed to form the
conductors 32 and the bonding pads 34 of copper or other metals,
such as Al, Cr, Ti, Ni, W, Au, Ag, Ta, Mb. Other suitable
deposition processes include CVD, PECVD, PVD, sputtering and
evaporation.
[0050] Referring to FIG. 1D, following formation of the conductors
32, a barrier/adhesion layer 36 can be formed on the conductors 32
and on the bonding pads 34. The barrier/adhesion layer 36 functions
to provide a diffusion barrier for the conductors 32 and the
bonding pads 34. The barrier/adhesion layer 36 also provides
adhesion to the conductors 32 and the bonding pads 34 for a
subsequently deposited non-oxidizing layer 38 (FIG. 1E). In
addition, the barrier/adhesion layer 36 allows a thickness of the
conductors 32 and the bonding pads 34 to be adjusted to achieve
desired electrical characteristics. For example, the resistivity of
the conductors 32 is a function of the width (W), the thickness
(Tc), the length (L) and the material of the conductors 32. The
thickness Tb of the barrier/adhesion layer 36 adds to the overall
thickness of the conductors 32 such that the width (W) or the
overall thickness can be varied to achieve a desired resistivity.
Similarly, capacitance C is a function of the area of the
conductors 32 and their distance d from other electrical elements.
The distance d can be dependent on the thickness Tb of the barrier
layer 36 such that the capacitance C can be adjusted.
[0051] In the illustrative embodiment, the barrier/adhesion layer
36 comprises electrolessly deposited nickel. Other suitable metals
for the barrier/adhesion layer 36 include V, Cr, CrCu and Cu. A
representative thickness for the barrier/adhesion layer 36 can be
from 100 .ANG. to 5 .mu.m. The barrier/adhesion layer 36 can be
electrolessly or electrolytically deposited on the conductors 32 by
dipping the substrate 14 in an zincate activation solution, and
then in a nickel containing solution substantially as previously
described for bumps 22. Alternately the barrier/adhesion layer 36
can be formed by blanket deposition such as sputtering, followed by
etching to define the pattern.
[0052] Referring to FIGS. 1E and 2E, following deposition of the
barrier/adhesion layer 36, a non-oxidizing layer 38 can be
deposited on the barrier/adhesion layer 36. The non-oxidizing layer
38 preferably comprises a noble metal such as gold (Au), platinum
(Pt) or palladium (Pd).
[0053] In the illustrative embodiment the non-oxidizing layer 38
completely covers the conductors 32 and the bonding pads 34.
Alternately, the non-oxidizing layer 38 can cover just the bonding
pads 34. The non-oxidizing layer 38 seals and protects the
conductors 32 and the bonding pads 34 from corrosion and oxidation.
In addition, the non-oxidizing layer provides a wire bondable
surface for wire bonding to the bonding pads 34. The non-oxidizing
layer 38 can be deposited on the barrier/adhesion layer 36 using an
electroless deposition process. For example, gold can be
electrolessly deposited using a gold containing solution, such as
gold potassium cyanide KAu(CN). A representative thickness Tn of
the non-oxidizing layer 38 can be from 0.5 .mu.m to 1.5 .mu.m.
[0054] As shown in FIG. 1H, each bonding pad 34 comprises a metal
stack which includes a portion of a conductor 32 (i.e., a
conductive layer), a portion of a barrier/adhesion layer 36, and a
portion of a non-oxidizing layer 38. The metal stack can comprise
three different metals (Cu/Ni/Au) or alternately two different
metals (Cu/Cu/Ag). For simplicity, the metal stack is shown in
FIGS. 1E-1G as having sharp continuous edges. However, with an
electroless deposition process the barrier/adhesion layer 36 will
coat the edges of the conductors 32, and the non-oxidizing layer 38
will coat the edges of the barrier/adhesion layer 36. Accordingly,
the edges of the barrier/adhesion layer 36 and the edges of the
non-oxidizing layer 38 will be rounded substantially as shown in
FIGS. 1H and 1I. In addition, the bonding pads 34 will be
completely sealed and protected from oxidation by the non-oxidizing
layer 38.
[0055] Referring to FIGS. 1F and 2F, a second polymer layer 40 can
be optionally deposited on the conductors 32 while leaving the
bonding pads 34 exposed. For example, the second polymer layer 40
can comprise a low k photoimageable polymer deposited to a desired
thickness, then patterned and developed to form openings 42 (FIG.
1I) aligned with the bonding pads 34.
[0056] Referring to FIG. 1G, a singulating step is performed to
separate the individual components 10 from the substrate 14. The
singulating step can be performed by attaching the substrate 14 to
a dicing tape 44 and then sawing grooves 46 through the substrate
14. Alternately, the singulating step can be performed by shearing,
etching or liquid jet cutting the substrate 14. Either prior or
subsequent to the singulating step additional processes can be
performed, such as encapsulating one or more surfaces of the
component 10.
[0057] As shown in FIG. 1J, a singulated component 10 includes a
semiconductor die 12 having die contacts 20 in electrical
communication with the integrated circuits 26 (FIG. 2G) thereon.
The component 10 also includes metal bumps 22 on the die contacts
20 and a first polymer layer 30 on the die 12. The component 10
also includes a pattern of conductors 32 on the first polymer layer
30 in electrical communication with the metal bumps 22. The
conductors 32 redistribute or fan out the electrical paths to the
die contacts 20. The component 10 also includes bonding pads 34
with barrier/adhesion layers 36 and non-oxidizing layers 38. As
will be further explained, the bonding pads 34 facilitate wire
bonding to the component 10. The component 10 can also include a
second polymer layer 40 on the non-oxidizing layers 38 having
openings 42 aligned with the bonding pads 34.
[0058] Referring to FIGS. 3A and 3B, an electronic assembly 48
constructed using multiple components 10 is illustrated. The
electronic assembly can comprise a multi chip module, a printed
circuit board, a second level package or a similar assembly
configured to perform a desired electrical function. The electronic
assembly 48 includes a supporting substrate 50 having a pattern of
electrodes 52 thereon. The electrodes electrically connect the
components 10 to one another or to other electrical elements (not
shown) of the assembly 48 or the outside world. The supporting
substrate 50 can comprise a module substrate, a package substrate,
a printed circuit board or other electronic element configured to
support and electrically engage the components 10. The components
10 are back bonded to the supporting substrate 50 and wires 56 are
bonded to the bonding pads 34 on the components 10 and to the
electrodes 52 on the supporting substrate 50. In addition, wire
bonds 54 are formed between the wires 56 and the bonding pads 34.
These wire bonds 54 have increased reliability due to the multiple
metal layer construction of the bonding pads 34. In addition, a
process window for making the wire bonds 54 is increased and damage
to the conductors 32 is decreased.
[0059] Referring to FIGS. 4A and 4B, a package assembly 58
constructed using a component 10 is illustrated. The assembly 58
includes a plastic body 62 and a pattern of lead fingers 60 which
form terminal leads for mounting and electrically engaging the
assembly. The component 10 is attached to the lead fingers 60 in a
lead on chip configuration using adhesive members 68, and is
encapsulated in the plastic body 62. In addition, wires 64 are wire
bonded to the lead fingers 60 and to the bonding pads 34 on the
component 10. Further, wire bonds 66 are formed between the wires
64 and the bonding pads 34 on the component 10. The wire bonds 66
provide an increased reliability, a larger process window and
prevent damage to the component 10 substantially as previously
described.
[0060] Referring to FIGS. 5A and 5B, an alternate embodiment
component 10A constructed in accordance with the invention is
illustrated. The component 10A is substantially similar to the
previously described component 10, and includes a polymer layer 30A
and bonding pads 34A in electrical communication with conductors
(not shown). The bonding pads 34A are constructed as a metal stack
substantially as previously described, but are not encapsulated in
a second polymer layer (e.g., 40--FIG. 1J). The component 10A also
includes terminal contacts 70A formed on the bonding pads 34A which
are arranged in a ball grid array (BGA). In this case the terminal
contacts 70A are in the form of stud bumps fabricated using a wire
bonder, ball bonder or similar apparatus. Preferably the terminal
contacts 70A are formed while the component 10A is still on the
substrate 14 (e.g., at FIG. 1E of the previously described
method).
[0061] The terminal contacts 70A can comprise a metal such as Cu,
Al or Au. In addition, the terminal contacts 70A can be used to
flip chip bond the component 10A to a mating component such as a
module substrate, package substrate or printed circuit board. The
terminal contacts 70A can also be configured in other patterns, and
used to wire bond the component 10A to a supporting substrate
substantially as previously described. However, in this case double
bonds are formed by the terminal contacts 70A and the wire bonds to
the terminal contacts 70A.
[0062] Referring to FIGS. 6A and 6B, a stacked electronic assembly
72 fabricated using an alternate embodiment interposer component
10I is illustrated. The interposer component 10I includes
conductors 32I and bonding pads 34I constructed as a metal stack
substantially as previously described for conductors 32 and bonding
pads 34. However, the interposer component 10I does not include
integrated circuits in electrical communication with the bonding
pads 34I. Rather, the interposer component 10I can be fabricated
from a blank semiconductor wafer, or alternately from a
non-conductive material such as ceramic or plastic. In addition,
the bonding pads 34I are configured to interconnect a lower die 74
(or substrate) and an upper die 76, in a stacked wedding cake
configuration. As such, the footprint of each element decreases as
the top of the stack is approached. In the illustrative embodiment,
the interposer component 10I is stacked and attached to the lower
die 74, and wires 78 are wire bonded to wire bonding pads 34I on
the interposer component 10I and to bonding pads 82 on the lower
die 74. In addition, the upper die 76 is stacked and attached to
the interposer 10I and wires 78 are wire bonded to bonding pads 84
on the upper die 76 and to the bonding pads 34I on the interposer
component 10I.
[0063] Thus the invention provides improved semiconductor
components, a wafer level method for fabricating the components,
and electronic assemblies incorporating the components. While the
invention has been described with reference to certain preferred
embodiments, as will be apparent to those skilled in the art,
certain changes and modifications can be made without departing
from the scope of the invention as defined by the following
claims.
* * * * *