U.S. patent application number 11/543224 was filed with the patent office on 2007-02-08 for delay distribution calculation method, circuit evaluation method and false path extraction method.
This patent application is currently assigned to Matsushita Electric Industrial Co., Ltd.. Invention is credited to Masahiro Fukui, Masakazu Tanaka, Shuji Tsukiyama.
Application Number | 20070033554 11/543224 |
Document ID | / |
Family ID | 27345243 |
Filed Date | 2007-02-08 |
United States Patent
Application |
20070033554 |
Kind Code |
A1 |
Tsukiyama; Shuji ; et
al. |
February 8, 2007 |
Delay distribution calculation method, circuit evaluation method
and false path extraction method
Abstract
Delay distribution in an integrated circuit is calculated while
taking into account a correlation of performance between
interconnects or elements in the integrated circuit, thereby
improving estimation accuracy. Circuit information, performance
distribution information of the interconnects or elements in the
integrated circuit, and correlation information of performance
between the interconnects or elements are input. A vertex is
selected for calculation, and a correlation between delay
distribution at the selected vertex and delay distribution in a
partial circuit including the selected vertex is calculated based
on the performance distribution information and the correlation
information.
Inventors: |
Tsukiyama; Shuji; (Tokyo,
JP) ; Tanaka; Masakazu; (Kyoto, JP) ; Fukui;
Masahiro; (Osaka, JP) |
Correspondence
Address: |
MCDERMOTT WILL & EMERY LLP
600 13TH STREET, N.W.
WASHINGTON
DC
20005-3096
US
|
Assignee: |
Matsushita Electric Industrial Co.,
Ltd.
Osaka
JP
|
Family ID: |
27345243 |
Appl. No.: |
11/543224 |
Filed: |
October 5, 2006 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10739309 |
Dec 19, 2003 |
7131082 |
|
|
11543224 |
Oct 5, 2006 |
|
|
|
09988602 |
Nov 20, 2001 |
6684375 |
|
|
10739309 |
Dec 19, 2003 |
|
|
|
Current U.S.
Class: |
716/108 ;
716/106 |
Current CPC
Class: |
G06F 30/00 20200101;
G06F 30/3312 20200101; G06F 2111/08 20200101; G05B 19/0421
20130101; G06F 2119/12 20200101 |
Class at
Publication: |
716/004 ;
716/006; 716/005 |
International
Class: |
G06F 17/50 20060101
G06F017/50 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 22, 2000 |
JP |
2000-355417 |
Nov 28, 2000 |
JP |
2000-360629 |
Jan 9, 2001 |
JP |
2001-001075 |
Claims
1-15. (canceled)
16. A method for extracting a false path in an integrated circuit
to be designed, wherein the false path is extracted using an
activating condition of a non-control signal edge within each logic
gate included in the integrated circuit.
17. The method according to claim 16, comprising the steps of:
propagating a logic value listed in the activating condition of a
non-control signal edge within a first gate by a propagation
process; conducting repeatedly the propagation step while the value
to be propagated is a control signal; and detecting a path from the
first gate to a second gate as the false path when the propagated
value is inconsistent with the activating condition of a
non-control signal edge within the second gate.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention generally relates to technology of
evaluating performance of an integrated circuit such as CMOS
(Complementary Metal-Oxide Semiconductor) and LSI (Large Scale
Integration) in its design. More particularly, the present
invention relates to technology of calculation of delay
distribution, and removal and extraction of false paths.
[0002] In the VLSI (Very Large Scale Integration) design in deep
sub-micron era, it is necessary to take variation in manufacturing
process into account in advance so that circuits with required
performance are produced with high yield. Like the technology such
as OPC (Optical Proximity Correction), variation control by mask
shape correction has become possible, and is increasingly required
in practical applications. Therefore, the future VLSI physical
design requires technology of designing a highly integrated, high
performance circuit by setting proper design margins for each
transistor in view of the manufacturing variation.
[0003] A method for estimating variation in circuit performance
such as critical path delay resulting from manufacturing variation
is essential to such design technology. Since the distribution of
critical path delay is independent of input, statistical static
timing analysis can be used as a method for estimating variation in
critical path delay.
[0004] One method for statistical static timing analysis is to
estimate the maximum delay on the assumption that variations in
signal transmission time do not have a correlation (disclosed in M.
Hashimoto and H. Onodera, "A performance optimization method by
gate resizing based on statistical static timing analysis," Proc.
Workshop on Synthesis And System Integration of Mixed Technology
(SASIMI 2000), pp. 77-82, 2000).
[0005] On the other hand, one method for static timing analysis of
a combinational circuit formed from CMOS logic gates is as follows:
a given circuit 100 as shown in FIG. 9 is represented by an acyclic
graph G=(V, E) 200 as shown in FIG. 10, and in this graph G 200,
the maximum delay required to propagate a value "0" or "1" is
obtained for each output terminal v.
[0006] In FIG. 10, each dashed ellipse 210 corresponds to a primary
input terminal and a primary output terminal of the circuit and
input/output terminals of a logic gate. A white circle 211 and a
black circle 212 in an ellipse 210 corresponding to a terminal v
are 0-vertex v0 and 1-vertex v0 of v, respectively, where v0 and v1
indicate that the corresponding terminal v has signal values "0"
and "1", respectively.
[0007] Moreover, S indicates a set of sources into which no edge
comes, and T is a set of sinks from which no edge goes out. The
sources correspond to the primary input terminals, and the sinks
correspond to the primary output terminals. Each directed path from
a source to a sink in the graph G is referred to as a path.
Although the direction of each edge is not shown in FIG. 10, every
edge is a directed edge going out from a left vertex and coming
into a right vertex.
[0008] In FIG. 10, each box 221, 222, 223 represents a logic gate
in the circuit 100. The left vertices in each box correspond to the
input terminals of the corresponding logic gate, and the right
vertices in each box correspond to the output terminal of the
corresponding logic gate. Each edge in the box goes out from a
vertex representing input of the corresponding logic gate into a
vertex representing output thereof. In the case where the box
represents a NAND gate or a NOR gate, each edge in the box
corresponds to pMOS or nMOS in the corresponding gate. The way to
generate the edges is determined according to the type of logic
gate. Each edge connecting vertices in different boxes corresponds
to an interconnect, and edge e0 going out from 0-vertex of a
terminal reaches 0-vertex of another terminal, and edge e1 going
out from 1-vertex of a terminal reaches 1-vertex of another
terminal.
[0009] The true maximum delay required to propagate a value "0" to
a terminal v is herein denoted by d0(v), and the true maximum delay
required to propagate a value "1" is herein denoted by d(1).
Herein, d0(v), d1(v) for each terminal v of the circuit are
represented by the longest path lengths d(v0), d(v1) from a sink to
v0, v1on the graph G, respectively. Therefore, the delay required
to transmit a signal value from a terminal v to a terminal w is
assigned to each edge e=(v, w) as a weight t(e).
[0010] Simulation using such an acyclic graph made it possible to
conduct timing analysis of a logic circuit by a relatively simple
process.
[0011] In delay calculation of a signal z in the circuit 100 as
shown in FIG. 9, however, if the delays of signals x and y heavily
depend on the delay of a signal b, there is a significant
correlation between the delays of the signals x and y. If there is
variation in interconnect delay, there is also a correlation
between the signal transmission delays of fanout of the signal b.
Accordingly, the statistical analysis that does not take
correlation into account is likely to be inaccurate.
[0012] When delay distribution estimation has poor accuracy, it
must be ensured that an integrated circuit will operate in a normal
condition even under a plurality of worst conditions which are not
likely to occur simultaneously in actual situations, resulting in
design including excessive margins. This unnecessarily increases
the area and costs such as power consumption in the designed
integrated circuit.
[0013] The conventional methods have additional problems.
[0014] The conventional methods include paths that cannot be
simulated actually (false paths). This results in excessively
increased calculation time, degraded accuracy in delay estimation,
and the like.
[0015] The false paths can be divided into two types: logical false
paths and functional false paths. A logical false path is a path
that will not be activated actually since there is no input for
logically propagating a signal to that path. A functional false
path is a path that will not be activated since there is an input
for activating that path but such an input will not be produced
actually. For example, in FIG. 11, among the paths passing through
two AND gates G1, G6 controlled by complementary signals z, /z,
such a path that the input x of the AND gate G1 other than the
input z becomes "1" and the output y of the AND gate G6 becomes "1"
corresponds to a logical false path. For example, when operation by
a series of operating units (X, M, Y) and a series of operating
units (A, M, B) is required, the use of a common multiplier M would
result in a series of operating units (A, M, Y) or (X, M, B).
However, if the specification does not allow simultaneous operation
of the operating units, these series of operating units correspond
to functional false paths.
[0016] It is practically impossible for human beings to find
logical false paths in view of the large circuit scale. Therefore,
an automatic finding method using a computer is essential.
SUMMARY OF THE INVENTION
[0017] It is an object of the present invention to provide a method
for calculating delay distribution of an integrated circuit, which
is capable of calculating delay distribution more accurately
according to an actual circuit.
[0018] It is another object of the present invention to provide an
integrated circuit evaluation method having improved evaluation
accuracy while avoiding effects of a false path. The present
invention also proposes a method for extracting a false path from
an integrated circuit to be designed.
[0019] More specifically, according to the present invention, in a
method for calculating delay distribution in an integrated circuit
to be designed, the delay distribution is calculated based on
correlation information indicating a correlation of performance
between interconnects or elements that are included in the
integrated circuit.
[0020] According to the present invention, the delay distribution
of the integrated circuit is calculated based on correlation
information indicating a correlation of performance between the
interconnects and elements that are included in the integrated
circuit. This enables the delay distribution of the integrated
circuit to be calculated with improved accuracy.
[0021] Preferably, the delay distribution calculation method
according to the present invention includes the steps of:
generating a graph representing the integrated circuit based on
circuit information indicating connection between elements in the
integrated circuit; and calculating delay distribution of each
vertex in the graph by using performance distribution information
and the correlation information. The performance distribution
information indicates performance distribution of the interconnects
and the elements that are included in the integrated circuit.
[0022] Preferably, the calculation step includes a first step of
selecting from the graph a vertex that does not belong to a set of
vertices whose delay distribution has been calculated as a vertex
for calculation, and a second step of calculating for the vertex
selected in the first step the delay distribution and a correlation
of performance with each vertex belonging to the set, based on the
performance distribution information and the correlation
information, and the first and second steps are repeatedly
conducted while adding to the set the vertex whose delay
distribution has been calculated.
[0023] Preferably, the delay distribution calculation method
according to the present invention includes the step of producing
the correlation information based on layout of the integrated
circuit by using correlation characteristics information. The
correlation characteristics information indicates a relation
between the correlation of performance between the interconnects or
the elements and layout characteristics.
[0024] According to the present invention, a method for evaluating
an integrated circuit to be designed includes: a first step of
producing an equivalent circuit that does not include a signal
transmission path corresponding to a false path, based on circuit
information indicating connection between components in the
integrated circuit; and a second step of evaluating the integrated
circuit by using the equivalent circuit produced in the first
step.
[0025] According to the present invention, evaluation can be
conducted by using the equivalent circuit including no false path,
allowing for rapid, accurate evaluation of performance of the
integrated circuit.
[0026] Preferably, in the circuit evaluation method according to
the present invention, false path information indicating the false
path is used, and the false path information represents the false
path by two vertices on a graph representing the integrated
circuit.
[0027] Preferably, the first step includes the steps of extracting
a first partial circuit provided with a first vertex as an input
and a second vertex as an output, the first vertex and the second
vertex being two vertices representing the false path, making a
copy of the first partial circuit as a second partial circuit, and
modifying connection of the first and second partial circuits and
another circuit such that there exists no path from the first
vertex toward the second vertex.
[0028] According to the present invention, in a method for
extracting a false path in an integrated circuit to be designed,
the false path is extracted using an activating condition of a
non-control signal edge within each logic gate included in the
integrated circuit.
[0029] Preferably, the false path extraction method according to
the present invention includes the steps of: propagating a logic
value listed in the activating condition of a non-control signal
edge within a first gate by a propagation process; conducting
repeatedly the propagation step while the value to be propagated is
a control signal; and detecting a path from the first gate to a
second gate as the false path when the propagated value is
inconsistent with the activating condition of a non-control signal
edge within the second gate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] FIG. 1 is a flowchart illustrating a delay distribution
calculation method according to a first embodiment of the present
invention;
[0031] FIG. 2 shows representation specifying false paths;
[0032] FIG. 3 shows an unmodified graph;
[0033] FIG. 4 is a flowchart illustrating a circuit evaluation
method according to a second embodiment of the present
invention;
[0034] FIG. 5 is a flowchart illustrating the process of producing
an equivalent circuit in the circuit evaluation method of FIG.
4;
[0035] FIG. 6 shows a modified graph;
[0036] FIG. 7 shows another example of the modified graph;
[0037] FIG. 8 is a flowchart illustrating a false path extraction
method according to a third embodiment of the present
invention;
[0038] FIG. 9 shows an example of a logic circuit;
[0039] FIG. 10 shows an acyclic graph representing the circuit of
FIG. 9;
[0040] FIG. 11 shows a logic circuit including false paths.
[0041] FIG. 12 is a flowchart illustrating the process of producing
correlation information; and
[0042] FIG. 13 is a flowchart illustrating the process of obtaining
correlation characteristics information.
DETAILED DESCRIPTION OF THE INVENTION
First Embodiment
[0043] A method for calculating distribution of the maximum delay
value for each terminal v of a circuit will be described in the
first embodiment of the present invention. In the following
description, d0(v) denotes the true maximum delay required to
propagate a value "0" to a terminal v, and dl(v) denotes the true
maximum delay required to propagate a value "1" to a terminal
v.
[0044] First, a given circuit is represented by an acyclic graph
G=(V, E) as shown in FIG. 10. For each edge e=(v, w), delay (weight
of the edge e) t(e) required to transmit a signal value from a
terminal v to a terminal w is regarded as a stochastic variable,
and has a normal distribution N(.mu., .sigma..sup.2) The mean
.beta. and variance .sigma..sup.2 of the delay t(e) are
respectively denoted by .beta.(e) and .sigma..sup.2(e). In other
words, probability density function f(t(e)) of the delay t(e) is
given by the following equation: f .function. ( t .function. ( e )
) = 1 2 .times. .pi. .times. .sigma. .function. ( e ) .times. exp
.function. [ - ( t .function. ( e ) - .mu. .function. ( e ) ) 2 2
.times. .sigma. 2 .function. ( e ) ] . ( 1 ) ##EQU1##
[0045] The delay t(e) of an edge e corresponding to an interconnect
will now be described. It is herein assumed that the interconnect
delay t(e) has variation with a normal distribution.
[0046] When an edge corresponding to an interconnect is an edge
e0=(v0, w0) connecting 0-vertices of vertices v and w, there exists
an edge e1=(v1 , w1) connecting 1-vertices of the vertices v and w.
However, variations of delay t(el) of the edge e1 and delay t(e0)
of the edge e0 are not independent of each other. Moreover, when
two or more edges e'=(v, w'), e''=(v, w'') go out from a vertex v
(that is, when a net has fanout), variations of delays t(e'),
t(e'') of the edges e', e'' are not independent of each other,
either. For such a set of edges (e', e'') in the same net, a
correlation coefficient r(e', e'').noteq.0 is introduced. The delay
of an edge e' corresponding to an interconnect is independent of
the delay of an edge corresponding to an interconnect of a
different net or an edge e'' that does not correspond to an
interconnect (i.e., that is included in a logic gate), so that the
correlation coefficient r(e', e'')=0.
[0047] Hereinafter, the edges corresponding to a logic gate and the
delays thereof will be described. The way to generate the edges in
order to represent the maximum delay required to propagate "0" or
"1'' to an output terminal w of the logic gate by the longest path
length d(w0), d(w1) to 0-vertex w0 or 1-vertex w1 of a vertex w on
the graph G will now be considered.
[0048] First, it is assumed that the logic gate is an AND gate, and
the AND gate has an input terminal v.sub.i (1 . i . k) and an
output terminal w. The delay d(w1) required to set the output w to
"1" corresponds to the time after all inputs v.sub.i become "1".
Therefore, the delay d(w1) is calculated by
d(w1)=max[d(v.sub.i1)+t(e.sub.i1|1.ltoreq.i.ltoreq.k] . . . (2)
under the condition that all inputs v.sub.i are "1". Therefore, for
each input v.sub.i is generated an edge e.sub.i1=(v.sub.i1, w1)
from 1-vertex v.sub.i1 of the input v.sub.i to 1-vertex w1 of w.
The delay t(e.sub.i1) of the edge e.sub.i1 corresponds to the time
required for the output w to become "1" after the input v.sub.i
becomes "1".
[0049] On the other hand, the delay d(w0) required to set the
output w of the AND gate to "0" is determined by the time required
for a single input to become "0". Accordingly, when every input
v.sub.j other than v.sub.i (j .noteq.i; 1 . j . k) is "0 and
d(v.sub.i0)+t(e.sub.i0) . d(v.sub.j0)+t(e.sub.j0),
d(w0)=d(v.sub.i0)+t(e.sub.i0).
[0050] Therefore, d(w0) seems to be given by
d(w0)=min[d(v.sub.i0)+t(e.sub.i0)|1.ltoreq.i.ltoreq.k] . . .
(3).
[0051] However, even when every input v.sub.j other than v.sub.i is
"1", d(w0)=d(v.sub.i0)+t(e.sub.i0). Therefore, provided that every
input v.sub.j other than v.sub.i is "1" for 1 . j . k, the maximum
delay d(w0) required to set w to "0" is given by the following
equation: d(w0)=max[d(v.sub.i0)+t(e.sub.i0)|1.ltoreq.i.ltoreq.k] .
. . (4).
[0052] Therefore, for each input v.sub.i is generated an edge
e.sub.i0=(v.sub.i0, w0) from 0-vertex v.sub.i0 of the input v.sub.i
to 0-vertex of the output w. The delay d(e.sub.i0) of the edge
e.sub.i0 corresponds to the time required for the output w to
become "0" after the input v.sub.i becomes "0".
[0053] Thus adding the edges within the AND gate and determining
the delays thereof enables the delays d(w1), d(w0) to be calculated
by the maximum operation.
[0054] Hereinafter, specific description will be given for the case
where the logic gate is a NAND gate. In this case, the expressions
for setting the output w to "1" and for setting the output w to "0"
need only be switched each other in the above equations (2), (4).
Therefore, the delays d(w1), d(w0) can be calculated by the
following equations:
d(w1)=max[d(v.sub.i0)+t(e.sub.i0)|1.ltoreq.i.ltoreq.k] . . . (5).
d(w0)=max[d(v.sub.i1)+t(e.sub.i1)|1.ltoreq.i.ltoreq.k] . . .
(6).
[0055] Accordingly, for each input v.sub.i are generated an edge
e.sub.i0=(v.sub.i0, w1) from 0-vertex v.sub.i0 of the input v.sub.i
to 1-vertex w1 of the output w, and an edge e.sub.i1=(v.sub.i1, w0)
from 1-vertex v.sub.i1 of the input v.sub.i to 0-vertex w0 of the
output w. The delay t(e.sub.i0) of the edge e.sub.i0 corresponds to
the time required for the output w to become "1" after the input
v.sub.i becomes "0" , and the delay t(e.sub.i1 ) of the edge
e.sub.i1 corresponds to the time required for the output w to
become "0" after the input v.sub.i becomes "1" . In the case where
the logic gate is an inverter, k=1.
[0056] From the same discussion, in the case where the logic gate
is an OR (or NOR) gate as well, d(w0) (d(w1) in the case of the NOR
gate) and d(w1) (d(w0) in the case of the NOR gate) can be
calculated by the following equations:
d(w0)=max[d(v.sub.i0)+t(e.sub.i0)|1.ltoreq.i.ltoreq.k] . . . (7).
d(w1)=max[d(v.sub.i1)+t(e.sub.i1)|1.ltoreq.i.ltoreq.k] . . .
(8).
[0057] Accordingly, the edges are generated for the OR gate in the
same manner as that for the AND gate, and are generated for the NOR
gate in the same manner as that for the NAND gate. In the case of a
CMOS composite gate as well, the edges are generated in the same
manner as that for the NAND (NOR) gate.
[0058] In the case of an XOR gate, however, a value "0" of the
input v.sub.i may set the output w to either a value "0" or "1".
Moreover, a value "138 of the input v.sub.i may set the output w to
either a value "O" or "1". Therefore, for each input v.sub.i are
generated an edge e.sub.i00=(v.sub.i0, w0) from 0-vertex v.sub.iof
the input v.sub.i to 0-vertex w0 of the output w, an edge
e.sub.i01=(v.sub.i0, w1) from 0-vertex v.sub.i0 of the input
v.sub.i to 1-vertex w1 of the output w, an edge e.sub.il
10=(v.sub.i1, w0) from 1-vertex v.sub.i1 of the input v.sub.i to
0-vertex w0 of the output w, and an edge e.sub.i11 =(v.sub.i1, w1)
from 1-vertex v.sub.11 of the input v.sub.i to 1-vertex w1 of the
output w. The delay t(e.sub.ibb) of each edge e.sub.ibb' (v.sub.ib,
wb') corresponds to the time required for the output w to become b'
after the input v.sub.i becomes b, where b and b' indicate either
"0" or "1" .
[0059] By thus generating the edges within the logic gate, the
longest path length to each sink obtained in the acyclic graph
G=(V, E) is a candidate for critical path delay.
[0060] Hereinafter, variation in delay in the logic gate will be
described.
[0061] In the case of a NAND gate, NOR gate or CMOS composite gate,
the delays t(e.sub.i0) and t(e.sub.i1) of the edges correspond to
switching delays of pMOS and nMOS to which the input v.sub.i of the
gate is connected. Such a switching delay is the time during which
a transistor is in a saturation region, and is determined by a
saturation drain current I.sub.dsat, load capacitance C to be
driven, slew rate of the gate voltage, and the like. The saturation
drain current I.sub.dsat has variation, which mostly depends on
variation in the gate length L. Like a threshold voltage V.sub.th,
the variation in the gate length L is approximately modeled by
normal distribution. Therefore, the switching delay t(e.sub.ib) is
also modeled by normal distribution N(.beta., .sigma..sup.2).
[0062] Variation in the gate length L is affected by the spacing P
between adjacent polysilicon gates, the transistor gate width W.
the length L.sub.DIF of a diffusion region, and the like.
Accordingly, by finding the relation between these values and
variation in the gate length L, the spacing P, gate width W and
diffusion region length L.sub.DIF can be obtained from the layout
pattern. As a result, variation in the gate length L can be
predicted, and hence variation in the switching delay can be
estimated.
[0063] Such variation in the delay is affected by the spacing
between adjacent polysilicon gates. Thus, variations of the delays
of the edges corresponding to adjacent transistors are not
independent of each other. Therefore, for a set of edges (e', e'')
included in the same logic gate, a correlation coefficient r(e',
e'' ).noteq.0 is introduced. Such a correlation is considered for
the logic gates other than the NAND gate and the NOR gate. When
there is no correlation, correlation coefficient r(e', e'')=0.
[0064] Since only the edges included in the same logic gate have a
correlation, delays of the edges e', e'', included in different
gates are independent of each other, and hence r(e', e'')=0. In the
case of the NAND gate and the NOR gate, delays of the edges e', e''
corresponding to different types of MOS are also independent of
each other.
[0065] Since only the edges corresponding to the interconnects in
the same net and the edges within a single logic gate have a
correlation in terms of variation in the delay, there exists no
(directed) path that passes through the edges having a correlation
in terms of the delay. Accordingly, the delays of all the edges on
a single path are independent of each other.
[0066] Hereinafter, calculation of maximum delay distribution of a
circuit of interest will be described using the delay distributions
of the logic gate and interconnects and the correlation
therebetween.
[0067] When stochastic variables x and y with a correlation
coefficient R[x, y]=.rho. have normal distributions N(.mu..sub.1,
.sigma..sub.1.sup.2) and N(.mu..sub.2, .sigma..sub.2.sup.2),
respectively, the mean Exp[t] and variance Var[t] of t(=max[x, y])
are obtained by the following equations unless
.sigma..sub.1.sup.2-.sigma..sub.2 .sup.2=.sigma.-1=0: Exp
.function. [ t ] = .mu. 1 .PHI. .function. ( .beta. ) + .mu. 2
.PHI. .function. ( - .beta. ) + .alpha. .phi. .function. ( - .beta.
) ( 9 ) Var .function. [ t ] = ( .mu. 1 2 + .sigma. 1 2 ) .PHI.
.function. ( .beta. ) + ( .mu. 2 2 + .sigma. 2 2 ) .PHI. .function.
( - .beta. ) + ( .mu. 1 + .mu. 2 ) .alpha. .phi. .function. (
.beta. ) - Exp .function. [ t ] 2 ( 10 ) ##EQU2## where t is
approximated to a normal distribution with two variables, and
.alpha.=
.sigma..sub.1.sup.2+.sigma..sub.2.sup.2-2.sigma..sub.1.sigma..sub.2.rho.
(11) .beta.=(.mu..sub.1-.mu..sub.2)/.alpha. (12) .phi. .function. (
x ) = 1 2 .times. .pi. .times. exp .function. [ - x 2 2 ] ( 13 )
.PHI. .function. ( x ) = 1 2 .times. .pi. .times. .intg. - .infin.
x .times. exp .function. [ - y 2 2 ] .times. d y ( 14 ) ##EQU3##
(disclosed in C. E. Clark, "The greatest of a finite set of random
variables" Operations Research, vol. 9, pp. 145-152, 1961).
[0068] Provided that correlation coefficients between z and x and
between z and y are R[x, z]=.rho.1 and R[y, z]=.rho.2,
respectively, a correlation coefficient R[t, z] between t and a
stochastic variable z with a normal distribution is given by the
following equation using normal distributions of the three
variables x, y, z: R .function. [ t , z ] = R .function. [ max
.function. [ x , y ] , z ] = [ .sigma. 1 .rho. 1 .PHI. .function. (
.beta. ) + .sigma. 2 .rho. 2 .PHI. .function. ( - .beta. ) ] Var
.function. [ t ] . ( 15 ) ##EQU4##
[0069] When using the above equations, the following equations
regarding probability are required. Provided that f(x.sub.1,
x.sub.2) is a probability density function of two variables
x.sub.1, x.sub.2, the mean Exp[x.sub.1+X.sub.2] and variance
Var[x.sub.1+x.sub.2] of x.sub.1+x.sub.2 are calculated by the
following equations (16) and (17): Exp .function. [ x 1 + x 2 ] =
.times. .intg. - .infin. .infin. .times. .intg. - .infin. .infin.
.times. ( x 1 + x 2 ) f .function. ( x 1 , x 2 ) .times. d x 1
.times. d x 2 = .times. .intg. - .infin. .infin. .times. .intg. -
.infin. .infin. .times. x 1 f .function. ( x 1 , x 2 ) .times. d x
1 .times. d x 2 + .times. .intg. - .infin. .infin. .times. .intg. -
.infin. .infin. .times. x 2 f .times. ( x 1 , x 2 ) .times. d x 1
.times. d x 2 = .times. .intg. - .infin. .infin. .times. x 1 f x 2
.function. ( x 1 ) .times. d x 1 + .times. .intg. - .infin. .infin.
.times. x 2 f x 1 .function. ( x 2 ) .times. d x 2 = .times. .mu. 1
+ .mu. 2 ( 16 ) Var .function. [ x 1 + x 2 ] = .times. .intg. -
.infin. .infin. .times. .intg. - .infin. .infin. .times. ( x 1 + x
2 - .mu. 1 - .mu. 2 ) 2 .times. f .times. ( x 1 , x 2 ) .times. d x
1 .times. d x 2 = .times. .intg. - .infin. .infin. .times. .intg. -
.infin. .infin. .times. { ( x 1 - .mu. 1 ) + ( x 2 - .mu. 2 ) } 2
.times. f .times. ( x 1 , x 2 ) .times. d x 1 .times. d x 2 =
.times. .intg. - .infin. .infin. .times. .intg. - .infin. .infin.
.times. ( x 1 - .mu. 1 ) 2 .times. f .times. ( x 1 , x 2 ) .times.
d x 1 .times. d x 2 + .times. .intg. - .infin. .times. .infin.
.times. .intg. - .infin. .times. .infin. .times. ( .times. x
.times. 1 .times. - .times. .mu. .times. 1 ) 2 .times. f .times. (
x .times. 1 , x .times. 2 ) .times. d x .times. 1 .times. d x
.times. 2 + .times. .intg. - .infin. .times. .infin. .times. .intg.
- .infin. .times. .infin. .times. 2 .times. ( x 1 - .mu. 1 )
.times. ( x 2 - .mu. 2 ) .times. f .times. ( x .times. 1 , x
.times. 2 ) .times. d x .times. 1 .times. d x .times. 2 = .times.
.sigma. 1 2 + .sigma. 2 2 + 2 Cov .function. [ x 1 , x 2 ] . ( 17 )
##EQU5##
[0070] The mean Exp[x.sub.1+x.sub.2] and variance
Var[x.sub.1+x.sub.2] of x.sub.1+x.sub.2 are thus given by the
following equations (18) and (19):
Exp[x.sub.1+x.sub.2]=Exp[x.sub.1]+Exp[x.sub.2] (18)
Var[x.sub.1+x.sub.2]=Var[x.sub.1]+Var[x.sub.2]+2Cov[x.sub.1,
x.sub.2] (19) where Cov[x.sub.1, x.sub.2] indicates covariance.
Provided that R[x.sub.1, x.sub.2] is a correlation coefficient,
Cov[x.sub.1, x.sub.2] is defined by the following equation (20):
Cov[x.sub.1, x.sub.2]=SQRT[Var[x.sub.1]Var[x.sub.2]]R[x.sub.1,
x.sub.2] (20).
[0071] Provided that f(x.sub.1, x.sub.2, x.sub.3) is a probability
density function of the three variables x.sub.1, x.sub.2, x.sub.3,
covariance of x.sub.1+x.sub.2 and x.sub.3, Cov[x.sub.1+x.sub.2,
x.sub.3], can be calculated by the following equation (21): Cov
.function. [ x 1 + x 2 , x 3 ] = .times. .intg. - .infin. .infin.
.times. .intg. - .infin. .infin. .times. .intg. - .infin. .infin.
.times. ( x 1 + x 2 - .mu. 1 - .mu. 2 ) .times. ( x 3 - .mu. 3 )
.times. f .times. ( x 1 , x 2 , x 3 ) .times. d x 1 .times. d x 2
.times. d x 3 = .times. .intg. - .infin. .infin. .times. .intg. -
.infin. .infin. .times. .intg. - .infin. .infin. .times. ( x 1 -
.mu. 1 ) .times. ( x 3 - .mu. 3 ) .times. f .times. ( x 1 , x 2 , x
3 ) .times. d x 1 .times. d x 2 .times. d x 3 + .times. .intg. -
.infin. .infin. .times. .intg. - .infin. .infin. .times. .intg. -
.infin. .infin. .times. ( x 2 - .mu. 2 ) .times. ( x 3 - .mu. 3 )
.times. f .times. ( x 1 , x 2 , x 3 ) .times. d x 1 .times. d x 2
.times. d x 3 = .times. Cov .function. [ x 1 , x 3 ] + Cov
.function. [ x 2 , x 3 ] . ( 21 ) ##EQU6## Thus,
Cov[x.sub.1+x.sub.2, x.sub.3] is given by the following equation
(22): Cov[x.sub.1+x.sub.2, x.sub.3]=Cov[x.sub.1,
x.sub.3]+Cov[x.sub.2, x.sub.3] (22)
[0072] The given graph has a plurality of series edges. The
procedure of replacing two series edges e'=(u, v), e'=(v, w) with a
single edge e*=(u, v) will now be described using the above
equations.
[0073] It is obvious from the way to produce the graph that the
delays t(e') and t(e'' ) are independent of each other, and hence
t(e*)=t(e')+t(e'' ). Therefore, the following equations (23) and
(24) are satisfied: .mu.(e*)=.mu.(e')+.mu.(e'') (23)
.sigma..sup.2(e*)=.sigma..sup.2(e')+.sigma..sup.2(e'') (24)
[0074] From the above equations (20) and (22), a correlation
coefficient .rho.(e*, e) between t(e*) and delay t(e) of another
edge e is given by the following equation (25): .rho. .function. (
e * , e ) = { .sigma. .function. ( e ' ) .rho. .function. ( e ' , e
) + .sigma. .function. ( e '' ) .rho. .function. ( e '' , e ) } /
.sigma. 2 .function. ( e ' ) + .sigma. 2 .function. ( e '' ) . ( 25
) ##EQU7## This can be confirmed by the following equation (26):
.rho. .function. ( e * , e ) = Cov .function. [ t .function. ( e *
) , t .function. ( e ) ] .sigma. .function. ( e * ) .sigma.
.function. ( e ) = Cov .function. [ t .function. ( e ' ) , t
.function. ( e ) ] + Cov .function. [ t .function. ( e '' ) , t
.function. ( e ) ] .sigma. .function. ( e * ) .sigma. .function. (
e ) = .sigma. .function. ( e ' ) .sigma. .function. ( e ) .rho.
.function. ( e ' , e ) + .sigma. .function. ( e '' ) .sigma.
.function. ( e ) .rho. .function. ( e '' , e ) .sigma. .function. (
e ) .sigma. 2 .function. ( e ' ) + .sigma. 2 .function. ( e '' ) =
{ .sigma. .function. ( e ' ) .rho. .function. ( e ' , e ) + .sigma.
.function. ( e '' ) .rho. .function. ( e '' , e ) } / .sigma. 2
.times. ( e ' ) + .sigma. 2 .function. ( e '' ) . ( 26 ) ##EQU8##
Such replacement of the series edges does not change independency
of the delays of the edges on a path. In other words, if there is a
path passing through both e and e*, .rho. (e*, e)=0.
[0075] A probability density function f(x.sub.1, x.sub.2, . . . ,
x.sub.n) of normal distribution with n variables is given by the
following equation (27): f .function. ( x 1 , x 2 , .times. , x n )
= .sigma. ij ( 2 .times. .pi. ) n .times. exp .function. [ - 1 2
.times. ( x - .mu. ) .tau. .times. ( .sigma. ij ) .times. ( x -
.mu. ) ] ( 27 ) ##EQU9##
[0076] where (x-.mu.) is a vector, (x-.mu.).sup..tau.is a
transposed vector of (x -.mu.), and (x
-.mu.).sup..tau.=(x.sub.1-.mu..sub.1, x.sub.2-.mu..sub.2, . . . ,
x.sub.n-.mu..sub.n). .sigma..sub.ij is a symmetric matrix given by
the following equation (28), and .sigma. .sigma. ij = ( .sigma. ij
) - 1 .times. : .times. .times. .sigma. ij = ( .sigma. 1 2 .times.
.sigma. 1 .times. .sigma. 2 .times. .rho. 12 .sigma. 1 .times.
.sigma. n .times. .rho. 1 .times. .times. n .sigma. 1 .times.
.sigma. 2 .times. .rho. 12 .sigma. 2 2 .times. .sigma. 2 .times.
.sigma. n .times. .rho. 2 .times. n .sigma. 1 .times. .sigma. n
.times. .rho. 1 .times. n .sigma. 2 .times. .sigma. n .times. .rho.
2 .times. n .sigma. n 2 .times. ) . ( 28 ) ##EQU10##
|.sigma..sub.ij|is a determinant of .sigma..sub.ij. .mu.,
.sigma..sup.2 and .rho. correspond to the mean, variance and
correlation coefficient.
[0077] A probability density function f(x.sub.1, x.sub.2) of normal
distribution with two variables having a correlation coefficient
.rho. is given by the following equation (29): f .function. ( x 1 ,
x 2 ) = 1 2 .times. .pi..sigma. 1 .times. .sigma. 2 .times. 1 -
.rho. 2 .times. exp .function. [ - 1 2 .times. ( 1 - .rho. 2 )
.times. { ( x 1 - .mu. 1 .sigma. 1 ) 2 - 2 .times. .rho. .function.
( x 1 - .mu. 1 .sigma. 1 ) .times. ( x 2 - u 2 .sigma. 2 ) + ( x 2
- .mu. 2 .sigma. 2 ) 2 } ] . ( 29 ) ##EQU11## For .rho.=1, the two
variables x.sub.1, x.sub.2 have the following relation: x 1 - .mu.
1 .sigma. 1 = x 2 - .mu. 2 .sigma. 2 . ( 30 ) ##EQU12##
[0078] Provided that f(x.sub.1, x.sub.2, . . . , x.sub.n) is a
probability density function with n variables, the probability
Pro[max[x.sub.1, x.sub.2, . . . , x.sub.n]D] that all variables are
not greater than D is given by the following equation (31): Pro
.function. [ max .function. [ x 1 , x 2 , .times. , x n ] .ltoreq.
D ] = .intg. - .infin. D .times. .intg. - .infin. D .times. .times.
.times. .intg. - .infin. D .times. f .function. ( x 1 , x 2 ,
.times. , x n ) .times. d x 1 .times. d x 2 .times. .times. .times.
d x n . ( 31 ) ##EQU13## Such a value D that the probability
Pro[max[x.sub.1, x.sub.2, . . . , x.sub.n]D] is equal to or less
than a specified value Y is obtained by solving the following
integral equation (32): =.intg..sub.-.infin..sup.D
.intg..sub.-.infin..sup.D . . . .intg..sub.-.infin..sup.D
f(x.sub.1, x.sub.2, . . . , x.sub.n)dx.sub.xdx.sub.2. . . dx.sub.n
(=) [Calculation of Delay Distribution]
[0079] Hereinafter, a method for calculating delay distribution of
an integrated circuit using the above relations will be
described.
[0080] More specifically, distribution of the maximum delay d(v) to
a vertex v of a sink set T (v .di-elect cons. T) (i.e., mean
Exp[d(v)] and variance Var[d(v)]), and correlation coefficient
R[d(v), d(w)] between the delays to vertices v, w of the sink set T
(v, w .di-elect cons. T) are obtained. Once these values are
obtained, the probability that the critical path delay max[d(v)|v
.di-elect cons. T] is equal to or less than D is obtained from the
above equation (31), assuming that every d(v) has a normal
distribution with |T| variables. The distribution thereof can be
obtained by differentiating the equation (31) by D as given by the
following equation (33): g .function. ( D ) = d [ .intg. - .infin.
D .times. .intg. - .infin. D .times. .times. .times. .intg. -
.infin. D .times. f .function. ( x 1 , x 2 , .times. , x n )
.times. d x 1 .times. d x 2 .times. .times. .times. d x n ] d D . (
33 ) ##EQU14##
[0081] These values can be calculated numerically. However, such
numerical calculation takes a very long time. In contrast,
approximating the above equation (33) by normal distribution
enables high-speed calculation of the distribution by repeatedly
conducting the following procedure (the above equations (9) to
(15)).
[0082] In the following description, d(v) denotes the maximum delay
to each vertex v (the longest path length from a source u (u
.di-elect cons.S) to v), and m(v) (=Exp[d(v)]) and s(v)
(=Var[d(v)]) denote the mean and variance of d(v), respectively.
Moreover, r(v, w) (=R[d(v), d(w)]) denotes the correlation
coefficient between the maximum delays d(v) and d(w) to two
vertices v and w, and c(v, e) (=R[d(v), t(e)]) denotes the
correlation coefficient between the maximum delay d(v) to a vertex
v and the delay t(e) of an edge e.
[0083] FIG. 1 is a flowchart illustrating a delay distribution
calculation method according to the first embodiment of the present
invention. In the present embodiment, distribution of the maximum
delay d(v) from a source to each vertex v (v .di-elect cons. V) is
calculated on the topological order in the acyclic graph G.
Therefore, a vertex set Front that always satisfies the following
conditions (A), (B) and (C) is considered:
[0084] (A) For each vertex v (v .di-elect cons.=Front), the mean
m(v) and variance s(v) of the maximum delay d(v) are known;
[0085] (B) For any two vertices v, u (v, u .di-elect cons. Front),
the correlation coefficient r(v, u) between the maximum delays d(v)
and d(u) is known; and
[0086] (C) For each vertex v (v .di-elect cons. Front), the
correlation coefficient c(v, e) between the maximum delay d(v) and
the delay t(e) of an arbitrary edge e (e .di-elect cons. E) is
known. Note that it is herein assumed that the series edges have
been replaced with a single edge by the method described above.
[0087] First, in step S11, the following information is input:
circuit information 11 indicating connection between elements in an
integrated circuit; performance distribution information 12
indicating performance distribution of interconnects and elements
such as logic gates which are included in the integrated circuit;
and correlation information 13 indicating correlation between delay
distributions of the interconnects and the elements. An acyclic
graph representing the integrated circuit is generated based on the
circuit information 11.
[0088] Then, in step S12, a vertex for delay distribution
calculation is selected. Initially, Front=S (source set), and for
each vertex u (u .di-elect cons. S), m(u)=s(u)=0. Since all the
correlation coefficients between distinct vertices in the set Front
can be set to zero, the above conditions are satisfied. Note that,
if the arrival times of primary inputs vary and have differences,
they can be considered in this step. In the subsequent repetition,
a single vertex is sequentially selected from the acyclic graph on
the topological order.
[0089] Thereafter, in step S13, correlation between the delay
distribution of the vertex selected in step S12 and the vertex that
has already been selected is calculated. A new vertex w is then
added to the set Front while satisfying the above conditions (A),
(B) and (C).
[0090] Assuming that a vertex in the set Front is v.sub.i (i=1, 2,
. . . , k, . . . , h), such a vertex w that every incoming edge
comes from the set Front is considered. For simplification, the
incoming edges to the vertex w are denoted by e.sub.i=(v.sub.i, w)
(i =1, 2, . . . , k). Such a set of vertices v.sub.i (v.sub.i
.di-elect cons. Front) that all the terminal vertices u of the
outgoing edges (v.sub.i, u) are included in FrontU.[w] is denoted
by Eliminate.
[0091] Provided that d'.sub.i(w) is the maximum delay of paths from
a source to the vertex w through an edge e.sub.i=(v.sub.i, w),
d'.sub.i(w)=d(v.sub.i)+t(e.sub.i) (34) Therefore, based on the
above equations (18) to (20), the mean m'i(w) and variance s'i(w)
of d'.sub.i(w) can be obtained by the following equation (35): m i
' .function. ( w ) .times. = .times. Exp .function. [ d i '
.function. ( w ) ] .times. = .times. m .function. ( v i ) .times. +
.times. .mu. .function. ( e i ) .times. .times. s i ' .function. (
w ) = Var .function. [ d i ' .function. ( w ) ] = s .function. ( v
i ) .times. + .times. .sigma. 2 .function. ( e i ) .times. +
.times. 2 .times. .times. .times. s .function. ( v i ) .sigma.
.function. ( e i ) .times. c .function. ( v i , .times. e i ) . (
35 ) ##EQU15##
[0092] Since the delays of the edges e.sub.i are independent of the
delays of the edges on any path leading to v.sub.i, d(v.sub.i) and
t(e.sub.i) are independent of each other, and c(v.sub.i,
e.sub.i)=0. Therefore, the following relation is obtained: s i '
.function. ( w ) = Var .function. [ d i .function. ( w ) ] = s
.function. ( v i ) + .sigma. 2 .function. ( e i ) . ( 36 )
##EQU16##
[0093] From the above equations (20) and (22), for any vertex u (u
.di-elect cons. Front) satisfying s(u).noteq.0 and any edge e (e
.di-elect cons. E), s i ' .function. ( w ) .times. s .function. ( u
) r i ' .function. ( w , u ) = s .function. ( v i ) .times. s
.function. ( u ) r .function. ( v i , u ) + s .function. ( u )
.sigma. .function. ( e i ) c .function. ( u , e i ) ( 37 ) s i '
.function. ( w ) .sigma. .function. ( e ) c i ' .function. ( w , e
) = s .function. ( v i ) .sigma. .function. ( e ) c .function. ( v
i , e ) + .sigma. .function. ( e i ) .sigma. .function. ( e ) .rho.
.function. ( e i , e ) . ( 38 ) ##EQU17## Therefore, the following
relation is obtained: r'.sub.i(w,u)={ s(v.sub.i)r(v.sub.i,
u)+.sigma.(e.sub.i)c(u, e.sub.i)}/ s'.sub.i(i w) (39)
c'.sub.i(w,e)={ s(v.sub.i)c(v.sub.i,
e)+.sigma.(e.sub.i).rho.(e.sub.i, e)}/ s'.sub.i(i w) (40). For
s(u)=0, r'.sub.i(w, u)=0.
[0094] The maximum delay of paths from a source vO to a vertex w
through any of the edges e.sub.j=(v.sub.j, w) (j=1, 2, . . . , i)
is denoted by d.sub.i(w), that is,
d.sub.i(w)=max[d'.sub.j(w)|1.ltoreq.j.ltoreq.i.ltoreq.] (41)
[0095] It is obvious that d.sub.1 (w)=d'.sub.1(w). Therefore, if
the distribution for d.sub.i-1 (w) has been obtained, that is, if
the following values are known, m.sub.i-1(w)=Exp[d.sub.i-1(w)] (42)
s.sub.i-1(w)=Var[d.sub.i-1(w)] (43) r.sub.i-1(w,u)=R[d.sub.i-1(w),
d(u)] (44) c.sub.i-1(w,e)=R[d.sub.i-1(w), t(e)] (45) then the
following equations (46) to (49) below will be obtained:
m.sub.i(w)=Exp[d.sub.i(w)] (46) s.sub.i(w)=Var[d.sub.i(w)] (47)
r.sub.i(w,u)=R[d.sub.i(w), d(u)] (48) c.sub.i(w,e)=R[d.sub.i(w),
t(e)] (49) Therefore, the following equation (50) is used:
d.sub.i(w)=max [d.sub.i-1(w), d'.sub.i(w)] (50).
[0096] Once the distribution of d(w) is obtained from i=2 to i=k,
the vertex w can be added to the set Front. It can be seen that
when the vertex w is added to the set Front, the new set
Front=(Front-Eliminate)U[w] satisfies the above conditions (A), (B)
and (C).
[0097] The distribution of d.sub.i(w) is calculated using the above
equations (9) to (15), that is, the following equation (51):
.alpha.=SQRT[s.sub.i-1(w)+s'.sub.i(w)-2SQRT[s.sub.i-1(w)s'.sub.i(w)]r'(w,-
w)]. . . (51). r'.sub.i(w, w)=R[d.sub.i-1(w), d'i(w)] can be
calculated by the following equation (52): r i ' .function. ( w , w
) = R .function. [ d i - 1 .function. ( w ) , d i ' .function. ( w
) ] = Cov .function. [ d i - 1 .function. ( w ) , d .function. ( v
i ) + t .function. ( e i ) ] s i - 1 .function. ( w ) .times. s i '
.function. ( w ) = Cov .function. [ d i - 1 .function. ( w ) , d
.function. ( v i ) ] + Cov .function. [ d i - 1 .function. ( w ) ,
t .function. ( e i ) ] s i - 1 .function. ( w ) .times. s i '
.function. ( w ) = s i - 1 .function. ( w ) .times. s .function. (
v i ) r i - 1 .function. ( w , v i ) + s i - 1 .function. ( w )
.sigma. .function. ( e i ) c i - 1 .function. ( w , e i ) s i - 1
.function. ( w ) .times. s i ' .function. ( w ) = s .function. ( v
i ) r i - 1 .function. ( w , v i ) + .sigma. .function. ( e i ) c i
- 1 .function. ( w , e i ) s i ' .function. ( w ) . ( 52 )
##EQU18## Accordingly, provided that .alpha. = s i - 1 .function. (
w ) + s i ' .function. ( w ) - 2 .times. s i - 1 .function. ( w )
.times. { s .function. ( v i ) r i - 1 .function. ( w , v i ) +
.sigma. .function. ( e ) c i - 1 .function. ( w , e ) } ( 53 )
.beta. = ( m i - 1 .function. ( w ) - m i ' .function. ( w ) ) /
.alpha. , ( 54 ) ##EQU19## the distribution of di(w) can be
calculated from the following equations (55) to (58): m i
.function. ( w ) = Exp .times. max .times. d i - 1 .function. ( w )
, d j ' .function. ( w ) = m i - 1 .function. ( w ) .PHI.
.function. ( .beta. ) + m i ' .function. ( w ) .PHI. .function. ( -
.beta. ) + .alpha. .phi. .function. ( .beta. ) ( 55 ) s i
.function. ( w ) = .times. Var .function. [ max .function. [ d i -
1 .function. ( w ) , d i ' .function. ( w ) ] ] = .times. { ( m i -
1 .function. ( w ) ) 2 + s i - 1 .function. ( w ) } .times. .PHI.
.function. ( .beta. ) + { ( m i ' .function. ( w ) ) 2 + s i '
.function. ( w ) } .times. .PHI. .function. ( - .beta. ) + .times.
{ m i - 1 .function. ( w ) + m i ' .function. ( w ) } .alpha. .phi.
.function. ( .beta. ) - { m i .function. ( w ) } 2 ( 56 ) r i
.function. ( w , u ) = R .function. [ max .function. [ d i - 1
.function. ( w ) , d i ' .function. ( w ) ] , d .function. ( u ) ]
= s i - 1 .function. ( w ) r i - 1 .function. ( w , u ) .PHI.
.function. ( .beta. ) + s i ' .function. ( w ) r i ' .function. ( w
, u ) .PHI. .function. ( - .beta. ) s i .function. ( w ) ( 57 ) c i
.function. ( w , e ) = R .function. [ max .function. [ d i - 1
.function. ( w ) , d i ' .function. ( w ) ] , t .function. ( e ) ]
= s i - 1 .function. ( w ) c i - 1 .function. ( w , e ) .PHI.
.function. ( .beta. ) + s i ' .function. ( w ) c i ' .function. ( w
, e ) .PHI. .function. ( - .beta. ) s i .function. ( w ) . ( 58 )
##EQU20## Accordingly, by repeating the process of adding a vertex
w within the circuit to the set Front, all the vertices in the
circuit can be added to the set Front, enabling delay distribution
of the circuit to be calculated while taking a correlation into
account.
[0098] By thus repeating the process of removing the set Eliminate
from the set Front and adding a vertex w to the set Front so that
Front=T, the processing is terminated. Whether the-condition for
terminating the processing (that is, Front=T) is satisfied or not
is determined in step S14.
[0099] When delay distribution calculation of all the vertices is
completed, delay distribution information 14 of the output
terminal, that is, the mean and variance of the delay to each
vertex in the sink T, is output in step S15, and the processing is
then terminated. Otherwise, the flow returns to step S12 so that
the processing is continued.
[0100] Note that, in the present embodiment, the correlation
information is represented by the correlation coefficient in the
delay distribution. However, the correlation information may
alternatively be represented by the correlation degree of a delay
value itself. The delay distribution may be calculated using the
correlation regarding performance other than the delay.
[0101] For example, the correlation information may be produced by
referring to the layout of an integrated circuit to be designed by
using correlation characteristic information. The term "correlation
characteristics information'' herein indicates the relation between
correlation of performance between interconnects or elements and
characteristics in terms of the layout. FIG. 12 shows the process
of producing correlation information.
[0102] Characteristics information of the elements include delay,
gate width, gate length, oxide film thickness, ion implantation
concentration, source-drain saturation current and threshold
voltage of a transistor, and the like. The process variation of
these values results from completely random factors, and factors
that vary depending on the layout information such as shape,
location and orientation. For example, the ion implantation
concentration of the transistor diffusion layer depends on the
orientation of an implantation apparatus in the manufacturing
process. Therefore, the same characteristics are more likely to be
obtained when the implantation apparatus has the same orientation.
Moreover, the values such as ion implantation concentration and
oxide film thickness are likely to vary continuously depending on
the location of the elements. For example, two elements are more
likely to exhibit similar characteristics when they are located
closer. Furthermore, the gate width and the gate length are likely
to vary depending on the surrounding layout pattern such as the
distance to another gate. Moreover, there is a strong correlation
of variation between the delays of distinct paths to the same logic
gate and between the interconnect delays in the case where a common
interconnect branches out.
[0103] Examples of the correlation characteristics information are
as follows:
[0104] (1) the distance D between two elements and the correlation
coefficient R between delay distributions of the two elements have
the relation: R=aexp(-D/b) (where a, b are a constant);
[0105] (2) the correlation coefficient is c when two elements are
arranged with the same orientation, but is e when they are arranged
with different orientations (where c, e are a constant);
[0106] (3) when an interconnect branches out, and the rate of a
common part to the entire interconnect length is w, the correlation
between the respective interconnect delays is R=fw (where f is a
constant); and
[0107] (4) the correlation coefficient between element delays is g
when the element delays result from the same element, but is h when
they result from distinct elements (where g, h are a constant).
[0108] Either at least one of the above relations or a combination
thereof may be used.
[0109] The correlation characteristics information may be obtained
by measurement. For example, an integrated circuit including a
multiplicity of sample elements having different orientations,
different surrounding layout patterns, different distances to
another element is manufactured for characteristics evaluation, and
characteristics of each element are measured in order to calculate
the mean and variance of the element characteristics. FIG. 13 shows
the process of obtaining correlation characteristics information.
Even if the correlation between delay distributions cannot be
obtained directly, it is known that a saturation current of a
transistor is approximately proportional to the delay, and that the
gate length is inversely proportional to the saturation current and
the gate width is proportional to the saturation current.
Therefore, if the correlation between the layout conditions and the
values such as gate length, gate width and saturation current can
be obtained, it can be used as correlation between the delays.
[0110] The correlation characteristics information can thus be
obtained prior to the integrated circuit design, according to the
process. In the actual integrated circuit design, correlation
information between elements can be obtained from the correlation
characteristics information, based on the information such as
actual layout.
[0111] For example, correlation coefficient R between delay
distributions of two elements arranged with the same. orientation
and at a distance D is obtained by R=f(D, c, h). Herein, f(x, y, z)
is an arbitrary function, for example, f(x, y, z) =Kyz/x (K is a
constant).
Second Embodiment
[0112] The second embodiment of the present invention relates to a
method for evaluating a given circuit by removing false paths.
[0113] A "logical false path" can be characterized by using
information on the connection structure of a circuit. In other
words, a logical false path can be defined as a path passing
through both two vertices x and y in an acyclic graph G=(V, E). A
"functional false path" can be specified as a path including a
causative path, and a causative path can be defined as a path from
a vertex x of X to a vertex y of Y by using a pair of vertex sets
(X, Y) (disclosed in H. C. Chen and D. H. Du, "Path sensitization
in critical path problem," IEEE Trans. Computer-Aided Design of ICs
and Systems, vol. 12, no. 2, pp. 196-207, 1993).
[0114] More specifically, in FIG. 2, false paths can be designed as
paths passing through both a vertex 41 of X and a vertex 42 of Y in
a specified pair of vertex sets (X, Y). Therefore, removing these
paths from the graph G 400 would enable improved accuracy of the
critical path delay.
[0115] A method for removing the false paths that can be specified
by a pair of vertex sets (X, Y) will now be described. It is herein
assumed that there exists no directed path between distinct two
vertices x' and x'' included in X, and no directed path between
distinct two vertices included in Y. In a logic circuit, x
.di-elect cons. X and y .di-elect cons. Y correspond to an input
and an output of a gate, respectively. Therefore, the above
assumption is not a contrived assumption. A set U' indicates a set
of vertices having both a directed path from a vertex x of X and a
directed path to a vertex y of Y, and a set U indicates the set U'
having X and Y removed therefrom (U=U'-X-Y). G[U]=(U, E[U])
indicates a vertex section graph 43 of the graph G induced by the
set U, where E[U]=[(v, w) .di-elect cons. E|v .di-elect cons. U, w
.di-elect cons. U].
[0116] In FIG. 3, Out is a set 52 of terminal vertices of the edges
going out from the set G[U] other than the vertex 42 of Y. and In
is a set 51 of initial vertices of the edges coming into the set
G[U] other than the vertex 41 of X. In other words, Out and In are
defined as follows: Out={v.di-elect cons.V|(u,v).di-elect cons.E,
u.di-elect cons.U, vU, vY} In={v.di-elect cons.V|(v,u).di-elect
cons.E, u.di-elect cons.U, vU, vX}.
[0117] It is obvious that Out and In satisfy the following
conditions:
[0118] i. Out and In have no common vertex, and there exists no
path from a vertex v of Out to a vertex w of In. The reason for
this is as follows: assuming that there is a directed path from a
vertex v to a vertex w, both a directed path from a vertex of X and
a directed path to a vertex of Y exist for such a vertex v or w,
which is inconsistent with the assumption of the set U;
[0119] ii. there exists no path from a vertex v of Out to a vertex
y of Y; and
[0120] iii. there exists no path from a vertex x of X to a vertex v
of In. Assuming that there exists such a path, the vertex v must be
included in U, which is inconsistent with the assumption of the set
U.
[0121] FIG. 4 is a flowchart illustrating a circuit evaluation
method of the present invention. In FIG. 4, circuit information 21
and false path information 22 are first input in step S21. The
circuit information 21 indicates the connection, performance and
the like of a circuit to be evaluated. The false path information
22 represents each false path by a set of two vertices on the graph
representing the integrated circuit.
[0122] In step S22, an equivalent circuit including no false path
is then produced from the circuit information 21. If there are a
plurality of false paths, step S22 is conducted repeatedly. In step
S33, the circuit is evaluated in terms of the delay, power
consumption and the like by using information 23 on the equivalent
circuit including no false path.
[0123] FIG. 5 is a flowchart illustrating the process in step S22.
An equivalent circuit is produced by modifying the acyclic graph
G=(V, E) for the pair of vertex sets (X, Y).
[0124] First, as shown in FIG. 3, a partial circuit G[U] 43 is
extracted in step S22a. As shown in FIG. 6, in step S22b, a copy of
the partial circuit G[U] 43 is made, and a graph G'' 62
corresponding to a second partial circuit is generated. The
original partial circuit G[U] 43 is represented by a graph G'61
corresponding to a first partial circuit. Then, in step S22c, all
the edges from a vertex in the graph G'61 to y 42 are removed, and
edges EG1 from a corresponding vertex in the graph G'' 62 to y 42
are generated instead. A copy EG3 of each edge EG2 going out from a
vertex of In 51 into a vertex in the graph G'61 is generated
between the vertex of In 51 and a corresponding vertex in the graph
G'' 62. Note that each edge EG4 going out from a vertex in the
graph G'61 into a vertex of Out 52 is left intact.
[0125] If a new sink is created in the graph G'61 or a new source
is created in the graph g'' 62, the process of removing such
vertices and edges connecting thereto is repeated until no sink or
source exists in the graphs G'61 and G'' 62. The acyclic graph thus
generated is denoted by G<(X, Y)>.
[0126] This graph <(X, Y)> satisfies the following
conditions:
[0127] (i) There exists no path in G<(X, Y)> that passes
through both a vertex x of X and a vertex y of Y;
[0128] (ii) For each path in the original graph G that does not
pass through both a vertex of X and a vertex of Y, there exists a
corresponding path in G<(X, Y)>; and
[0129] (iii) For each path in G<(X, Y)>, there exists a
corresponding path (that passes through the same vertex and edge)
in the original graph G.
[0130] Accordingly, obtaining variation in the critical path delay
in G<(X, Y)> corresponds to obtaining variation in the
maximum delay in a path that does not pass through both a vertex of
X and a vertex of Y in the original graph G.
[0131] FIG. 7 shows another example of the graph modifying process
for producing an equivalent circuit satisfying the above
conditions. In step S22c, all the edges from a vertex in the graph
G'61 corresponding to a first partial circuit to a vertex 42 of Y
are removed, and edges EG5 from a corresponding vertex in the graph
G'' 62 corresponding to a second partial circuit to a vertex 42 of
Y are generated instead. After adding G'' 62 to G'61, a copy EG7 of
each edge EG6 going out from a vertex in G'61 into a vertex of Out
52 is generated between a corresponding vertex in G'' 62 to the
vertex in Out 52. Moreover, all the edges going out from a vertex
of In 51 into a vertex in G'61 are removed, and edges EG8 from the
respective vertex of In 51 to a corresponding vertex of G'' 62 are
generated instead.
[0132] In the example of FIG. 6, the graph G'61 corresponding to a
first partial circuit is connected to a first vertex 41, In 51 and
Out 52, but is not connected to a second vertex 42. On the other
hand, the graph G'' 62 corresponding to a second partial circuit is
connected to the second vertex 42 and In 51, but is not connected
to the first vertex 41 and Out 52. As a result, there exists no
path from the first vertex 41 toward the second vertex 42.
[0133] In the example of FIG. 7, the graph G'61 corresponding to a
first partial circuit is connected to the first vertex 41 and Out
52, but is not connected to the second vertex 42 and In 51. On the
other hand, the graph G'' 62 corresponding to a second partial
circuit is connected to the second vertex 42, In 51 and Out 52, but
is not connected to the first vertex 41. As a result, there exists
no path from the first vertex 41 toward the second vertex 42.
[0134] Hereinafter, a method for producing an equivalent circuit
according to the present embodiment will now be described
generally.
[0135] A set of all the false paths to be removed is represented by
a set of pairs of vertex sets, F=[(Xi, Yi)|i =1, 2, . . . , f]. In
order to remove all the false paths from G, the above modifying
process is repeated for each pair (X, Y) (.di-elect cons.F). When
creating G<X, Y>by modifying G, the vertices of U are copied.
Therefore, each pair (X', Y') other than (X, Y) ((X', Y') F-[(X,
Y)]) is corrected as follows by using U:
[0136]
[0137] I. For X'.andgate. U .noteq.f:
[0138] When a copy of a vertex of x'.andgate. U remains in G<X,
Y> without creating a new sink or source, the copied vertex is
added to X'; and
[0139] II. For Y'.andgate. U .noteq.f:
[0140] When a copy of a vertex of Y' .andgate. U remains in G<X,
Y> without creating a new sink or source, the copied vertex is
added to Y'.
[0141] A non-updated pair is denoted by (X', Y') and an updated
pair is denoted by (X'', Y''). It is obvious that there exists no
directed path connecting vertices of X'' and no directed path
connecting vertices of Y'' in G<X, Y>. In G, a set of paths
passing through both a vertex of X and a vertex of Y is denoted by
P(X, Y), and a set of paths passing through both a vertex of X' and
a vertex of Y' is denoted by P(X', Y'). In G<X, Y>, a set of
paths passing through both a vertex of X'' and a vertex of Y'' is
denoted by P'(X'', Y''). Every path included in P'(X'', Y'')
corresponds to a path in P(X', Y'). In other words, every path
corresponding to a path in P(X', Y') and existing in G<X, Y>
is included in P'(X'', Y''). Therefore, no path in G other than
those in P(X', Y') is included in P'(X'', Y'').
[0142] Accordingly, provided that the graph obtained by modifying
G<(X, Y)> for (X', Y') is G'', all the paths in P'(X'', Y'')
have been removed from G''. This means that all the paths in P(X',
Y') are removed from G. In other words, the following conditions
are satisfied:
[0143] (i) There exists no path corresponding to P(X, Y) and no
path corresponding to P(X', Y') in G;
[0144] (ii) All the paths included in G<X, Y> other than
P'(X'', Y'') exist in G''. Accordingly, all the paths in G other
than in P(X, Y) and P(X', Y') exist in G''; and
[0145] (iii) Every path in G'' has a corresponding path in G<X,
Y>, and hence in G.
[0146] From the above, provided that the graph from which all the
false paths specified by F have been removed by repeating the
modification process of the graph and the update process of the
pairs of vertex sets described above is G*=(V*, E*), respective
paths on G*=(V*, E*) and the original graph G=(V, E) have the
following relations:
[0147] (i) For each pair (X, Y) .di-elect cons. F, there exists no
path in G* that passes through both a vertex x of X and a vertex y
of Y;
[0148] (ii) All the paths in G other than the false paths specified
by F exist in G*; and
[0149] (iii) Every path in G* has a corresponding path in G.
[0150] This process can be represented as follows:
[0151] For F=[(X.sub.i, Y.sub.i)|i=1, 2, . . . , f],
G_(1)=G<X_(1), Y_(1)>, G.sub.i=G.sub.i-1<X.sub.i.sup.i-1,
Y.sub.i.sup.i-1>(i=2, . . . , f), where
G.sub.i-1<X.sub.i.sup.i-1, Y.sub.i.sup.i-1>(i=2, . . . , f)
is a graph resulting from modifying the graph G.sub.i-1 for
(X.sub.i.sup.i-1, Y.sub.i.sup.i-1), and (X.sub.i.sup.i-1,
Y.sub.i.sup.i-1) (i=2, . . . , f) is a pair resulting from updating
(X.sub.i.sup.i-2, Y.sub.i.sup.i-2) by using U.sub.i-1 defined by
(X.sub.i-1.sup.i-2, y.sub.i-1.sup.i-2)
[0152] U.sub.i-1 is obtained by removing a vertex of
X.sub.i-1.sup.1-2 and a vertex of Y.sub.i-1.sup.i-2 from a set of
vertices on G.sub.i-1 =G_(i-2)<X.sub.i-1.sup.i-2,
Y.sub.i-1.sup.i-2>that have both a directed path from a vertex
of X.sub.i-1.sup.i-2 and a directed path to a vertex of
Y.sub.i-1.sup.i-2.
[0153] Starting with G_(0)=G, X_(1) (0)=X_(1), Y_(1) (0)=Y_(1), the
process of producing G.sub.i=G.sub.i-1<X.sub.i.sup.i-1,
Y.sub.i.sup.i-1>is repeated for each (X.sub.i, Y.sub.i) (i=1, 2,
. . . , f), whereby G.sub.f is obtained. Provided that a set of all
the paths on G specified by F is P(F)=UiP(X.sub.i, Y.sub.i), there
exists no path on G.sub.f that corresponds to P(F), and each path
on G other than P(F) has a corresponding path on G.sub.f.
Third Embodiment
[0154] The third embodiment of the present invention relates to a
method for extracting false paths from a circuit to be designed.
The extracted false paths can be removed by using the method of the
second embodiment.
[0155] As described above in the second embodiment, a "logical
false path" can be characterized by using information on the
connection structure of a circuit. In other words, a logical false
path can be defined as a path passing through both of two vertices
x, y in an acyclic graph G=(V, E).
[0156] Like a signal value "0" in the AND gate, a signal- value
that determines the output of a logic gate when applied to one
input thereof is called a "control signal" . Like a signal value
"1" in the AND gate, a signal value that does not determine the
output of a logic gate even when applied to one input thereof is
called a "non-control signal" . There are a control signal and a
non-control signal for the AND, OR, NAND and NOR gates, and these
signals have a negative relation. In contrast, in an inverter, both
"0" and "1" are control signals, and in the XOR gate, both "0" and
"1" are non-control signals. In other words, in the AND, OR, NAND
and NOR gates and the inverter, the output is determined when a
control signal applied to one input thereof.
[0157] The process of propagating a control signal.will be defined
for each of the gates. For example, in FIG. 11, when z="1", the
output of the inverter G4 is "0", and the output c of the AND gate
G 5 is "0". Accordingly, z=1 leads to c=0 by the propagation
process. As a result, z=0 when c=1. Note that this relation can be
obtained by an inverse propagation process.
[0158] In order that a non-control signal path is activated in the
AND, OR, NAND and NOR gate, all other input signals of the gate
must be the non-control signal. In contrast, in order that a
control signal path is activated in the AND, OR, NAND and NOR gate,
either the non-control signal is transmitted to each input other
than the input v corresponding to the path, or the control signal
is transmitted to each input other than the input v after it
arrives at the input v. This necessitates the use of the delay
amount to determine whether the control signal path is activated or
not. In contrast, whether the non-control signal path is activated
or not can be determined regardless of the time factor, that is,
can be determined only from the connection and the gate type.
[0159] In the-graph G=(V, E), the condition for an edge to be
activated, that is, the condition that the non-control signal
passes through all other edges coming into w, is given for each
edge e=(v, w) within the logic gate through which the non-control
signal is transmitted. This is herein referred to as "activating
condition of a non-control signal edge e". The condition that the
non-control signal s is transmitted to the other edges e'=(u, w)
coming into w is denoted by Net(u)=s, where Net(u) is the net
(signal) incident to u of G.
[0160] If the signal s of Net(u) has fanout other than u, which is
transmitted to another logic gate L as a control signal, the output
value of the logic gate L is determined by the propagation process.
The logic value listed in the activating condition of a non-control
signal edge is propagated by the propagation process. For example,
in FIG. 11, the activating condition of (v1, w1) in the gate G1 as
a first gate is z=1, that is, Net(u)=1, which can be propagated to
the input a=1 of the gate G4 and the input c =0 of the gate G6. As
described before, z=0 when c=1. Therefore, it can be seen that the
activating condition of an edge (bl, yl) in the AND gate G6 as a
second gate, that is, c =1, will not be satisfied simultaneously
with z=1. In other words, the edges (v1, w1) and (b1, y1) cannot be
activated simultaneously. Therefore, each path passing through both
edges (v1, w1) and (b1, y1) can be determined as a false path. Such
a false path can be specified by a pair of vertices (v1, b1).
[0161] FIG. 8 is a flowchart illustrating a false path extraction
method according to the third embodiment of the present invention.
As shown in FIG. 8, circuit information 31 is first input in step
S31. Then, a requisite condition of a signal for activating a
non-control signal in each gate is determined in step S32.
Enc=(unc, wnc) denotes an edge in the gate whose input corresponds
to a non-control signal ncs, and RE(enc)=[(vnc, wnc) .di-elect
cons. E] denotes a set of edges having the activating condition of
Net(u)=ncs. Net(u) =ncs can determine the value of each net by the
propagation process.
[0162] Thereafter, in step S33, a signal change of the gates that
are not simultaneously activated is extracted based on the
requisite condition determined in step S32. It is now assumed that
the value of an input c of a gate G is a control signal cs of G,
and G has an input b in addition to the input C. Provided that an
edge in the gate G whose input c corresponds to the control signal
ncs is enc'=(cnc, ync), each edge (bnc, ync) in RE(enc')=[(bnc,
ync) .di-elect cons. E] has the activating condition of Net(c)=ncs.
Therefore, the edges (vnc, wnc) (.di-elect cons. RE(enc)) and (bnc,
ync) (.di-elect cons. RE(enc')) will not be activated
simultaneously. Provided that suc(v) is a set of vertices in the
gate G that are accessible from a vertex v through a directed path,
a pair of vertices (vnc, bnc) specifies a false path.
[0163] Provided that m is the number of edges in a graph, all such
pairs of vertices for a single edge enc can be found with time
complexity of O(m). Therefore, all the pairs of vertices can be
found with time complexity of O(m.sup.2).
[0164] As has been described above, according to the present
invention, delay distribution of an integrated circuit is
calculated while taking into account the correlation of performance
between interconnects or elements, allowing for improved delay
estimation accuracy. This prevents excessive margins in integrated
circuit design, enabling reduction in area and power
consumption.
[0165] Moreover, removing the false paths in evaluation of an
integrated circuit allows for reduced time complexity and improved
delay estimation accuracy.
* * * * *