U.S. patent application number 11/195293 was filed with the patent office on 2007-02-08 for method for forming recesses.
This patent application is currently assigned to NANYA TECHNOLOGY CORPORATION. Invention is credited to Chien-Li Cheng, Chung-Yuan Lee, Pei-Ing Lee.
Application Number | 20070032085 11/195293 |
Document ID | / |
Family ID | 37718177 |
Filed Date | 2007-02-08 |
United States Patent
Application |
20070032085 |
Kind Code |
A1 |
Lee; Pei-Ing ; et
al. |
February 8, 2007 |
METHOD FOR FORMING RECESSES
Abstract
A method for forming a recess. The method includes providing a
substrate with two protrusions having a first side wall and a
second side wall opposite to the first side wall disposed above the
substrate, conformally forming a mask layer on the substrate and
the protrusions, tilt implanting the mask layer with a first angle
using a first implanting mask adjacent to the first side wall of
the protrusions, tilt implanting the mask layer with a second angle
using a second implanting mask adjacent to the second side wall of
the protrusions, removing implanted portions of the mask layer to
form a patterned mask layer, and etching the substrate using the
patterned mask layer, thereby forming a recess, wherein distances
from the recess to the two protrusions, respectively, are
different.
Inventors: |
Lee; Pei-Ing; (Changhua
County, TW) ; Lee; Chung-Yuan; (Taoyuan City, TW)
; Cheng; Chien-Li; (Hsinchu City, TW) |
Correspondence
Address: |
QUINTERO LAW OFFICE
1617 BROADWAY, 3RD FLOOR
SANTA MONICA
CA
90404
US
|
Assignee: |
NANYA TECHNOLOGY
CORPORATION
TAOYUAN
TW
|
Family ID: |
37718177 |
Appl. No.: |
11/195293 |
Filed: |
August 2, 2005 |
Current U.S.
Class: |
438/700 ;
257/E21.039; 257/E21.235; 438/703; 438/705; 438/944; 438/947 |
Current CPC
Class: |
H01L 29/66621 20130101;
H01L 27/10823 20130101; H01L 27/10876 20130101; H01L 27/10829
20130101; H01L 21/3086 20130101; Y10S 438/944 20130101; Y10S
438/947 20130101; H01L 21/26586 20130101 |
Class at
Publication: |
438/700 ;
438/703; 438/705; 438/944; 438/947; 257/E21.039 |
International
Class: |
H01L 21/311 20060101
H01L021/311; H01L 21/302 20060101 H01L021/302 |
Claims
1. A method for forming a recess, comprising: providing a substrate
with two protrusions disposed above the substrate, wherein each
protrusion comprises a first side wall and a second side wall
opposite to the first side wall; conformally forming a mask layer
on the substrate and the protrusions; tilt implanting the mask
layer with a first angle using a first implanting mask adjacent to
the first side wall of the protrusions; tilt implanting the mask
layer with a second angle using a second implanting mask adjacent
to the second side wall of the protrusions; removing implanted
portions of the mask layer to form a patterned mask layer; and
etching the substrate using the patterned mask layer, thereby
forming a recess, wherein distances from the recess to the two
protrusions, respectively, are different.
2. The method as claimed in claim 1, wherein the protrusions are
single side buried strap isolations.
3. The method as claimed in claim 1, wherein the mask layer
comprises a first mask layer and a second mask layer overlying the
first mask layer.
4. The method as claimed in claim 3, wherein the first mask layer
is a silicon nitride layer.
5. The method as claimed in claim 3, wherein the second mask layer
is a silicon oxide layer.
6. The method as claimed in claim 1, wherein the first and second
implanting masks are photoresist layers.
7. The method as claimed in claim 1, wherein the mask layer is
implanted with BF.sub.2.
8. The method as claimed in claim 1, wherein the second angle is
larger than the first angle.
9. The method as claimed in claim 1, further comprising forming a
recessed gate in the recess.
10. A method for forming a recess in fabrication of a memory cell,
comprising: providing a substrate with two trench capacitor devices
defining a predetermined area therebetween, wherein upper portions
of the trench capacitor devices are revealed; conformally forming a
mask layer on the substrate and the trench capacitor devices;
forming a first implanting mask on one side of the predetermined
area; tilt implanting the mask layer with a first angle using the
first implanting mask; forming a second implanting mask on the
other side of the predetermined area; tilt implanting the mask
layer with a second angle using the second implanting mask;
removing implanted portions of the mask layer to form a patterned
mask layer; etching the substrate using the patterned mask layer,
thereby forming a recess, wherein distances from the recess to the
two trench capacitor devices, respectively, are different; and
forming a recessed gate in the recess.
11. The method as claimed in claim 10, wherein the upper portion is
a single side buried strap isolation of the trench capacitor
device.
12. The method as claimed in claim 10, wherein the mask layer
comprises a first mask layer and a second mask layer overlying the
first mask layer.
13. The method as claimed in claim 12, wherein the first mask layer
is a silicon nitride layer.
14. The method as claimed in claim 12, wherein the second mask
layer is a silicon oxide layer.
15. The method as claimed in claim 10, wherein the first and second
implanting masks are photoresist layers.
16. The method as claimed in claim 10, wherein forming the first
implanting mask comprises steps of: forming a first photoresist
layer over the substrate and the trench capacitor devices;
recessing the first photoresist layer to be level with or below top
surfaces of the trench capacitor devices; and patterning the first
photoresist layer to form a first implanting mask on one side of
the predetermined area.
17. The method as claimed in claim 10, wherein forming the second
implanting mask comprises steps of: forming a second photoresist
layer over the substrate and the trench capacitor devices;
recessing the second photoresist layer to be level with or below
top surfaces of the trench capacitor devices; and patterning the
second photoresist layer to form a second implanting mask on one
side of the predetermined area.
18. The method as claimed in claim 10, wherein the mask layer is
implanted with BF.sub.2.
19. The method as claimed in claim 10, wherein the second angle is
larger than the first angle.
Description
BACKGROUND
[0001] The present invention relates to a method for forming a
semiconductor structure, and more specifically to a method for
forming a recess.
[0002] Recently, as fabrication techniques for semiconductor
integrated circuits have developed, the number of elements in a
chip has increased. Element size has decreased as integration
density has increased. For example, the area of memory cells in a
memory must be continuously reduced to support a larger number of
memory cells, thereby increasing density. Conventional planar
transistors such as metal oxide semiconductor field effect
transistors (MOSFETs), however, occupy a large amount of surface
area on a chip, substantially reducing the available area
thereon.
[0003] Since the scalability of planar transistors in memory
devices is severely limited, memory cells have looked toward
utilization of vertical transistors. Vertical transistors are
promising candidates for scalability, especially below minimum
feature sizes of 100 nm.
[0004] Typically, as shown in FIG. 1, a memory cell with a vertical
transistor requires forming a recess between two trench capacitors.
The recess is defined by photolithography methods. As the feature
size shrinks to 100 nm below, however, it is difficult to
preciously control the location of the recess. In photolithography,
a misaligned recess pattern may likely be formed on the photoresist
layer due to overlay errors during exposure, causing a serious
alignment shift among such as a recessed gate, an active area, deep
trenches, and a bit line contact and deteriorating the yield of
fabrication. This issue, however, may get more and more serious
while DRAM dimension shrinking. Additionally, as contact slit
margin is reducing, contact failure may occur due to insufficient
margin.
[0005] Thus, it is necessary to develop a method providing a
precise alignment control among semiconductor elements, in
particular, the distances between a recessed gate and deep trenches
and enlarging the margin of contact slit.
SUMMARY
[0006] The invention provides a method for forming a recess. A
substrate with two protrusions disposed above the substrate is
provided. Each protrusion has a first side wall and a second side
wall opposite to the first side wall. A mask layer is conformally
formed on the substrate and the protrusions. The mask layer is then
tilt-implanted with a first angle using a first implanting mask
adjacent to the first side wall of the protrusions. The mask layer
is then tilt-implanted again with a second angle using a second
implanting mask adjacent to the second side wall of the
protrusions. Implanted portions of the mask layer are removed to
form a patterned mask layer. The substrate is etched using the
patterned mask layer to form a recess.
[0007] A detailed description is given in the following embodiments
with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The present invention can be more fully understood by
reading the subsequent detailed description and examples with
references made to the accompanying drawings, wherein:
[0009] FIG. 1 is a top view of a conventional recess structure.
[0010] FIGS. 2A.about.2K are cross sections of the method for
forming a recess of the invention.
DETAILED DESCRIPTION
[0011] FIGS. 2A.about.2K illustrate cross sections of the method
for forming a recess according to the invention.
[0012] Referring to FIG. 2A, a substrate 100 with two trench
capacitor devices 102 protruding above the substrate 100 is
provided. The substrate 100 may comprise P-type, N-type, or epitaxy
silicon. The trench capacitor device 102 includes a protrusion
structure 104 such as a single side buried strap isolation
overlying a trench capacitor 106. Each protrusion structure 104 has
a first side wall 107 and a second side wall 107' opposite to the
first side wall 107. Also, a predetermined area 108 is defined
between the two trench capacitor devices 102.
[0013] Referring to FIG. 2B, a first mask layer 110 is conformally
formed on the substrate 100 and the trench capacitor devices 102.
The first mask layer 110 comprises silicon oxide, silicon nitride,
or silicon oxynitride, preferably silicon nitride. The second mask
layer 112 is then conformally formed on the first mask layer 110.
The second mask layer 112 is a material different from the first
mask layer 110 and is preferably a silicon oxide layer.
[0014] Referring to FIG. 2C, a first photoresist layer 114 is
formed over the substrate 100 and the trench capacitor devices 102.
The first photoresist layer 114 is then recessed to level with or
below top surfaces 116 of the trench capacitor devices 102, as
shown in FIG. 2D. The recess may be accomplished by plasma ashing,
such as O.sub.3 or O.sub.2 ashing.
[0015] Referring to FIG. 2E, the first photoresist layer 114 is
patterned to form a first implanting mask 118. The first implanting
mask 118 is adjacent to the first side wall 107 of the protrusion
structure 104, that is, on one side of the predetermined area
108.
[0016] Referring to FIG. 2F, a portion of the second mask layer 112
is tilt-implanted 120 at a first angle with, such as BF.sub.2,
using the first implanting mask 118. A first implanted portion 126a
is formed above a predetermined recess area. The first implanted
portion 126a is used to define a part of the recess location, which
can be preciously controlled by the height of the protrusion
structure 104 and the tilt-implanted angle.
[0017] Another tilt-implanting process is performed. A second
photoresist layer 122 is formed over the substrate 100 and the
trench capacitor devices 102 and recessed to level with or below
top surfaces 116 of the trench capacitor devices 102 by the similar
processes, as shown in FIGS. 2C and 2D.
[0018] Referring to FIG. 2G, the second photoresist layer 122 is
patterned to form a second implanting mask 124. The second
implanting mask 124 is adjacent to the second side wall 107' of the
protrusion structure 104, that is, on the other side of the
predetermined area 108. Next, another portion of the second mask
layer 112 is tilt-implanted 121 again at a second angle with, such
as BF.sub.2, using the second implanting mask 124. Thus, a second
implanted portion 126b is formed. The first and second implanted
portions 126a and 126b define the location of the recess to be
formed. The first and second implanting angles are different, for
example, the second implanting angle toward a buried strap 105 is
larger than the first implanting angle. As such, a larger contact
area can be formed in one side of the predetermined area 108 during
the subsequent process.
[0019] Referring to FIG. 2H, after removing the second implanting
mask 124, the implanted portion 126 of the second mask layer 112
between the two trench capacitor devices 102 is exposed. All of the
implanted portions of the second mask layer 112 are then removed,
exposing the first mask layer 110 overlying the predetermined
recess area, as shown in FIG. 2I.
[0020] The first mask layer 110 uncovered by non-implanted second
mask layer 112 is then removed to form a patterned mask layer,
exposing a substrate area 128, as shown in FIG. 2J.
[0021] Referring to FIG. 2K, the exposed substrate area 128 is then
etched using the patterned mask layer 112 between the two trench
capacitor devices 102 to form a recess 130 nearby the buried strap
105 in the predetermined area 108. The predetermined area 108 is
divided into two different regions by the recess 130, such as a
larger first region 142 and a smaller second region 144, so that
distances from the recess 130 to the two trench capacitor devices
102, respectively, are different.
[0022] A gate oxide 132 and a recessed gate 134 are finally formed
in the recess 130 and source/drain 136/138 is formed in the
predetermined area 108 using methods known in the art. A contact
148 may further be formed within the larger one of the two regions
(142 and 144), such as the first region 142, through a dielectric
layer 146, enlarging the contact slit width.
[0023] The invention provides a precious self alignment method for
forming a recessed gate between deep trenches by tilt-implanting
with different angles using a photoresist layer as an implanting
mask. Also, the non balance recess position can substantially
enlarge the contact slit margin, avoiding contact failure.
[0024] Although the above embodiment is illustrated by a process
for forming a recess in a memory cell, the invention is not limited
thereto. One skilled in the art can appreciate that the invention
may apply to any devices requiring a precise opening.
[0025] While the invention has been described by way of example and
in terms of preferred embodiment, it is to be understood that the
invention is not limited thereto. To the contrary, it is intended
to cover various modifications and similar arrangements (as would
be apparent to those skilled in the art). Therefore, the scope of
the appended claims should be accorded the broadest interpretation
so as to encompass all such modifications and similar
arrangements.
* * * * *