U.S. patent application number 11/483964 was filed with the patent office on 2007-01-25 for light emitting device methods.
This patent application is currently assigned to Luminus Devices, Inc.. Invention is credited to Michael Gregory Brown, Scott W. Duncan, Alexei A. Erchak, John W. Graff, Milan Singh Minsky.
Application Number | 20070020790 11/483964 |
Document ID | / |
Family ID | 33304302 |
Filed Date | 2007-01-25 |
United States Patent
Application |
20070020790 |
Kind Code |
A1 |
Erchak; Alexei A. ; et
al. |
January 25, 2007 |
Light emitting device methods
Abstract
Light-emitting device methods are disclosed.
Inventors: |
Erchak; Alexei A.;
(Cambridge, MA) ; Graff; John W.; (Swampscott,
MA) ; Brown; Michael Gregory; (Tyngsboro, MA)
; Duncan; Scott W.; (Andover, MA) ; Minsky; Milan
Singh; (Newton, MA) |
Correspondence
Address: |
WOLF GREENFIELD & SACKS, PC
FEDERAL RESERVE PLAZA
600 ATLANTIC AVENUE
BOSTON
MA
02210-2206
US
|
Assignee: |
Luminus Devices, Inc.
Woburn
MA
|
Family ID: |
33304302 |
Appl. No.: |
11/483964 |
Filed: |
July 10, 2006 |
Related U.S. Patent Documents
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Application
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Filing Date |
Patent Number |
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10794452 |
Mar 5, 2004 |
7074631 |
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11483964 |
Jul 10, 2006 |
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10723987 |
Nov 26, 2003 |
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11483964 |
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10724004 |
Nov 26, 2003 |
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11483964 |
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10724033 |
Nov 26, 2003 |
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10724006 |
Nov 26, 2003 |
7084434 |
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11483964 |
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10724029 |
Nov 26, 2003 |
7098589 |
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10724015 |
Nov 26, 2003 |
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10724005 |
Nov 26, 2003 |
7083993 |
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10735498 |
Dec 12, 2003 |
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60462889 |
Apr 15, 2003 |
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60474199 |
May 29, 2003 |
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60475682 |
Jun 4, 2003 |
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60503653 |
Sep 17, 2003 |
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60503654 |
Sep 17, 2003 |
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60513807 |
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60514764 |
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Current U.S.
Class: |
438/22 ;
257/E33.068; 438/28 |
Current CPC
Class: |
H01L 33/20 20130101;
Y10S 438/956 20130101; Y10S 438/95 20130101; H01L 33/0093 20200501;
H01L 2933/0083 20130101 |
Class at
Publication: |
438/022 ;
438/028 |
International
Class: |
H01L 21/00 20060101
H01L021/00 |
Claims
1. A method of making a light-emitting device, the method
comprising: disposing a planarization layer on a surface of a layer
of semiconductor material; disposing a lithography layer on a
surface of the planarization layer; and performing nanolithography
to remove at least a portion of the planarization layer, at least a
portion of the lithography layer and at least a portion of the
layer of semiconductor material, thereby forming a dielectric
function in the surface of the layer of semiconductor material that
varies spatially according to a pattern.
2. The method of claim 1, wherein performing nanolithography
includes forming indentations in the lithography layer.
3. The method of claim 2, further comprising heating the
lithography layer while forming the indentations in the lithography
layer.
4. The method of claim 3, wherein the lithography layer is cooled
after forming the indentations.
5. The method of claim 2, further comprising UV-curing the
lithography layer while forming the indentations in the lithography
layer.
6. The method of claim 2, wherein the indentations from the
lithography layer correspond to the portion of the lithography
layer removed during nanolithography.
7. The method of claim 1, wherein the portion of the planarization
layer removed during nanolithography corresponds to the portion of
the lithography layer removed during nanolithography.
8. The method of claim 7, wherein the portion of the layer of
semiconductor material removed during nanolithography corresponds
to the portion of the planarization layer removed during
nanolithography.
9. The method of claim 8, wherein the portion of the layer of
semiconductor material removed during nanolithography forms the
pattern in the surface of the layer of semiconductor material.
10. The method of claim 1, further comprising, after removing
portions of the lithography and planarization layers, depositing a
material on exposed portions of the layer of semiconductor
material.
11. The method of claim 10, further comprising depositing the
material on an exposed upper surface of the lithography layer.
12. The method of claim 11, further comprising removing the
portions of lithography layer having the material deposited
thereon.
13. The method of claim 12, further comprising removing the
portions of the planarization layer corresponding to the portions
of the lithography layer having the material deposited thereon.
14. The method of claim 12, further comprising removing portions of
the layer of semiconductor material that do not have the material
deposited thereon to form the pattern in the surface of the layer
of semiconductor material.
15. The method of claim 10, wherein the material comprises a
metal.
16. The method of claim 15, wherein the material comprises at least
one metal selected from the group consisting of aluminum, nickel,
titanium and tungsten.
17. The method of claim 1, wherein performing nanolithography
includes forming indentations in the lithography layer, and the
method further comprises coating at least some of the indentations
in the lithography layer with an etch resistant material.
18. The method of claim 17, wherein the etch resistant material is
disposed on the surface of the lithography layer, and the etch
resistant material is then etched to expose an upper surface of the
lithography layer while keeping some of the etch resistant material
in the indentations in the lithography layer.
19. The method of claim 18, wherein the etch resistant material is
spin coated onto the lithography layer.
20-60. (canceled)
61. A method of making a light-emitting device, the method
comprising: providing an article that comprises a layer of
semiconductor material, and a planarization layer supported by the
layer of semiconductor material; and performing nanolithography to
remove at least a portion of the planarization layer and at least a
portion of the layer of semiconductor material, thereby forming a
dielectric function in the surface of the layer of semiconductor
material that varies spatially according to a pattern.
62-106. (canceled)
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of Ser. No. 10/794,452,
filed Mar. 5, 2004 which claims priority under 35 U.S.C. .sctn.119
to the following U.S. Provisional Patent Applications: 60/462,889,
filed Apr. 15, 2003; 60/474,199, filed May 29, 2003; 60/475,682,
filed Jun. 4, 2003; 60/503,653, filed Sep. 17, 2003; 60/503,654
filed Sep. 17, 2003; 60/503,661, filed Sep. 17, 2003; 60/503,671,
filed Sep. 17, 2003; 60/503,672, filed Sep. 17, 2003; 60/513,807,
filed Oct. 23, 2003; and 60/514,764, filed Oct. 27, 2003. This
application also claims priority under 35 U.S.C. .sctn.120 to, and
is a continuation-in-part of, the following U.S. patent application
Ser. No. 10/723,987, entitled "Light Emitting Devices," and filed
Nov. 26, 2003; U.S. Ser. No. 10/724,004, entitled "Light Emitting
Devices," and filed Nov. 26, 2003; U.S. Ser. No. 10/724,033,
entitled "Light Emitting Devices," and filed Nov. 26, 2003; U.S.
Ser. No. 10/724,006, entitled "Light Emitting Devices," and filed
Nov. 26, 2003; U.S. Ser. No. 10/724,029, entitled "Light Emitting
Devices," and filed Nov. 26, 2003; U.S. Ser. No. 10/724,015,
entitled "Light Emitting Devices," and filed Nov. 26, 2003; U.S.
Ser. No. 10/724,005, entitled "Light Emitting Devices," and filed
Nov. 26, 2003; U.S. Ser. No. 10/735,498, entitled "Light Emitting
Devices," and filed Dec. 12, 2003. Each of these patent
applications is incorporated herein by reference.
TECHNICAL FIELD
[0002] The invention relates to light-emitting device methods.
BACKGROUND
[0003] A light emitting diode (LED) often can provide light in a
more efficient manner than an incandescent light source and/or a
fluorescent light source. The relatively high power efficiency
associated with LEDs has created an interest in using LEDs to
displace conventional light sources in a variety of lighting
applications. For example, in some instances LEDs are being used as
traffic lights and to illuminate cell phone keypads and
displays.
[0004] Typically, an LED is formed of multiple layers, with at
least some of the layers being formed of different materials. In
general, the materials and thicknesses selected for the layers
determine the wavelength(s) of light emitted by the LED. In
addition, the chemical composition of the layers can be selected to
try to isolate injected electrical charge carriers into regions
(commonly referred to as quantum wells) for relatively efficient
conversion to optical power. Generally, the layers on one side of
the junction where a quantum well is grown are doped with donor
atoms that result in high electron concentration (such layers are
commonly referred to as n-type layers), and the layers on the
opposite side are doped with acceptor atoms that result in a
relatively high hole concentration (such layers are commonly
referred to as p-type layers).
[0005] A common approach to preparing an LED is as follows. The
layers of material are prepared in the form of a wafer. Typically,
the layers are formed using an epitaxial deposition technique, such
as metal-organic chemical vapor deposition (MOCVD), with the
initially deposited layer being formed on a growth substrate. The
layers are then exposed to various etching and metallization
techniques to form contacts for electrical current injection, and
the wafer is subsequently sectioned into individual LED chips.
Usually, the LED chips are packaged.
[0006] During use, electrical energy is usually injected into an
LED and then converted into electromagnetic radiation (light), some
of which is extracted from the LED.
SUMMARY
[0007] The invention relates to light-emitting device methods.
[0008] In one aspect, the invention features a method of making a
light-emitting device. The method includes disposing a
planarization layer on a surface of a layer of semiconductor
material, and disposing a lithography layer on a surface of the
planarization layer. The method also includes performing
nanolithography to remove at least a portion of the planarization
layer, at least a portion of the lithography layer and at least a
portion of the layer of semiconductor material, thereby forming a
dielectric function in the surface of the layer of semiconductor
material that varies spatially according to a pattern.
[0009] In another aspect, the invention features a method of making
a light-emitting device. The method includes providing an article
that comprises a layer of semiconductor material and a
planarization layer supported by the layer of semiconductor
material. The method also includes performing nanolithography to
remove at least a portion of the planarization layer and at least a
portion of the layer of semiconductor material, thereby forming a
dielectric function in the surface of the layer of semiconductor
material that varies spatially according to a pattern.
[0010] Embodiments can feature one or more of the following
advantages.
[0011] In certain embodiments, a light-emitting system can include
an LED and/or a relatively large LED chip that can exhibit
relatively high light extraction.
[0012] In some embodiments, a light-emitting system can include an
LED and/or a relatively large LED chip that can exhibit relatively
high surface brightness, relatively high average surface
brightness, relatively low need for heat dissipation or relatively
high rate of heat dissipation, relatively low etendue and/or
relatively high power efficiency.
[0013] In certain embodiments, a light-emitting system can include
an LED and/or a relatively large LED chip that can be designed so
that relatively little light emitted by the LED/LED chip is
absorbed by packaging.
[0014] In some embodiments, a light-emitting system can include a
packaged LED (e.g., a relatively large packaged LED) that can be
prepared without using an encapsulant material. This can result in
a packaged LED that avoids certain problems associated with the use
of certain encapsulant materials, such as reduced performance
and/or inconsistent performance as a function of time, thereby
providing a packaged LED that can exhibit relatively good and/or
reliable performance over a relatively long period of time.
[0015] In certain embodiments, a light-emitting system can include
an LED (e.g., a packaged LED, which can be a relatively large
packaged LED) that can have a relatively uniform coating of a
phosphor material.
[0016] In some embodiments, a light-emitting system can include an
LED (e.g., a packaged LED, which can be a relatively large packaged
LED) that can be designed to provide a desired light output within
a particular angular range (e.g., within a particular angular range
relative to the LED surface normal).
[0017] In some embodiments, a light-emitting system can include an
LED and/or a relatively large LED chip that can be prepared by a
process that is relatively inexpensive.
[0018] In certain embodiments, a light-emitting system can include
an LED and/or a relatively large LED chip that can be prepared by a
process that can be conducted on a commercial scale without
incurring costs that render the process economically
unfeasible.
[0019] Features and advantages of the invention are in the
description, drawings and claims.
DESCRIPTION OF DRAWINGS
[0020] FIG. 1 is a schematic representation of a light emitting
system.
[0021] FIG. 2 is a side view of an LED with a patterned
surface.
[0022] FIG. 3 is a top view the patterned surface of the LED of
FIG. 2.
[0023] FIG. 4 is a graph of an extraction efficiency of an LED with
a patterned surface as function of a detuning parameter.
[0024] FIG. 5 is a schematic representation of the Fourier
transformation of a patterned surface of an LED.
[0025] FIG. 6 is a graph of an extraction efficiency of an LED with
a patterned surface as function of nearest neighbor distance.
[0026] FIG. 7 is a graph of an extraction efficiency of an LED with
a patterned surface as function of a filling factor.
[0027] FIG. 8 is a top view a patterned surface of an LED.
[0028] FIG. 9 is a graph of an extraction efficiency of LEDs with
different surface patterns.
[0029] FIG. 10 is a graph of an extraction efficiency of LEDs with
different surface patterns.
[0030] FIG. 11 is a graph of an extraction efficiency of LEDs with
different surface patterns.
[0031] FIG. 12 is a graph of an extraction efficiency of LEDs with
different surface patterns.
[0032] FIG. 13 is a schematic representation of the Fourier
transformation two LEDs having different patterned surfaces
compared with the radiation emission spectrum of the LEDs.
[0033] FIG. 14 is a graph of an extraction efficiency of LEDs
having different surface patterns as a function of angle.
[0034] FIG. 15 is a side view of an LED with a patterned surface
and a phosphor layer on the patterned surface.
[0035] FIG. 16 is a cross-sectional view of a multi-layer
stack.
[0036] FIG. 17 is a cross-sectional view of a multi-layer
stack.
[0037] FIG. 18 is a cross-sectional view of a multi-layer
stack.
[0038] FIG. 19 is a cross-sectional view of a multi-layer
stack.
[0039] FIG. 20 depicts a side view of a substrate removal
process.
[0040] FIG. 21 is a partial cross-sectional view of a multi-layer
stack.
[0041] FIG. 22 is a partial cross-sectional view of a multi-layer
stack.
[0042] FIG. 23 is a partial cross-sectional view of a multi-layer
stack.
[0043] FIG. 24 is a partial cross-sectional view of a multi-layer
stack.
[0044] FIG. 25 is a partial cross-sectional view of a multi-layer
stack.
[0045] FIG. 26 is a partial cross-sectional view of a multi-layer
stack.
[0046] FIG. 27 is a partial cross-sectional view of a multi-layer
stack.
[0047] FIG. 28 is a partial cross-sectional view of a multi-layer
stack.
[0048] FIG. 29 is a partial cross-sectional view of a multi-layer
stack.
[0049] FIG. 30 is a partial cross-sectional view of a multi-layer
stack.
[0050] FIG. 31 is a partial cross-sectional view of a multi-layer
stack.
[0051] FIG. 32 is a partial cross-sectional view of a multi-layer
stack.
[0052] FIG. 33 is a partial cross-sectional view of a multi-layer
stack.
[0053] FIG. 34 is a partial cross-sectional view of a multi-layer
stack.
[0054] Like reference symbols in the various drawings indicate like
elements.
DETAILED DESCRIPTION
[0055] FIG. 1 is a schematic representation of a light-emitting
system 50 that has an array 60 of LEDs 100 incorporated therein.
Array 60 is configured so that, during use, light that emerges from
LEDs 100 (see discussion below) emerges from system 50 via surface
55.
[0056] Examples of light-emitting systems include projectors (e.g.,
rear projection projectors, front projection projectors), portable
electronic devices (e.g., cell phones, personal digital assistants,
laptop computers), computer monitors, large area signage (e.g.,
highway signage), vehicle interior lighting (e.g., dashboard
lighting), vehicle exterior lighting (e.g., vehicle headlights,
including color changeable headlights), general lighting (e.g.,
office overhead lighting), high brightness lighting (e.g.,
streetlights), camera flashes, medical devices (e.g., endoscopes),
telecommunications (e.g. plastic fibers for short range data
transfer), security sensing (e.g. biometrics), integrated
optoelectronics (e.g., intrachip and interchip optical
interconnects and optical clocking), military field communications
(e.g., point to point communications), biosensing (e.g.
photo-detection of organic or inorganic substances), photodynamic
therapy (e.g. skin treatment), night-vision goggles, solar powered
transit lighting, emergency lighting, airport runway lighting,
airline lighting, surgical goggles, wearable light sources (e.g.
life-vests). An example of a rear projection projector is a rear
projector television. An example of a front projection projector is
a projector for displaying on a surface, such as a screen or a
wall. In some embodiments, a laptop computer can include a front
projection projector.
[0057] Typically, surface 55 is formed of a material that transmits
at least about 20% (e.g., at least about 30%, at least about 40%,
at least about 50%, at least about 60%, at least about 70%, at
least about 80%, at least about 90%, at least about 95%) of the
light that emerges from LEDs 100 and impinges on surface 55.
Examples of materials from which surface 55 can be formed include
glass, silica, quartz, plastic and polymers.
[0058] In some embodiments, it may be desirable for the light that
emerges (e.g., total light intensity, light intensity as a function
of wavelength, and/or peak emission wavelength) from each LED 100
to be substantially the same. An example is time-sequencing of
substantially monochromatic sources (e.g. LEDs) in display
applications (e.g., to achieve vibrant full-color displays).
Another example is in telecommunications where it can be
advantageous for an optical system to have a particular wavelength
of light travel from the source to the light guide, and from the
light guide to the detector. A further example is vehicle lighting
where color indicates signaling. An additional example is in
medical applications (e.g., photosensitive drug activation or
biosensing applications, where wavelength or color response can be
advantageous).
[0059] In certain embodiments, it may be desirable for the light
that emerges (e.g., total light intensity, light intensity as a
function of wavelength, and/or peak emission wavelength) from at
least some of LEDs 100 to be different from the light that emerges
(e.g., total light intensity, light intensity as a function of
wavelength, and/or peak emission wavelength) from different LEDs
100. An example is in general lighting (e.g., where multiple
wavelengths can improve the color rendering index (CRI)). CRI is a
measurement of the amount of color shift that objects undergo when
lighted by the light-emitting system as compared with the color of
those same objects when seen under a reference lighting system
(e.g., daylight) of comparable correlated temperature. Another
example is in camera flashes (e.g., where substantially high CRI,
such as substantially close to the CRI of noontime sunlight, is
desirable for a realistic rendering of the object or subject being
photographed). A further example is in medical devices (e.g., where
substantially consistent CRI is advantageous for tissue, organ,
fluid, etc. differentiation and/or identification). An additional
example is in backlighting displays (e.g., where certain CRI white
light is often more pleasing or natural to the human eye).
[0060] Although depicted in FIG. 1 as being in the form of an
array, LEDs 100 can be configured differently. As an example, in
some embodiments, system 50 includes a single LED 100. As another
example, in certain embodiments, the array is curved to help
angularly direct the light from various sources onto the same point
(e.g., an optic such as a lens). As a further example, in some
embodiments, the array of devices is hexagonally distributed to
allow for close-packing and high effective surface brightness. As
an additional example, in certain embodiments, the devices are
distributed around a mirror (e.g., a dichroic mirror) that combines
or reflects light from the LEDs in the array.
[0061] In FIG. 1 the light that emerges from LEDs 100 is shown as
traveling directly from LEDs 100 to surface 55. However, in some
embodiments, the light that emerges from LEDs 100 can travel an
indirect path from LEDs 100 to surface 55. As an example, in some
embodiments, system 50 includes a single LED 100. As another
example, in certain embodiments, light from LEDs 100 is focused
onto a microdisplay (e.g., onto a light valve such as a digital
light processor (DLP) or a liquid crystal display (LCD)). As a
further example, in some embodiments, light is directed through
various optics, mirrors or polarizers (e.g., for an LCD). As an
additional example, in certain embodiments, light is projected
through primary or secondary optics, such as, for example, a lens
or a set of lenses.
[0062] FIG. 2 shows a side view of an LED 100 in the form of a
packaged die. LED 100 includes a multi-layer stack 122 disposed on
a submount 120. Multi-layer stack 122 includes a 320 nm thick
silicon doped (n-doped) GaN layer 134 having a pattern of openings
150 in its upper surface 110. Multi-layer stack 122 also includes a
bonding layer 124, a 100 nm thick silver layer 126, a 40 nm thick
magnesium doped (p-doped) GaN layer 128, a 120 nm thick
light-generating region 130 formed of multiple InGaN/GaN quantum
wells, and a AlGaN layer 132. An n-side contact pad 136 is disposed
on layer 134, and a p-side contact pad 138 is disposed on layer
126. An encapsulant material (epoxy having an index of refraction
of 1.5) 144 is present between layer 134 and a cover slip 140 and
supports 142. Layer 144 does not extend into openings 150.
[0063] Light is generated by LED 100 as follows. P-side contact pad
138 is held at a positive potential relative to n-side contact pad
136, which causes electrical current to be injected into LED 100.
As the electrical current passes through light-generating region
130, electrons from n-doped layer 134 combine in region 130 with
holes from p-doped layer 128, which causes region 130 to generate
light. Light-generating region 130 contains a multitude of point
dipole radiation sources that emit light (e.g., isotropically)
within the region 130 with a spectrum of wavelengths characteristic
of the material from which light-generating region 130 is formed.
For InGaN/GaN quantum wells, the spectrum of wavelengths of light
generated by region 130 can have a peak wavelength of about 445
nanometers (nm) and a full width at half maximum (FWHM) of about 30
nm.
[0064] It is to be noted that the charge carriers in p-doped layer
126 have relatively low mobility compared to the charge carriers in
the n-doped semiconductor layer 134. As a result, placing silver
layer 126 (which is conductive) along the surface of p-doped layer
128 can enhance the uniformity of charge injection from contact pad
138 into p-doped layer 128 and light-generating region 130. This
can also reduce the electrical resistance of device 100 and/or
increase the injection efficiency of device 100. Because of the
relatively high charge carrier mobility of the n-doped layer 134,
electrons can spread relatively quickly from n-side contact pad 136
throughout layers 132 and 134, so that the current density within
the light-generating region 130 is substantially uniform across the
region 130. It is also to be noted that silver layer 126 has
relatively high thermal conductivity, allowing layer 126 to act as
a heat sink for LED 100 (to transfer heat vertically from the
multi-layer stack 122 to submount 120).
[0065] At least some of the light that is generated by region 130
is directed toward silver layer 126. This light can be reflected by
layer 126 and emerge from LED 100 via surface 110, or can be
reflected by layer 126 and then absorbed within the semiconductor
material in LED 100 to produce an electron-hole pair that can
combine in region 130, causing region 130 to generate light.
Similarly, at least some of the light that is generated by region
130 is directed toward pad 136. The underside of pad 136 is formed
of a material (e.g., a Ti/Al/Ni/Au alloy) that can reflect at least
some of the light generated by light-generating region 130.
Accordingly, the light that is directed to pad 136 can be reflected
by pad 136 and subsequently emerge from LED 100 via surface 110
(e.g., by being reflected from silver layer 126), or the light that
is directed to pad 136 can be reflected by pad 136 and then
absorbed within the semiconductor material in LED 100 to produce an
electron-hole pair that can combine in region 130, causing region
130 to generate light (e.g., with or without being reflected by
silver layer 126).
[0066] As shown in FIGS. 2 and 3, surface 110 of LED 100 is not
flat but consists of a modified triangular pattern of openings 150.
In general, various values can be selected for the depth of
openings 150, the diameter of openings 150 and the spacing between
nearest neighbors in openings 150 can vary. Unless otherwise noted,
for purposes of the figures below showing the results of numerical
calculations, openings 150 have a depth 146 equal to about 280 nm,
a non-zero diameter of about 160 nm, a spacing between nearest
neighbors or about 220 nm, and an index of refraction equal to 1.0.
The triangular pattern is detuned so that the nearest neighbors in
pattern 150 have a center-to-center distance with a value between
(a-.DELTA.a) and (a+.DELTA.a), where "a" is the lattice constant
for an ideal triangular pattern and ".DELTA.a" is a detuning
parameter with dimensions of length and where the detuning can
occur in random directions. To enhance light extraction from LED
100 (see discussion below), detuning parameter, .DELTA.a, is
generally at least about one percent (e.g., at least about two
percent, at least about three percent, at least about four percent,
at least about five percent) of ideal lattice constant, a, and/or
at most about 25% (e.g., at most about 20%, at most about 15%, at
most about 10%) of ideal lattice constant, a. In some embodiments,
the nearest neighbor spacings vary substantially randomly between
(a-.DELTA.a) and (a+.DELTA.a), such that pattern 150 is
substantially randomly detuned.
[0067] For the modified triangular pattern of openings 150, it has
been found that a non-zero detuning parameter enhances the
extraction efficiency of an LED 100. For LED 100 described above,
as the detuning parameter .DELTA.a increases from zero to about
0.15 a, numerical modeling (described below) of the electromagnetic
fields in the LED 100 has shown that the extraction efficiency of
the device increases from about 0.60 to about 0.70, as shown in
FIG. 4.
[0068] The extraction efficiency data shown in FIG. 4 are
calculated by using a three-dimensional finite-difference
time-domain (FDTD) method to approximate solutions to Maxwell's
equations for the light within and outside of LED 100. See, for
example, K. S. Kunz and R. J. Luebbers, The Finite-Difference
Time-Domain Methods (CRC, Boca Raton, Fla., 1993); A. Taflove,
Computational Electrodynamics: The Finite-Difference Time-Domain
Method (Artech House, London, 1995), both of which are hereby
incorporated by reference. To represent the optical behavior of LED
100 with a particular pattern 150, input parameters in a FDTD
calculation include the center frequency and bandwidth of the light
emitted by the point dipole radiation sources in light-generating
region 130, the dimensions and dielectric properties of the layers
within multilayer stack 122, and the diameters, depths, and nearest
neighbor distances (NND) between openings in pattern 150.
[0069] In certain embodiments, extraction efficiency data for LED
100 are calculated using an FDTD method as follows. The FDTD method
is used to solve the full-vector time-dependent Maxwell's
equations: .gradient. .fwdarw. .times. .times. E .fwdarw. = - .mu.
.times. .differential. H .fwdarw. .differential. t , .times.
.gradient. .fwdarw. .times. .times. H .fwdarw. = .infin. .times.
.differential. E .fwdarw. .differential. t + .differential. P
.fwdarw. .differential. t , ##EQU1## where the polarizability
{right arrow over (P)}={right arrow over (P)}.sub.1+{right arrow
over (P)}.sub.2+ . . . +{right arrow over (P)}.sub.m captures the
frequency-dependent response of the quantum well light-generating
region 130, the p-contact layer 126 and other layers within LED
100. The individual {right arrow over (P)}.sub.m terms are
empirically derived values of different contributions to the
overall polarizability of a material (e.g., the polarization
response for bound electron oscillations, the polarization response
for free electron oscillations). In particular, d 2 .times. P
.fwdarw. m d t 2 + .gamma. m .times. d P .fwdarw. m d t + .omega. m
2 .times. P .fwdarw. m = .function. ( .omega. ) .times. E .fwdarw.
, ##EQU2## where the polarization corresponds to a dielectric
constant .function. ( .omega. ) = .infin. + m .times. s m .omega. m
2 - .omega. 2 - I .times. .times. .gamma. m .times. .omega. .
##EQU3##
[0070] For purposes of the numerical calculations, the only layers
that are considered are encapsulant 144, silver layer 126 and
layers between encapsulant 144 and silver layer 126. This
approximation is based on the assumption that encapsulant 144 and
layer 126 are thick enough so that surrounding layers do not
influence the optical performance of LED 100. The relevant
structures within LED 100 that are assumed to have a frequency
dependent dielectric constant are silver layer 126 and
light-generating region 130. The other relevant layers within LED
100 are assumed to not have frequency dependent dielectric
constants. It is to be noted that in embodiments in which LED 100
includes additional metal layers between encapsulant 144 and silver
layer 126, each of the additional metal layers will have a
corresponding frequency dependent dielectric constant. It is also
to be noted that silver layer 126 (and any other metal layer in LED
100) has a frequency dependent term for both bound electrons and
free electrons, whereas light-generating region 130 has a frequency
dependent term for bound electrons but does not have a frequency
dependent term for free electrons. In certain embodiments, other
terms can be included when modeling the frequency dependence of the
dielectric constant. Such terms may include, for example,
electron-phonon interactions, atomic polarizations, ionic
polarizations and/or molecular polarizations.
[0071] The emission of light from the quantum well region of
light-generating region 130 is modeled by incorporating a number of
randomly-placed, constant-current dipole sources within the
light-generating region 130, each emitting short Gaussian pulses of
spectral width equal to that of the actual quantum well, each with
random initial phase and start-time.
[0072] To cope with the pattern of openings 150 in surface 110 of
the LED 100, a large supercell in the lateral direction is used,
along with periodic boundary conditions. This can assist in
simulating relatively large (e.g., greater than 0.01 mm on edge)
device sizes. The full evolution equations are solved in time, long
after all dipole sources have emitted their energy, until no energy
remains in the system. During the simulation, the total energy
emitted, the energy flux extracted through top surface 110, and the
energy absorbed by the quantum wells and the n-doped layer is
monitored. Through Fourier transforms both in time and space,
frequency and angle resolved data of the extracted flux are
obtained, and therefore an angle- and frequency-resolved extraction
efficiency can be calculated. By matching the total energy emitted
with the experimentally known luminescence of light-generating
region 130, absolute angle-resolved extraction in lumens/per solid
angle/per chip area for given electrical input is obtained.
[0073] Without wishing to be bound by theory, it is believed that
the detuned pattern 150 can enhance the efficiency with which light
generated in region 130 emerges from LED 100 via surface 110
because openings 150 create a dielectric function that varies
spatially in layer 134 according to pattern 150. It is believed
that this alters the density of radiation modes (i.e., light modes
that emerge from surface 110) and guided modes (i.e., light modes
that are confined within multi-layer stack 122) within LED 100, and
that this alteration to the density of radiation modes and guided
modes within LED 100 results in some light that would otherwise be
emitted into guided modes in the absence of pattern 150 being
scattered (e.g., Bragg scattered) into modes that can leak into
radiation modes. In certain embodiments, it is believed that
pattern 150 (e.g., the pattern discussed above, or one of the
patterns discussed below) can eliminate all of the guided modes
within LED 100.
[0074] It is believed that the effect of detuning of the lattice
can be understood by considering Bragg scattering off of a crystal
having point scattering sites. For a perfect lattice arranged in
lattice planes separated by a distance d, monochromatic light of
wavelength .lamda. is scattered through an angle .theta. according
to the Bragg condition, n.lamda.=2d sin .theta., where n is an
integer that gives the order of the scattering. However, it is
believed that for a light source having a spectral bandwidth
.DELTA..lamda./.lamda. and emitting into a solid angle
.DELTA..THETA., the Bragg condition can be relaxed by detuning the
spacing of between lattice sites by a detuning parameter .DELTA.a.
It is believed that detuning the lattice increases the scattering
effectiveness and angular acceptance of the pattern over the
spectral bandwidth and spatial emission profile of the source.
[0075] While a modified triangular pattern 150 having a non-zero
detuning parameter .DELTA.a has been described that can enhance
light extraction from LED 100, other patterns can also be used to
enhance light extraction from LED 100. When determining whether a
given pattern enhances light extraction from LED 100 and/or what
pattern of openings may be used to enhance light extraction from
LED 100, physical insight may first be used to approximate a basic
pattern that can enhance light extraction before conducting such
numerical calculations.
[0076] The extraction efficiency of LED 100 can be further
understood (e.g., in the weak scattering regime) by considering the
Fourier transform of the dielectric function that varies spatially
according to pattern 150. FIG. 5 depicts the Fourier transform for
an ideal triangular lattice. Extraction of light into a particular
direction with in-plane wavevector k is related to the source
emission S.sub.k' into all those modes with in-plane wavevector k'
(i.e. parallel to pattern 150) that are compatible to k by the
addition or subtraction of a reciprocal lattice vector G, i.e
k=k'.+-.G. The extraction efficiency is proportional to the
magnitude of the corresponding Fourier component (F.sub.k) of the
dielectric function .epsilon..sub.G given by F k .fwdarw. = c k
.fwdarw. .times. G -> .times. G .fwdarw. .times. S k .fwdarw. -
G .fwdarw. , .times. G .fwdarw. = .intg. .function. ( r .fwdarw. )
.times. e - I .times. .times. G .fwdarw. .times. r .fwdarw. .times.
d r .fwdarw. ##EQU4##
[0077] Since light propagating in the material generally satisfies
the equation
k.sup.2(in-plane)+k.sup.2(normal)=.epsilon.(.omega./c).sup.2, the
maximum G to be considered is fixed by the frequency (.omega.)
emitted by the light-generating region and the dielectric constant
of the light-generating region. As shown in FIG. 5, this defines a
ring in reciprocal space which is often called the light line. The
light line will be an annulus due to the finite bandwidth of the
light-generating region but for sake of clarity we illustrate the
light line of a monochromatic source. Similarly, light propagating
within the encapsulant is bounded by a light line (the inner circle
in FIG. 5). Therefore, the extraction efficiency is improved by
increasing F.sub.k for all directions k that lie within the
encapsulant light-line which amounts to increasing the number of G
points within the encapsulant light line and increasing the
scattering strength .epsilon..sub.G for G points which lie within
the material light line. This physical insight can be used when
selecting patterns that can improve extraction efficiency.
[0078] As an example, FIG. 6 shows the effect of increasing lattice
constant for an ideal triangular pattern. The data shown in FIG. 6
are calculated using the parameters given for LED 100 shown in FIG.
2, except that the emitted light has a peak wavelength of 450 nm,
and the depth of the holes, the diameter of the holes, and the
thickness of the n-doped layer 134 scale with the nearest neighbor
distance, a, as 1.27 a, 0.72 a, and 1.27 a+40 nm, respectively.
Increasing the lattice constant, increases the density of G points
within the light-line of the encapsulant. A clear trend in
extraction efficiency with NND is observed. It is believed that the
maximum extraction efficiency occurs for NND approximately equal to
the wavelength of light in vacuum. The reason a maximum is
achieved, is that as the NND becomes much larger than the
wavelength of light, the scattering effect is reduced because the
material becomes more uniform.
[0079] As another example, FIG. 7 shows the effect of increasing
hole size or filling factor. The filling factor for a triangular
pattern is given by (2.pi./ 3)*(r/a).sup.2, where r is the radius
of a hole. The data shown in FIG. 7 are calculated using the
parameters given for the LED 100 shown in FIG. 2, except that the
diameter of the openings is changed according the filling factor
value given on the x-axis of the graph. The extraction efficiency
increases with filling factor as the scattering strengths
(.epsilon..sub.G) increase. A maximum is observed for this
particular system at a filling factor of .about.48%. In certain
embodiments, LED 100 has a filling factor of at least about 10%
(e.g., at least about 15%, at least about 20%) and/or at most about
90% (e.g., at most about 80%, at most about 70%, at most about
60%).
[0080] While a modified triangular pattern has been described in
which a detuning parameter relates to positioning of openings in
the pattern from the positions in an ideal triangular lattice, a
modified (detuned) triangular pattern may also be achieved by
modifying the holes in an ideal triangular pattern while keeping
the centers at the positions for an ideal triangular pattern. FIG.
8 shows an embodiment of such a pattern. The enhancement in light
extraction, the methodology for conducting the corresponding
numerical calculation, and the physical explanation of the enhanced
light extraction for a light-emitting device having the pattern
shown in FIG. 8 is generally the same as described above. In some
embodiments, a modified (detuned) pattern can have openings that
are displaced from the ideal locations and openings at the ideal
locations but with varying diameters.
[0081] In other embodiments, enhanced light extraction from a
light-emitting device can be achieved by using different types of
patterns, including, for example, complex periodic patterns and
nonperiodic patterns. As referred to herein, a complex periodic
pattern is a pattern that has more than one feature in each unit
cell that repeats in a periodic fashion. Examples of complex
periodic patterns include honeycomb patterns, honeycomb base
patterns, (2.times.2) base patterns, ring patterns, and Archimidean
patterns. As discussed below, in some embodiments, a complex
periodic pattern can have certain openings with one diameter and
other openings with a smaller diameter. As referred to herein, a
nonperiodic pattern is a pattern that has no translational symmetry
over a unit cell that has a length that is at least 50 times the
peak wavelength of light generated by region 130. Examples of
nonperiodic patterns include aperiodic patterns, quasicrystalline
patterns, Robinson patterns, and Amman patterns.
[0082] FIG. 9 shows numerical calculations for LED 100 for two
different complex periodic patterns in which certain openings in
the patterns have a particular diameter, and other openings in the
patterns have smaller diameters. The numerical calculations
represented in FIG. 9 show the behavior of the extraction
efficiency (larger holes with a diameter of 80 nm) as the diameter
of the smaller holes (dR) is varied from zero nm to 95 nm. The data
shown in FIG. 7 are calculated using the parameters given for the
LED 100 shown in FIG. 2 except that the diameter of the openings is
changed according the filling factor value given on the x-axis of
the graph. Without wishing to be bound by theory, multiple hole
sizes allow scattering from multiple periodicities within the
pattern, therefore increasing the angular acceptance and spectral
effectiveness of the pattern. The enhancement in light extraction,
the methodology for conducting the corresponding numerical
calculation, and the physical explanation of the enhanced light
extraction for a light-emitting device having the pattern shown in
FIG. 9 is generally the same as described above.
[0083] FIG. 20 hows numerical calculations for LED 100 having
different ring patterns (complex periodic patterns). The number of
holes in the first ring surrounding the central hole is different
(six, eight or 10) for the different ring patterns. The data shown
in FIG. 10 are calculated using the parameters given for the LED
100 shown in FIG. 2, except that the emitted light has a peak
wavelength of 450 nm. The numerical calculations represented in
FIG. 10 show the extraction efficiency of LED 100 as the number of
ring patterns per unit cell that is repeated across a unit cell is
varied from two to four. The enhancement in light extraction, the
methodology for conducting the corresponding numerical calculation,
and the physical explanation of the enhanced light extraction for a
light-emitting device having the pattern shown in FIG. 10 is
generally the same as described above.
[0084] FIG. 11 shows numerical calculations for LED 100 having an
Archimidean pattern. The Archimedean pattern A7 consists of
hexagonal unit cells 230 of 7 equally-spaced holes with a nearest
neighbor distance of a. Within a unit cell 230, six holes are
arranged in the shape of a regular hexagon and the seventh hole is
located at the center of the hexagon. The hexagonal unit cells 230
then fit together along their edges with a center-to-center spacing
between the unit cells of a'=a*(1+ {square root over (3)}) to
pattern the entire surface of the LED. This is known as an A7
tiling, because 7 holes make up the unit cell. Similarly, the
Archimidean tiling A19 consists of 19 equally-spaced holes with a
NND of a. The holes are arranged in the form of an inner hexagon of
seven holes, and outer hexagon of 12 holes, and a central hole
within the inner hexagon. The hexagonal unit cells 230 then fit
together along their edges with a center-to-center spacing between
the unit cells of a'=a*(3+ {square root over (3)}) to pattern the
entire surface of the LED. The enhancement in light extraction, the
methodology for conducting the corresponding numerical calculation,
and the physical explanation of the enhanced light extraction for a
light-emitting device having the pattern shown in FIG. 11 is
generally the same as described above. As shown in FIG. 11 the
extraction efficiency for A7 and A19 is about 77%. The data shown
in FIG. 11 are calculated using the parameters given for the LED
100 shown in FIG. 2, except that the emitted light has a peak
wavelength of 450 and except that the NND is defined as the
distance between openings within an individual cell.
[0085] FIG. 12 shows numerical calculation data for LED 100 having
a quasicrystalline pattern. Quasicrystalline patterns are
described, for example, in M. Senechal, Quasicrystals and Geometry
(Cambridge University Press, Cambridge, England 1996), which is
hereby incorporated by reference. The numerical calculations show
the behavior of the extraction efficiency as the class of 8-fold
based quasi-periodic structure is varied. It is believed that
quasicrystalline patterns exhibit high extraction efficiency due to
high degree of in-plane rotational symmetries allowed by such
structures. The enhancement in light extraction, the methodology
for conducting the corresponding numerical calculation, and the
physical explanation of the enhanced light extraction for a
light-emitting device having the pattern shown in FIG. 12 is
generally the same as described above. Results from FDTD
calculations shown in FIG. 12 indicate that the extraction
efficiency of quasicrystalline structures reaches about 82%. The
data shown in FIG. 12 are calculated using the parameters given for
the LED 100 shown in FIG. 2, except that the emitted light has a
peak wavelength of 450 and except that the NND is defined as the
distance between openings within an individual cell.
[0086] While certain examples of patterns have been described
herein, it is believed that other patterns can also enhance the
light extraction from LED 100 if the patterns satisfy the basic
principles discussed above. For example, it is believed that adding
detuning to quasicrystalline or complex periodic structures can
increase extraction efficiency.
[0087] In some embodiments, at least about 45% (e.g., at least
about 50%, at least about 55%, at least about 60%, at least about
70%, at least about 80%, at least about 90%, at least about 95%) of
the total amount of light generated by light-generating region 130
that emerges from LED 100 emerges via surface 110.
[0088] In certain embodiments, the cross-sectional area of LED 100
can be relatively large, while still exhibiting efficient light
extraction from LED 100. For example, one or more edges of LED 100
can be at least about one millimeter (e.g., at least about 1.5
millimeters, at least about two millimeters, at least about 2.5
millimeters, at least about three millimeters), and at least about
45% (e.g., at least about 50%, at least about 55%, at least about
60%, at least about 70%, at least about 80%, at least about 90%, at
least about 95%) of the total amount of light generated by
light-generating region 130 that emerges from LED 100 emerges via
surface 110. This can allow for an LED to have a relatively large
cross-section (e.g., at least about one millimeter by at least
about one millimeter) while exhibiting good power conversion
efficiency.
[0089] In some embodiments, the extraction efficiency of an LED
having the design of LED 100 is substantially independent of the
length of the edge of the LED. For example, the difference between
the extraction efficiency of an LED having the design of LED 100
and one or more edges having a length of about 0.25 millimeter and
the extraction efficiency of LED having the design of LED 100 and
one or more edges having a length of one millimeter can vary by
less than about 10% (e.g., less than about 8%, less than about 5%,
less than about 3%). As referred to herein, the extraction
efficiency of an LED is the ratio of the light emitted by the LED
to the amount of light ls generated by the device (which can be
measured in terms of energy or photons). This can allow for an LED
to have a relatively large cross-section (e.g., at least about one
millimeter by at least about one millimeter) while exhibiting good
power conversion efficiency.
[0090] In certain embodiments, the quantum efficiency of an LED
having the design of LED 100 is substantially independent of the
length of the edge of the LED. For example, the difference between
the quantum efficiency of an LED having the design of LED 100 and
one or more edges having a length of about 0.25 millimeter and the
quantum efficiency of LED having the design of LED 100 and one or
more edges having a length of one millimeter can vary by less than
about 10% (e.g., less than about 8%, less than about 5%, less than
about 3%). As referred to herein, the quantum efficiency of an LED
is the ratio of the number of photons generated by the LED to the
number of electron-hole recombinations that occur in the LED. This
can allow for an LED to have a relatively large cross-section
(e.g., at least about one millimeter by at least about one
millimeter) while exhibiting good performance.
[0091] In some embodiments, the wall plug efficiency of an LED
having the design of LED 100 is substantially independent of the
length of the edge of the LED. For example, the difference between
the wall plug efficiency of an LED having the design of LED 100 and
one or more edges having a length of about 0.25 millimeter and the
wall plug efficiency of LED having the design of LED 100 and one or
more edges having a length of one millimeter can vary by less than
about 10% (e.g., less than about 8%, less than about 5%, less than
about 3%). As referred to herein, the wall plug efficiency of an
LED is the product of the injection efficiency of the LED (the
ratio of the numbers of carriers injected into the device to the
number of carriers that recombine in the light-generating region of
the device), the radiative efficiency of the LED (the ratio of
electron-hole recombinations that result in a radiative event to
the total number of electron-hole recombinations), and the
extraction efficiency of the LED (the ratio of photons that are
extracted from the LED to the total number of photons created).
This can allow for an LED to have a relatively large cross-section
(e.g., at least about one millimeter by at least about one
millimeter) while exhibiting good performance.
[0092] In some embodiments, it may be desirable to manipulate the
angular distribution of light that emerges from LED 100 via surface
110. To increase extraction efficiency into a given solid angle
(e.g., into a solid angle around the direction normal to surface
110) we examine the Fourier transform of the dielectric function
that varies spatially according to pattern 150 (as described
earlier). FIG. 13 shows the Fourier transform construction for two
ideal triangular lattices of different lattice constant. To
increase the extraction efficiency, we seek to increase the number
of G points within the encapsulant light line and scattering
strengths of G points (.epsilon..sub.G) within the material light
line. This would imply increasing the NND so as to achieve the
effect depicted in FIG. 6. However, here we are concerned with
increasing the extraction efficiency into a solid angle centered
around the normal direction. Therefore, we would also like to limit
the introduction of higher order G points by reducing the radius of
the encapsulant light line, such that the magnitude of
G>(.omega.(n.sub.e))/c. We can see that by decreasing the index
of refraction of the encapsulant (the bare minimum of which is
removing the encapsulant all together) we allow larger NND and
therefore increase the number of G points within the material light
line that are available to contribute to extraction in the normal
direction (F.sub.k=0) while simultaneously avoiding diffraction
into higher order (oblique angles) in the encapsulant. The above
described trends are depicted in FIG. 14 which shows extraction
efficiency into a solid angle (given by the collection half-angle
in the diagram). The data shown in FIG. 14 are calculated using the
parameters given for the LED 100 shown in FIG. 2, except that the
emitted light has a peak wavelength of 530 nm and a bandwidth of 34
nm, the index of refraction of the encapsulant was 1.0, the
thickness of the p-doped layer was 160 nm, the light generating
layer was 30 nm thick, the NND (a) for the three curves is shown on
FIG. 14, and the depth, hole diameter, and n-doped layer thickness
scaled with a, as 1.27 a, 0.72 a, and 1.27 a+40 nm, respectively.
As the lattice constant is increased, the extraction efficiency at
narrow angles increases as well as the overall extraction
efficiency into all angles. However, for even larger lattice
constant, diffraction into higher order modes in the encapsulant
limits the extraction efficiency at narrow angles even though the
overall extraction efficiency increases into all angles. For a
lattice constant of 460 nm, we calculate greater than 25%
extraction efficiency into a collection half-angle of 30.degree..
That is, about half of the extracted light is collected within only
about 13.4% of the upper hemisphere of solid angle demonstrating
the collimation effect of the pattern. It is believed that any
pattern that increases the number of G points within the material
light line while limiting the number of G points within the
encapsulant light line to only the G points at k=0 can improve the
extraction efficiency into a solid angle centered around the normal
direction.
[0093] The approach is especially applicable for reducing the
source etendue which is believed to often be proportional to
n.sup.2, where n is the index of refraction of the surrounding
material (e.g., the encapsulant). It is therefore believed that
reducing the index of refraction of the encapsulating layer for LED
100 can lead to more collimated emission, a lower source etendue,
and therefore to a higher surface brightness (here defined as the
total lumens extracted into the etendue of the source). In some
embodiments then, using an encapsulant of air will reduce the
source etendue while increasing extraction efficiency into a given
collection angle centered around the normal direction.
[0094] In certain embodiments, when light generated by region 130
emerges from LED 100 via surface 110, the distribution of light is
more collimated than a lambertian distribution. For example, in
some embodiments, when light generated by region 130 emerges from
LED 100 via surface 110, at least about 40% (e.g., at least about
50%, at least about 70%, at least about 90%) of the light emerging
via the surface of the dielectric layer emerges within at most
about 30.degree. (e.g., at most about 25.degree., at most about
20.degree., at most about 15.degree.) of an angle normal to surface
110.
[0095] The ability to extract a relatively high percentage of light
from a desired angle alone or coupled with a relatively high light
extraction can allow for a relatively high density of LEDs to be
prepared on a given wafer. For example, in some embodiments, a
wafer has at least about five LEDs (e.g., at least about 25 LEDs,
at least about 50 LEDs) per square centimeter.
[0096] In some embodiments, it may be desirable to modify the
wavelength(s) of light that emerge(s) from a packaged LED 100
relative to the wavelength(s) of light generated by
light-generating region 130. For example, as shown in FIG. 15, an
LED 300 having a layer containing a phosphor material 180 can be
disposed on surface 110. The phosphor material can interact with
light at the wavelength(s) generated by region 130 to provide light
at desired wavelength(s). In some embodiments, it may be desirable
for the light that emerges from packaged LED 100 to be
substantially white light. In such embodiments, the phosphor
material in layer 180 can be formed of, for example, a
(Y,Gd)(Al,Ga)G:Ce.sup.3+ or "YAG" (yttrium, aluminum, garnet)
phosphor. When pumped by blue light emitted from the
light-generating region 130, the phosphor material in layer 180 can
be activated and emit light (e.g., isotropically) with a broad
spectrum centered around yellow wavelengths. A viewer of the total
light spectrum emerging from packaged LED 100 sees the yellow
phosphor broad emission spectrum and the blue InGaN narrow emission
spectrum and typically mixes the two spectra to perceive white.
[0097] In certain embodiments, layer 180 can be substantially
uniformly disposed on surface 10. For example, the distance between
the top 151 of pattern 150 and the top 181 of layer 180 can vary by
less than about 20% (e.g., less than about 10%, less than about 5%,
less than about 2%) across surface 110.
[0098] In general, the thickness of layer 180 is small compared to
the cross-sectional dimensions of surface 130 of LED 100, which are
typically about one millimeter (mm) by one mm. Because layer 180 is
substantially uniformly deposited on surface 110, the phosphor
material in layer 180 can be substantially uniformly pumped by
light emerging via surface 110. The phosphor layer 180 is
relatively thin compared to the dimensions of the surface 110 of
the LED 100, such that light emitted by the light-generating region
130 is converted into lower wavelength light within the phosphor
layer 180 approximately uniformly over the entire surface 110 of
LED 100. Thus, the relatively thin, uniform phosphor layer 180
produces a uniform spectrum of white light emitted from the LED 100
as a function of position on surface 110.
[0099] In general, LED 100 can be fabricated as desired. Typically,
fabrication of LED 100 involves various deposition, laser
processing, lithography, and etching steps.
[0100] For example, FIG. 16 shows a LED wafer 500 containing an LED
layer stack of material deposited on a substrate (e.g., sapphire,
compound semiconductor, zinc oxide, silicon carbide, silicon) 502.
Such wafers are commercially available. Exemplary commercial
suppliers include Epistar Corporation, Arima Optoelectronics
Corporation and South Epitaxy Corporation. On substrate 502 are
disposed, consecutively, a buffer layer 504 (e.g., a
nitride-containing layer, such as a GaN layer, an AlN layer, an
AlGaN layer), an n-doped semiconductor layer (e.g., an n-doped
Si:GaN) layer 506, a current spreading layer 508 (e.g., an
AlGaN/GaN heterojunction or superlattice), a light-emitting region
510 (e.g., an InGaN/GaN multi-quantum well region), and a
semiconductor layer 512 (e.g., a p-doped Mg:GaN layer). Wafer 500
generally has a diameter of at least about two inches (e.g., from
about two inches to about 12 inches, from about two inches to about
six inches, from about two inches to about four inches, from about
two inches to about three inches).
[0101] FIG. 17 shows a multi-layer stack 550 including layers 502,
504, 506, 508, 510 and 512, as well as layers 520, 522, 524 and
526, which are generally formed of materials capable of being
pressure and/or heat bonded as described below. For example, layer
520 can be a nickel layer (e.g., electron-beam evaporated), layer
522 can be a silver layer (e.g., electron-beam evaporated), layer
524 can be a nickel layer (e.g., electron-beam evaporated), and
layer 526 can be a gold layer (e.g., electron-beam evaporated). In
some embodiments, layer 520 can be a relatively thin layer, and
layer 524 can be a relatively thick layer. Layer 524 can act, for
example, as diffusion barrier to reduce the diffusion of
contaminants (e.g., gold) into layers 520, 522 and/or 524 itself.
After deposition of layers 520, 522, 524 and 526, multi-layer stack
550 can be treated to achieve an ohmic contact. For example, stack
550 can be annealed (e.g., at a temperature of from about
400.degree. C. to about 600.degree. C.) for a period of time (e.g.,
from about 30 seconds to about 300 seconds) in an appropriate gas
environment (e.g., nitrogen, oxygen, air, forming gas).
[0102] FIG. 18 shows a multi-layer stack 600 that includes a
submount (e.g., germanium (such as polycrystalline germanium),
silicon (such as polycrystalline silicon), silicon-carbide, copper,
copper-tungsten, diamond, nickel-cobalt) 602 having layers 604,
606, 608 and 610 deposited thereon. Submount 602 can be formed, for
example, by sputtering or electroforming. Layer 604 is a contact
layer and can be formed, for example, from aluminum (e.g., electron
evaporated). Layer 606 is a diffusion barrier and can be formed,
for example, from Ni (e.g. electron evaporated). Layer 608 can be a
gold layer (e.g., electron-beam evaporated), and layer 610 can be a
AuSn bonding layer (e.g., thermal evaporated, sputtered) onto layer
608. After deposition of layers 604, 606, 608 and 610, multi-layer
stack 600 can be treated to achieve an ohmic contact. For example,
stack 600 can be annealed (e.g., at a temperature of from about
350.degree. C. to about 500.degree. C.) for a period of time (e.g.,
from about 30 seconds to about 300 seconds) in an appropriate gas
environment (e.g., nitrogen, oxygen, air, forming gas).
[0103] FIG. 19 shows a multi-layer stack 650 formed by bonding
together layers 526 and 610 (e.g., using a solder bond, using a
eutectic bond, using a peritectic bond). Layers 526 and 610 can be
bonded, for example, using thermal-mechanical pressing. As an
example, after contacting layers 526 and 610, multi-layer stack 650
can be put in a press and pressurized (e.g., using a pressure of up
to about 5 MPa, up to about 2 MPa) heated (e.g., to a temperature
of from about 200.degree. C. to about 400.degree. C.). Stack 650
can then be cooled (e.g., to room temperature) and removed from the
press.
[0104] Substrate 502 and buffer layer 504 are then at least
partially removed from stack 650. In general, this can be achieved
using any desired methods. For example, as shown in FIG. 20, in
some embodiments, substrate 502 is removed by exposing stack 650
(e.g., through surface 501 of substrate 502) to electromagnetic
radiation at an appropriate wavelength to partially decompose layer
504. It is believed that this results in local heating of layer
504, resulting in the partial decomposition of the material of
layer 504 adjacent the interface of layer 504 and substrate 502,
thereby allowing for the removal of substrate 502 from stack 650
(see discussion below). For example, in embodiments in which layer
504 is formed of gallium nitride, it is believed that constituents
including gallium and gaseous nitrogen are formed. In some
embodiments, stack 650 can be heated during exposure of surface 501
to the electromagnetic radiation (e.g., to reduce strain within
stack 650). Stack 650 can be heated, for example, by placing stack
650 on a hot plate and/or by exposing stack 650 to an additional
laser source (e.g. a CO.sub.2 laser). Heating stack 650 during
exposure of surface 501 to electromagnetic radiation can, for
example, reduce (e.g., prevent) liquid gallium from re-solidifying.
This can reduce the build up of strain within stack 650 which can
occur upon the re-solidification of the gallium
[0105] In certain embodiments, after exposure to the
electromagnetic radiation, residual gallium is present and keeps
substrate 502 bonded in stack 650. In such embodiments, stack 650
can be heated to above the melting temperature of gallium to allow
substrate 502 to be removed from the stack. In certain embodiments,
stack 650 may be exposed to an etchant (e.g., a chemical etchant,
such as HCl) to etch the residual gallium and remove substrate 502.
Other methods of removing the residual gallium (e.g., physical
methods) may also be used.
[0106] As an example, in certain embodiments, surface 501 is
exposed to laser radiation including the absorption wavelength of
layer 504 (e.g., about 248 nanometers, about 355 nanometers). Laser
radiation processes are disclosed, for example, in U.S. Pat. Nos.
6,420,242 and 6,071,795, which are hereby incorporated by
reference. The multi-layer stack is then heated to above the
melting point of gallium, at which point substrate 502 and buffer
layer 504 are removed from the stack by applying a lateral force to
substrate 502 (e.g., using a cotton swab).
[0107] In some embodiments, multiple portions of surface 501 are
simultaneously exposed to the electromagnetic radiation. In certain
embodiments, multiple portions of surface 501 are sequentially
exposed to electromagnetic radiation. Combinations of simultaneous
and sequential exposure can be used. Further, the electromagnetic
radiation can be exposed on surface 501 in the form of a pattern
(e.g., a serpentine pattern, a circular pattern, a spiral pattern,
a grid, a grating, a triangular pattern, an elementary pattern, a
random pattern, a complex pattern, a periodic pattern, a
nonperiodic pattern). In some embodiments, the electromagnetic
radiation can be rastered across one or more portions of surface
501. In certain embodiments, surface 501 is exposed to overlapping
fields of electromagnetic radiation.
[0108] In some embodiments, the electromagnetic radiation passes
through a mask before reaching surface 501. As an example, the
electromagnetic radiation can pass through an optical system that
includes a mask (e.g., a high thermal conductivity mask, such as a
molybdenum mask, a copper-beryllium mask) before reaching surface
501. In some embodiments, the mask is an aperture (e.g., for
truncating or shaping the beam). The optical system can include,
for example, at least two lenses having the mask disposed
therebetween. As another example, the mask can be formed as a
pattern of material on surface 501, with the mask leaving certain
portions of surface 501 exposed and some portions of surface 501
unexposed. Such a mask can be formed, for example, via a
lithography process. In some embodiments, the electromagnetic
radiation can be rastered across one or more portions of the
mask.
[0109] Without wishing to be bound by theory, it is believed that
reducing at least one dimension of the region on surface 501
exposed to electromagnetic radiation within a given area of surface
501 can limit undesired crack propagation, such as crack
propagation into layer 504, layer 506 or other layers of stack 650
during removal of substrate 502, while still allowing for crack
propagation at the interface between substrate 502 and buffer layer
504. It is believed that, if the size of the feature of the
electromagnetic radiation on surface 501 is too large, then a
gaseous bubble (e.g., a nitrogen bubble) may form that can create a
localized pressure that can cause undesired cracking. For example,
in embodiments in which surface 501 is exposed to laser radiation
that forms a spot or a line on surface 501, at least one dimension
of the spot or line can be a maximum of at most about one
millimeter (e.g., at most about 500 microns, at most about 100
microns, at most about 25 microns, at most about 10 microns). In
some embodiments, the spot size is from about five microns to about
one millimeter (e.g., from about five microns to about 100 microns,
from about five microns to about 25 microns, from about five
microns to about 10 microns).
[0110] In certain embodiments, stack 650 is vibrated while surface
501 is exposed to the electromagnetic radiation. Without wishing to
be bound by theory, it is believed that vibrating stack 650 while
exposing stack 650 to the electromagnetic radiation can enhance
crack propagation along the interface between layer 504 and
substrate 502. Generally, the conditions are selected to limit the
propagation of cracks into layer 504 (e.g., so that substantially
no cracks propagate into layer 504, 506, and the rest of stack
650).
[0111] After removal of substrate 502, a portion of buffer layer
504 typically remains on at least a portion of the surface of layer
506. A residue of material from substrate 502 (e.g., containing
aluminum and/or oxygen) can also be present on the remaining
portion of buffer layer 504 and/or on the surface of layer 506. It
is generally desirable to remove the remaining portions of buffer
layer 504 and any residue from substrate 502, to expose the surface
of layer 506, and to clean the exposed surface of layer 506 because
layer 506 (which is typically formed of an n-doped semiconductor
material) can exhibit good electrical properties (e.g., desirable
contact resistance) for subsequent formation of an electrical
contact. One or more process steps are usually used to remove any
residue and/or remaining portion of buffer layer 504 present, and
to clean the surface of layer 506 (e.g., to remove impurities, such
as organics and/or particles). The process(es) can be performed
using a variety of techniques and/or combinations of techniques.
Examples include chemical-mechanical polishing, mechanical
polishing, reactive ion etching (e.g., with a substantially
chemically etching component), physical etching, and wet etching.
Such methods are disclosed, for example, in Ghandhi, S., VLSI
Fabrication Principles: Silicon & Gallium Arsenide (1994),
which is hereby incorporated by reference. In certain embodiments,
buffer layer 504 is not completely removed. Instead, in such
embodiments, these processes can be used to remove only on portions
of buffer layer 504 that correspond to locations where electrical
leads will subsequently be disposed (e.g., by using a self-aligned
process).
[0112] Often, when substrate 502 is removed, the amount of strain
in stack 650 (e.g., due to the lattice mismatch and/or thermal
mismatch between the layers in stack 650) can change. For example,
if the amount of strain in stack 650 is decreased, the peak output
wavelength of region 510 can change (e.g., increase). As another
example, if the amount of strain in stack 650 is increased, the
peak output wavelength of region 510 can change (e.g.,
decrease).
[0113] To limit undesired cracking during removal of substrate 502,
in some embodiments, consideration is given to the coefficient of
thermal expansion of both substrate 502, the coefficient of thermal
expansion of submount 602, the combined thickness of layers 504,
506, 508, 510, and 512, and/or the coefficient of thermal expansion
of one or more of layers 504, 506, 508, 510, and 512. As an
example, in some embodiments, substrate 502 and submount 602 are
selected so that the coefficient of thermal expansion of submount
602 differs from a coefficient of thermal expansion of substrate
502 by less than about 15% (e.g., less than about 10%, less than
about 5%). As another example, in certain embodiments, substrate
502 and submount 602 are selected so that the thickness of submount
602 is substantially greater than the thickness of substrate 502.
As an additional example, in some embodiments, semiconductor layers
504, 506, 508, 510, 512 and submount 602 are selected so that the
coefficient of thermal expansion of submount 602 differs from a
coefficient of thermal expansion of one or more of layers 504, 506,
608, 510, and 512 by less than about 15% (e.g., less than about
10%, less than about 5%).
[0114] In general, substrate 502 and submount 602 can have any
desired thickness. In some embodiments, substrate 502 is at most
about five millimeters (e.g., at most about three millimeters, at
most about one millimeter, about 0.5 millimeter) thick. In certain
embodiments, submount 602 is at most about 10 millimeters (e.g., at
most about five millimeters, at most about one millimeter, about
0.5 millimeter) thick. In some embodiments, submount 602 is thicker
than substrate 502, and, in certain embodiments, substrate 502 is
thicker than submount 602.
[0115] After removal of buffer layer 504 and exposing/cleaning the
surface of layer 506, the thickness of layer 506 can be reduced to
a desired final thickness for use in the light-emitting device.
This can be achieved, for example, using a mechanical etching
process, alone or in combination with an etching process. In some
embodiments, after etching/cleaning the exposed surface of layer
506, the surface of layer 506 has a relatively high degree of
flatness (e.g., a relatively high degree of flatness on the scale
of the lithography reticle to be used). As an example, in some
embodiments, after etching/cleaning the exposed surface of layer
506, the surface of layer 506 has a flatness of at most about 10
microns per 6.25 square centimeters (e.g., at most about five
microns per 6.25 square centimeters, at most about one micron per
6.25 square centimeters). As another example, in certain
embodiments, after etching/cleaning the exposed surface of layer
506, the surface of layer 506 has a flatness of at most about 10
microns per square centimeter (e.g., at most about five microns per
square centimeter, at most about one microns per square
centimeter). In certain embodiments, after etching/cleaning the
exposed surface of layer 506, the surface of layer 506 has an RMS
roughness of at most about 50 nanometers (e.g., at most about 25
nanometers, at most about 10 nanometers, at most about five
nanometers, at most about one nanometer).
[0116] In some embodiments, prior to forming the dielectric
function that varies spatially according to a pattern in the
surface of layer 506, the exposed surface of layer 506 may be too
rough and/or insufficiently flat to use nanolithography to form the
pattern with sufficient accuracy and/or reproducibility. To enhance
the ability to accurately and/or reproducibly form the pattern in
the surface of layer 506, the nanolithography process may include
depositing a planarization layer on the surface of layer 506 and a
lithography layer on the surface of the planarization layer. For
example, FIG. 21 shows an embodiment in which a planarization layer
702 is disposed on the surface of layer 506, and a lithography
layer 704 is disposed on the surface of layer 702, an exposed
surface 505 of layer 506 may be relatively rough (e.g., RMS
roughness of about 10 nanometers or more) after cleaning/etching
layer 506. In some embodiments, planarization layer 702 is formed
of multiple layers (e.g., of the same material) that are
sequentially deposited.
[0117] Examples of materials from which planarization layer 702 can
be selected include polymers (e.g., DUV-30J from Brewer Sciences,
anti-reflection coatings, high viscosity formable polymers), and
examples of materials from which lithography layer 704 can be
selected include UV-curable polymers (e.g., low viscosity
MonoMat.TM. available from Molecular Imprints, Inc.). Layers 702
and 704 can be formed using any desired technique, such as, for
example, spin coating, vapor deposition, and the like.
[0118] Layer 702 can be, for example, at least about 100 nanometers
thick (e.g., at least about 500 nanometers thick) and/or at most
about five microns thick (e.g., at most about one micron thick).
Layer 704 can be, for example, at least about one nanometer thick
(e.g., at least about 10 nanometers thick) and/or at most about one
micron thick (e.g., at most about 0.5 micron thick).
[0119] A mold that defines a portion of the desired pattern is then
pressed into lithography layer and (typically with heating or
UV-curing of the mold and/or layer 704), and stepped across the
surface of layer 704 in a portion-by-portion manner to form
indentions in layer 704 (FIG. 22) that correspond to the desired
pattern in the surface of layer 506. In some embodiments, a single
step covers the entire wafer (e.g., full wafer nanolithography
techniques) Layer 704 is then etched (e.g., using reactive ion
etching, wet etching) to expose portions of the surface of layer
702 corresponding to what were the indented portions of layer 704
(FIG. 23). Examples of such imprint/etch processes are disclosed,
for example, in U.S. Pat. No. 5,722,905, and Zhang et al., Applied
Physics Letters, Vol. 83, No. 8, pp. 1632-34, both of which are
hereby incorporated by reference. Typically, the pattern in layer
704 also leaves regions for depositing n-contacts later on in the
process flow. In alternate embodiments, other techniques (e.g.,
x-ray lithography, deep ultraviolet lithography, extreme
ultraviolet lithography, immersion lithography, interference
lithography, electron beam lithography, photolithography,
microcontact printing, self-assembly techniques) may be used to
create the pattern in layer 704.
[0120] As shown in FIG. 24, patterned layer 704 is used as a mask
to transfer the pattern into the planarization layer 702 (e.g., dry
etching, wet etching). An example of a dry etching method is
reactive ion etching. Referring to FIG. 25, layers 702 and 704 are
subsequently used as a mask to transfer the pattern into the
surface of layer 506 (e.g., using dry etching, wet etching). As
shown in FIG. 26, following etching of layer 506, the layers 702
and 704 are removed (e.g., using an oxygen-based reactive ion etch,
a wet solvent etch).
[0121] Referring to FIG. 27, in some embodiments, the process can
include, disposing a material 708 (e.g., a metal, such as aluminum,
nickel, titanium, tungsten) in the etched portions of layers 702
and 704 (e.g., by evaporation) and on the surface of layer 704. As
shown in FIG. 28, layers 702 and 704 are then etched (e.g., using
reactive ion etching, wet etching), leaving behind etch-resistant
material 708 on the surface of layer 506, which can serve as a mask
for etching the pattern into the surface of layer 506 (FIG. 29).
Referring to FIG. 30, etch resistant material 708 can then be
removed (e.g., using dry etching, wet etching).
[0122] In some embodiments, the process can include, after forming
the indents in layer 704, disposing (e.g., spin coating) an etch
resistant material (e.g., a Si-doped polymer) 710 on the surface of
layer 704 and in the indents in layer 704, and material 710 is then
etched back (e.g., using dry etching) so that to expose the surface
of layer 704 while maintaining the etch-resistant material in the
indents in layer 704 (FIG. 31). As shown in FIG. 32, portions of
layers 702 and 704 are then etched (e.g., using reactive ion
etching, dry etching, wet etching), leaving behind etch-resistant
material 708 and the portions of layers 702 and 704 under material
708, which serve as a mask for etching the pattern into the surface
of layer 506 (FIG. 33). Referring to FIG. 34, the remaining
portions of layers 702 and 704, as well as etch resistant material
708, can then be removed (e.g., using reactive ion etching, dry
etching, wet etching). In some embodiments, removing layer 708 can
involve the use of a plasma process (e.g., a fluorine plasma
process).
[0123] After the pattern has been transferred to n-doped layer 506,
a layer of phosphor material can optionally be disposed (e.g.,
spin-coated) onto the patterned surface of n-doped layer 506. In
some embodiments, the phosphor can conformally coat the patterned
surface (coat with substantially no voids present along the bottoms
and sidewalls of the openings in the patterned surface).
Alternatively, a layer of encapsulant material can be disposed on
the surface of patterned n-doped layer 506 (e.g. by CVD,
sputtering, suspension by liquid binder that is subsequently
evaporated). In some embodiments, the encapsulant can contain one
or more phosphor materials. In some embodiments, the phosphor can
be compressed to achieve thickness uniformity less than about 20%,
less than about 15%, less than about 10%, less than about 5%, or
less than about 2% of the average thickness of the phosphor. In
some embodiments, the phosphor-containing encapsulant can
conformally coat the patterned surface.
[0124] After the dielectric function pattern has been created in
the n-doped layer 506, individual LED dice can be cut from the
wafer. Once wafer processing and wafer testing is complete,
individual LED dice are separated and prepared for packaging and
testing. A sidewall passivation step and/or a pre-separation deep
mesa etching step may be used to reduce potential damage to the
electrical and/or optical properties of the patterned LED incurred
during wafer cutting. The individual LEDs can be any size up to the
size of the wafer itself, but individual LEDs are typically square
or rectangular, with sides having a length between about 0.5 mm to
5 mm. To create the dice, standard photolithography is used to
define the location of contact pads on the wafer for energizing the
device, and ohmic contacts are evaporated (e.g. using electron beam
evaporation) onto the desired locations.
[0125] If an LED die is packaged, the package should generally be
capable of facilitating light collection while also providing
mechanical and environmental protection of the die. For example, a
transparent cover can be packaged on the LED die to protect the
patterned surface of the 506 when an encapsulant is not used. The
cover slip is attached to supports 142 using a glassy frit that is
melted in a furnace. The opposite ends of the supports are
connected using a cap weld or an epoxy for example. Supports are
typically Ni-plated to facilitate welding to an Au plated surface
of the package. It believed that the absence of an encapsulant
layer allows higher tolerable power loads per unit area in the
patterned surface LED 100. Degradation of the encapsulant can be a
common failure mechanism for standard LEDs and is avoided not using
an encapsulant layer.
[0126] Because the LEDs are cut from a large area flat wafer, their
light output per area does not decrease with area. Also, because
the cross section of an individual LEDs cut from a wafer is only
slightly larger than the light-emitting surface area of the LED,
many individual, and separately addressable LEDs can be packed
closely together in an array. If one LED does not function (e.g.,
due to a large defect), then it does not significant diminish the
performance of the array because the individual devices are closely
packed.
[0127] While certain embodiments have been described, other
embodiments are possible.
[0128] As an example, while certain thickness for a light-emitting
device and associated layers are discussed above, other thicknesses
are also possible. In general, the light-emitting device can have
any desired thickness, and the individual layers within the
light-emitting device can have any desired thickness. Typically,
the thicknesses of the layers within multi-layer stack 122 are
chosen so as to increase the spatial overlap of the optical modes
with light-generating region 130, to increase the output from light
generated in region 130. Exemplary thicknesses for certain layers
in a light-emitting device include the following. In some
embodiments, layer 134 can have a thickness of at least about 100
nm (e.g., at least about 200 nm, at least about 300 nm, at least
about 400 nm, at least about 500 nm) and/or at most about 10
microns (e.g., at most about five microns, at most about three
microns, at most about one micron). In certain embodiments, layer
128 has a thickness of at least about 10 nm (e.g., at least about
25 nm, at least about 40 nm) and/or at most about one micron (e.g.,
at most about 500 nm, at most about 100 nm). In some embodiments,
layer 126 has a thickness of at least about 10 nm (e.g., at least
about 50 nm, at least about 100 nm) and/or at most about one micron
(e.g., at most about 500 nm, at most about 250 nm). In certain
embodiments, light-generating region 130 has a thickness of at
least about 10 nm (e.g., at least about 25 nm, at least about 50
nm, at least about 100 nm) and/or at most about 500 nm (e.g., at
most about 250 nm, at most about 150 nm).
[0129] As an example, while a light-emitting diode has been
described, other light-emitting devices having the above-described
features (e.g., patterns, processes) can be used. Such
light-emitting devices include lasers and optical amplifiers.
[0130] As another example, while current spreading layer 132 has
been described as a separate layer from n-doped layer 134, in some
embodiments, a current spreading layer can be integral with (e.g.,
a portion of) layer 134. In such embodiments, the current spreading
layer can be a relatively highly n-doped portion of layer 134 or a
heterojunction between (e.g. AlGaN/GaN) to form a 2D electron
gas.
[0131] As a further example, while certain semiconductor materials
have been described, other semiconductor materials can also be
used. In general, any semiconductor materials (e.g., III-V
semiconductor materials, organic semiconductor materials, silicon)
can be used that can be used in a light-emitting device. Examples
of other light-generating materials include InGaAsP, AlInGaN,
AlGaAs, InGaAlP. Organic light-emitting materials include small
molecules such as aluminum tris-8-hydroxyquinoline (Alq.sub.3) and
conjugated polymers such as
poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-vinylenephenylene] or
MEH-PPV.
[0132] As an additional example, while large area LEDs have been
described, the LEDs can also be small area LEDs (e.g., LEDs smaller
than the standard about 300 microns on edge).
[0133] As another example, while a dielectric function that varies
spatially according to a pattern has been described in which the
pattern is formed of holes, the pattern can also be formed in other
ways. For example, a pattern can be formed continuous veins and/or
discontinuous veins in the appropriate layer. Further, the pattern
in varying dielectric function can be achieved without using holes
or veins. For example, materials having different dielectric
functions can be patterned in the appropriate layer. Combinations
of such patterns can also be used.
[0134] As a further example, while layer 126 has been described as
being formed of silver, other materials can also be used. In some
embodiments, layer 126 is formed of a material that can reflect at
least about 50% of light generated by the light-generating region
that impinges on the layer of reflective material, the layer of
reflective material being between the support and the multi-layer
stack of materials. Examples of such materials include distributed
Bragg reflector stacks and various metals and alloys, such as
aluminum and aluminum-containing alloys.
[0135] As another example, support 120 can be formed of a variety
of materials. Examples of materials from which support 120 can be
formed include copper, copper-tungsten, aluminum nitride, silicon
carbide, beryllium-oxide, diamonds, TEC and aluminum.
[0136] As an additional example, while layer 126 has been described
as being formed of a heat sink material, in some embodiments, a
light-emitting device can include a separate layer (e.g., disposed
between layer 126 and submount 120) that serves as a heat sink. In
such embodiments, layer 126 may or may not be formed of a material
that can serve as a heat sink.
[0137] As a further example, while the varying pattern in
dielectric function has been described as extending into n-doped
layer 134 only (which can substantially reduce the likelihood of
surface recombination carrier losses) in addition to making use of
the entire light-generating region, in some embodiments, the
varying pattern in dielectric function can extend beyond n-doped
layer (e.g., into current spreading layer 132, light-generating
region 130, and/or p-doped layer 128).
[0138] As another example, while embodiments have been described in
which air can be disposed between surface 110 can cover slip 140,
in some embodiments materials other than, or in an addition to, air
can be disposed between surface 110 and cover slip 140. Generally,
such materials have an index of refraction of at least about one
and less than about 1.5 (e.g., less than about 1.4, less than about
1.3, less than about 1.2, less than about 1.1). Examples of such
materials include nitrogen, air, or some higher thermal
conductivity gas. In such embodiments, surface 110 may or may not
be patterned. For example, surface 110 may be non-patterned but may
be roughened (i.e., having randomly distributed features of various
sizes and shapes less than .lamda./5).
[0139] As another example, while embodiments involving the
deposition and etching of planarization and lithography layers have
been described, in some embodiments, a pre-patterned etch mask can
be laid down on the surface of the n-doped semiconductor layer.
[0140] As a further example, in some embodiments, an etch mask
layer can be disposed between the n-doped semiconductor layer and
the planarization layer. In such embodiments, the method can
include removing at least a portion of the etch mask layer (e.g.,
to form a pattern in the etch stop layer corresponding to the
pattern in the n-doped semiconductor layer).
[0141] As an additional example, while embodiments, have been
disclosed in which surface 110 is patterned and smooth, in some
embodiments, surface 110 may be patterned and rough (i.e., having
randomly distributed features of various sizes and shapes less than
.lamda./5, less than .lamda./2, less than .lamda.). Further, in
certain embodiments, the sidewalls of openings 150 can be rough
(i.e., having randomly distributed features of various sizes and
shapes less than .lamda./5, less than .lamda./2, less than
.lamda.), with or without surface 110 being rough. Moreover, in
some embodiments, the bottom surface of openings 150 can be rough
(i.e., having randomly distributed features of various sizes and
shapes less than .lamda./5, less than .lamda./2, less than
.lamda.). Surface 110, the sidewalls of openings 150, and/or the
bottom surfaces of openings 150 can be roughened, for example, by
etching (e.g., wet etching, dry etching, reactive ion etching).
Without wishing to be bound by theory, it is believed that
roughening surface 110 and/or the sidewalls of openings 150 may
increase the probability, with respect to a atomically smooth
surface, that a light ray will eventually strike at an angle that
less than the critical angle given by Snell's law and will be
extracted.
[0142] As another example, in some embodiments, the submount can be
machined to include spring-like structures. Without wishing to be
bound by theory, it is believed that such spring-like structures
may reduce cracking during removal of the substrate.
[0143] As a further example, in some embodiments, the submount can
be supported by an acoustically absorbing platform (e.g., a
polymer, a metallic foam). Without wishing to be bound by theory,
it is believed that such acoustically absorbing structures may
reduce cracking during removal of the substrate.
[0144] As an additional example, in some embodiments, the substrate
is treated (e.g., etched, ground, sandblasted) before being
removed. In certain embodiments, the substrate may be patterned
before it is removed. In some embodiments, the thickness of the
layers is selected so that, before removing the substrate and
buffer layers, the neutral mechanical axis of the multi-layer stack
is located substantially close (e.g., less than about 500 microns,
less than about 100 microns, less than about 10 microns, less than
about five microns) to the interface between the p-doped
semiconductor layer and a bonding layer. In certain embodiments,
portions of the substrate are separately removed (e.g., to reduce
the likelihood of cracking).
[0145] As another example, while embodiments have been described in
which a buffer layer is separate from an n-doped semiconductor
layer (e.g., a buffer layer grown on the substrate, with an n-doped
semiconductor layer separately grown on the buffer), in some
embodiments, there can be a single layer instead. For example, the
single layer can be formed by first depositing a relatively low
doped (e.g., undoped) semiconductor material on the substrate,
followed by (in one process) depositing a relatively high doped
(n-doped) semiconductor material.
[0146] As a further example, while embodiments have been described
in which a substrate is removed by a process that includes exposing
a surface of the substrate to electromagnetic radiation (e.g.,
laser light), in some embodiments other methods can be used to
remove the substrate. For example, removal of the substrate can
involve etching and/or lapping the substrate. In certain
embodiments, the substrate can be etched and/or lapped, and then
subsequently exposed to electromagnetic radiation (e.g., laser
light).
[0147] As an additional example, in some embodiments, after
depositing the planarization layer but before depositing the
lithography layer, the upper surface of the planarization layer can
be flattened. For example, a flat object, such as an optical flat,
can be placed on the upper surface of the planarization layer while
heating the planarization layer (e.g., with a hot plate). In some
embodiments, a pressure can be applied (e.g., using a physical
weight or press) to assist with the flattening process.
[0148] As another example, in some embodiments the substrate can be
treated before being removed. For example, the substrate can be
exposed to one or more processes selected from etching, polishing,
grinding and sandblasting. In certain embodiments, treating the
substrate can include patterning the substrate. In some
embodiments, treating the substrate includes depositing an
antireflective coating on the substrate. Such an antireflective
coating can, for example, allow relatively large regions of the
substrate to be removed when using a substrate removal process that
involves exposing the substrate to electromagnetic radiation
because the coating can reduce reflection of the electromagnetic
radiation. In certain embodiments, a pattern on the surface of the
substrate can also be used to achieve an anti-reflection
effect.
[0149] In some embodiments, a light-emitting device can include a
layer of a phosphor material coated on surface 110, cover layer 140
and supports 142.
[0150] In certain embodiments, a light-emitting device can include
a cover layer 140 that has a phosphor material disposed therein. In
such embodiments, surface 110 may or may not be patterned.
[0151] In an alternative implementation, the light emitted by the
light-generating region 130 is UV (or violet, or blue) and the
phosphor layer 180 includes a mixture of a red phosphor material
(e.g., L.sub.2O.sub.2S:Eu.sup.3+), a green phosphor material (e.g,
ZnS:Cu,Al,Mn), and blue phosphor material (e.g,
(Sr,Ca,Ba,Mg).sub.10(PO.sub.4).sub.6Cl:Eu.sup.2+).
[0152] Other embodiments are in the claims.
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