U.S. patent application number 11/455645 was filed with the patent office on 2007-01-11 for semiconductor device including a floating gate electrode having stacked structure.
Invention is credited to Kazuo Hatakeyama.
Application Number | 20070007582 11/455645 |
Document ID | / |
Family ID | 37617532 |
Filed Date | 2007-01-11 |
United States Patent
Application |
20070007582 |
Kind Code |
A1 |
Hatakeyama; Kazuo |
January 11, 2007 |
Semiconductor device including a floating gate electrode having
stacked structure
Abstract
A semiconductor device includes a semiconductor layer having a
plurality of element regions in its surface area, which are
delimited by at least one element isolation trench, a plurality of
floating gate electrodes provided on the element regions with a
first gate insulation film interposed therebetween and each
including a first charge-storage layer having a first width which
is equal to that of each of the element regions and a second
charge-storage layer stacked on the first charge-storage layer and
having a second width which is smaller than the first width, and a
plurality of control gate electrodes provided on the floating gate
electrodes with a second gate insulation films interposed
therebetween. The device further includes an element isolating
insulation film buried into the element isolation trench. The top
surface of the element isolating insulation film is located higher
than that of the first charge-storage layer.
Inventors: |
Hatakeyama; Kazuo; (Tokyo,
JP) |
Correspondence
Address: |
C. IRVIN MCCLELLAND;OBLON, SPIVAK, MCCLELLAND, MAIER & NEUSTADT, P.C.
1940 DUKE STREET
ALEXANDRIA
VA
22314
US
|
Family ID: |
37617532 |
Appl. No.: |
11/455645 |
Filed: |
June 20, 2006 |
Current U.S.
Class: |
257/316 ;
257/E21.209; 257/E21.682; 257/E27.103 |
Current CPC
Class: |
H01L 27/115 20130101;
H01L 27/11521 20130101; H01L 29/40114 20190801; H01L 29/42336
20130101 |
Class at
Publication: |
257/316 |
International
Class: |
H01L 29/788 20060101
H01L029/788 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 21, 2005 |
JP |
2005-180731 |
Claims
1. A semiconductor device comprising: a semiconductor layer having
a plurality of element regions in a surface area thereof, the
element regions being delimited by at least one element isolation
trench; a plurality of floating gate electrodes provided on the
element regions with a first gate insulation film interposed
therebetween, each of the floating gate electrodes including a
first charge-storage layer having a first width which is equal to
that of each of the element regions and a second charge-storage
layer stacked on the first charge-storage layer and having a second
width which is smaller than the first width; a plurality of control
gate electrodes provided on the floating gate electrodes with a
second gate insulation film interposed therebetween; and an element
isolating insulation film buried into the element isolation trench,
a top surface of the element isolating insulation film being
located higher than that of the first charge-storage layer.
2. The semiconductor device according to claim 1, wherein the
second charge-storage layer is a polysilicon layer formed by
selective epitaxial growth.
3. The semiconductor device according to claim 1, wherein the
second charge-storage layer is a polysilicon layer formed by
chemical vapor deposition.
4. The semiconductor device according to claim 1, wherein the
element isolation trench is provided along a first direction.
5. The semiconductor device according to claim 1, wherein the
control gate electrodes are continuously provided in a second
direction that crosses the element isolation trench.
6. The semiconductor device according to claim 1, wherein
nonvolatile memory cells are provided in surface areas of the
element regions, respectively, which correspond to the floating
gate electrodes and the control gate electrodes.
7. The semiconductor device according to claim 6, wherein a given
number of nonvolatile memory cells are arranged in series in the
first direction to form a NAND type memory cell column.
8. The semiconductor device according to claim 1, wherein a second
distance between second charge-storage layers of adjacent two
floating gate electrodes is longer than a first distance between
first charge-storage layers.
9. A semiconductor device comprising: a semiconductor layer having
at least one element isolation trench in a surface area thereof; at
least one element isolation region formed by burying an element
isolating insulation film into the element isolation trench; a
plurality of element regions electrically isolated by the element
isolation region; a plurality of floating gate electrodes provided
on the element regions with a first gate insulation film interposed
therebetween; and a plurality of control gate electrodes provided
on the floating gate electrodes with a second gate insulation film
interposed therebetween, wherein the floating gate electrodes each
have a stacked structure of two or more charge-storage layers, a
width of a lowermost charge-storage layer being equal to that of
each of the element regions, and a width of each of other upper
charge-storage layers being smaller than that of the lowermost
charge-storage layer, and a top surface of the lowermost
charge-storage layer is located lower than that of the element
isolating insulation film.
10. The semiconductor device according to claim 9, wherein the
upper charge-storage layers are polysilicon layers formed by
selective epitaxial growth.
11. The semiconductor device according to claim 9, wherein the
upper charge-storage layers are polysilicon layer formed by
chemical vapor deposition.
12. The semiconductor device according to claim 9, wherein the
element isolation trench is provided along a first direction.
13. The semiconductor device according to claim 9, wherein the
control gate electrodes are continuously provided in a second
direction that crosses the element isolation trench.
14. The semiconductor device according to claim 9, wherein
nonvolatile memory cells are provided in surface areas of the
element regions, respectively, which correspond to the floating
gate electrodes and the control gate electrodes.
15. The semiconductor device according to claim 14, wherein a given
number of nonvolatile memory cells are arranged in series in the
first direction to form a NAND type memory cell column.
16. The semiconductor device according to claim 9, wherein a second
distance between second charge-storage layers of adjacent two
floating gate electrodes is longer than a first distance between
first charge-storage layers.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from prior Japanese Patent Application No. 2005-180731,
filed Jun. 21, 2005, the entire contents of which are incorporated
herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device.
More specifically, the invention relates to a nonvolatile
semiconductor memory device such as a flash memory, which includes
memory cells formed of metal oxide semiconductor (MOS) transistors
each having a double (stacked) gate structure.
[0004] 2. Description of the Related Art
[0005] Flash electrically erasable and programmable read only
memories (flash EEPROMs) have recently been well known as
nonvolatile semiconductor memory devices that are capable of
electrically rewriting (writing and erasing) data and suitable for
high density and large capacity. The flash EEPROMs include memory
cells of MOS transistors each having a double-gate structure in
which a floating gate is provided between a silicon substrate and a
control gate.
[0006] The nonvolatile semiconductor memory devices such as flash
EEPROMs have the following problem. If the distance between
adjacent memory cells in the word line direction is shortened, an
interference effect occurs between the memory cells with increases
in capacity coupling between adjacent floating gates. This problem
deteriorates cell characteristics, such as write and erase
characteristics of memory cells.
[0007] As a solution to the above problem, it can be thought that
the distance between adjacent memory cells is lengthened by
decreasing only the width of a floating gate in the word line
direction without changing the design pitches of memory cells.
However, a floating gate, which is opposed to a silicon substrate
with a tunnel oxide film interposed therebetween, is decreased in
sectional area if only it is decreased only in width. It is
therefore feared that cell current will be reduced. With this
solution, the problem with the deterioration of cell
characteristics due to the interference effect between adjacent
memory cells can be resolved, but a new problem that the reduction
in cell current deteriorates the cell characteristics will
occur.
[0008] The above new problem will become serious in a high-density,
large-capacity NAND flash EEPROM such as a next-generation memory
with 90 nm or less design rules and a multivalued memory for
storing multivalued data.
[0009] As described above, the nonvolatile semiconductor memory
devices are microfabricated more and more and likely to decrease in
the distance between adjacent memory cells. They have required a
technique capable of reducing an interference effect that occurs
between adjacent memory cells with increases in capacity coupling
between adjacent floating gates without decreasing cell current,
and avoiding deteriorating cell characteristics due to the
microfabrication.
[0010] In order to suppress the increase of capacity coupling
between adjacent floating gates, there have been proposed methods
of forming a recess in an element isolation insulating film
provided between memory cells and then forming a control gate line
(word line) in the recess. Of these methods, there is a method of
reliably forming a control gate line in a recess of an element
isolating insulation film even though an element isolation trench
decreases in width to suppress the capacity coupling between
floating gates (see, e.g., Jpn. Pat. Appln. KOKAI Publication
2005-85996). In the prior art devices, the floating gates are each
formed of a single film having a uniform width, while the control
gate line extends to a deep portion of the element isolating
insulation film.
BRIEF SUMMARY OF THE INVENTION
[0011] According to a first aspect of the present invention, there
is provided a semiconductor device comprising a semiconductor layer
having a plurality of element regions in a surface area thereof,
the element regions being delimited by at least one element
isolation trench, a plurality of floating gate electrodes provided
on the element regions with a first gate insulation film interposed
therebetween, each of the floating gate electrodes including a
first charge-storage layer having a first width which is equal to
that of each of the element regions and a second charge-storage
layer stacked on the first charge-storage layer and having a second
width which is smaller than the first width, a plurality of control
gate electrodes provided on the floating gate electrodes with a
second gate insulation film interposed therebetween, and an element
isolating insulation film buried into the element isolation trench,
a top surface of the element isolating insulation film being
located higher than that of the first charge-storage layer.
[0012] According to a second aspect of the present invention, there
is provided a semiconductor device comprising a semiconductor layer
having at least one element isolation trench in a surface area
thereof, at least one element isolation region formed by burying an
element isolating insulation film into the element isolation
trench, a plurality of element regions electrically isolated by the
element isolation region, a plurality of floating gate electrodes
provided on the element regions with a first gate insulation film
interposed therebetween, and a plurality of control gate electrodes
provided on the floating gate electrodes with a second gate
insulation film interposed therebetween, wherein the floating gate
electrodes each have a stacked structure of two or more
charge-storage layers, a width of a lowermost charge-storage layer
being equal to that of each of the element regions, and a width of
each of other upper charge-storage layers being smaller than that
of the lowermost charge-storage layer, and a top surface of the
lowermost charge-storage layer is located lower than that of the
element isolating insulation film.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0013] FIG. 1A is a plan view of a configuration of memory cells of
a nonvolatile semiconductor memory device according to an
embodiment of the present invention;
[0014] FIG. 1B is a sectional view of memory cells of the
nonvolatile semiconductor memory device according to the embodiment
of the present invention;
[0015] FIG. 2 is a sectional view illustrating a step of a method
of manufacturing the nonvolatile semiconductor memory device
according to the embodiment of the present invention;
[0016] FIG. 3 is a sectional view illustrating a step of the method
of manufacturing the nonvolatile semiconductor memory device
according to the embodiment of the present invention;
[0017] FIG. 4 is a sectional view illustrating a step of the method
of manufacturing the nonvolatile semiconductor memory device
according to the embodiment of the present invention;
[0018] FIG. 5 is a sectional view illustrating a step of the method
of manufacturing the nonvolatile semiconductor memory device
according to the embodiment of the present invention; and
[0019] FIG. 6 is a sectional view illustrating a step of the method
of manufacturing the nonvolatile semiconductor memory device
according to the embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0020] An embodiment of the present invention will be described
with reference to the accompanying drawings. It should be noted
that the drawings are schematic ones and the dimension ratios shown
therein are different from the actual ones. Needless to say, the
dimensions vary from drawing to drawing and so do the ratios of
dimensions.
[0021] FIGS. 1A and 1B show a basic configuration of a
semiconductor device according to an embodiment of the present
invention. The configuration will be described, taking as an
example memory cells each having a double-gate structure in a
nonvolatile semiconductor memory device such as a NAND flash
EEPROM. FIG. 1A is a plan view and FIG. 1B is a sectional view
taken along line Ib-Ib.
[0022] A plurality of trenches 12 each serving as an element
isolation trench are formed in the surface area of a p-type silicon
substrate (or a p well region) 11 serving as a semiconductor layer.
The trenches 12 are arranged in parallel in a first direction (bit
line direction). An element isolating insulation film (e.g., a
silicon oxide film that is referred to as a SiO.sub.2 film
hereinafter) 13 is buried into each of the trenches 12. Thus, an
element isolation region 14 having a shallow trench isolation (STI)
structure is formed to isolate element regions (described later)
electrically from each other.
[0023] On the other hand, a plurality of element regions 15 are
formed in the surface area of the p-type silicon substrate 11 and
delimited by the trenches 12. A floating gate electrode (floating
gate) 17 is formed on the top surface of each of element regions 15
serving as channel regions, with a tunnel oxide film (first gate
insulation film) 16 interposed therebetween. The tunnel oxide film
16 is formed of a SiO.sub.2 film having a thickness of, e.g., 150
.ANG. or less.
[0024] In the present embodiment, the floating gate electrode 17
has a stacked structure in which two or more charge-storage layers
are stacked one on another. The charge-storage layers include a
first charge-storage layer (lowermost one) 17a and a second
charge-storage layer (upper one) 17b. The width of the first
charge-storage layer 17a in a second direction (word line
direction) that is perpendicular to the first direction is almost
equal to that of each of the element regions 15. In contrast, the
width of the second charge-storage layer 17b in the second
direction is smaller than that of the first charge-storage layer
17a.
[0025] The top surface of the element isolating insulation film 13
is located higher than that of the first charge-storage layer 17a
(the interface surface between the first and second charge-storage
layers 17a and 17b). On the first charge-storage layer 17a except
the second charge-storage layer 17b, for example, a tetra ethoxy
silane (TEOS) film 18 is provided such that its top surface is
flush with that of the element isolating insulation film 13. Then,
a control gate electrode 20 is formed on the top surfaces of the
element isolating insulation film 13, TEOS film 18 and second
charge-storage layer 17b, with a gate-to-gate insulation film
(interpolysilicon insulation film) 19 serving as a second gate
insulation film interposed therebetween. Each control gate
electrode 20 is provided on a plurality of floating gate electrodes
17, which are arranged in the second direction, to serve as a word
line.
[0026] The floating gate electrodes 17 and control gate electrodes
20 are self-aligned such that their end faces in the first
direction coincide with the vertical direction, as shown in FIG.
1A. Further, an n-type diffusion layer 21 is formed in the surface
area of each of the element regions 15 between control gate
electrodes 20, with the result that a plurality of memory cells MC
are arranged in matrix.
[0027] With the above configuration, between adjacent floating gate
electrodes 17, the distance (first distance) between the first
charge-storage layers 17a is left as conventional, and the distance
(second distance) between the second charge-storage layers 17b,
which corresponds to the gate-to-gate insulation film 19, can be
lengthened apparently. Consequently, cell current can be maintained
at the same value as a conventional one, which is determined by the
design pitches of the element regions 15, and an interference
effect that occurs between adjacent memory cells with increases in
capacity coupling between adjacent floating gate electrodes 17 can
greatly be reduced. The deterioration of cell characteristics due
to microfabrication, such as the write and erase characteristics of
memory cells MC, can easily be avoided.
[0028] If a NAND flash EEPROM is configured by the nonvolatile
semiconductor memory device having memory cells described above,
one end of a column of a given number of memory cells (e.g.,
sixteen memory cells) connected in series in the first direction is
connected to a bit line via one select transistor, and the other
end thereof is connected to a source line via the other select
transistor.
[0029] A method of manufacturing a nonvolatile semiconductor memory
device (having memory cells) so configured will be described with
reference to FIGS. 2 to 6. This method employs a gate first-forming
technique. FIGS. 2 to 6 are sectional views corresponding to FIG.
1B.
[0030] First, an insulation film serving as a tunnel oxide film 16
is formed on the surface of a p-type silicon substrate (or a p well
region) 11 and then an impurity-doped polysilicon layer serving as
a first charge-storage layer 17a is deposited on the insulation
film by chemical vapor deposition (CVD). After that, a mask
material 31 for processing the film 16 and layer 17a is formed on
the polysilicon layer. As the mask material 31, a material such as
a silicon nitride film (referred to as SiN film hereinafter), which
allows an adequate selection ratio between the material and the
polysilicon layer or a high-density plasma (HDP) film (described
later), is employed. Using the mask material 31 as a mask, the
polysilicon layer, insulation film and p-type silicon substrate 11
are self-aligned to form the first charge-storage layer 17a and the
tunnel oxide film 16, and a trench 12 is opened to form element
regions 15 (see FIG. 2).
[0031] The sidewall portions of the trench 12 and the first
charge-storage layer 17a are oxidized when necessary. An HDP film
serving as an element isolating insulation film 13 is deposited on
the entire surface of the resultant structure to fill the trench 12
completely. Using the mask material 31 as a stopper, the top
surface of the HDP film is flattened by CMP or the like. After
that, the mask material 31 is removed by hot phosphoric acid (see
FIG. 3).
[0032] A TEOS film 18 with good coverage is deposited on the top
surface of the first charge-storage layer 17a from which the mask
material 31 is removed. Part of the TEOS film 18 is etched back
selectively until the top surface of the layer 17a is exposed,
thereby leaving the TEOS film 18 only on the sidewall portions of
the element isolating insulation film (HDP film) 13 (see FIG.
4).
[0033] An impurity-doped polysilicon layer serving as a second
charge-storage layer 17b is grown on the exposed surface of the
first charge-storage layer 17a by, e.g., selective epitaxial
growth. After that, the top surface of the polysilicon layer is
flattened by CMP or the like such that it becomes flush with the
top surface of the HDP film. Thus, a floating gate electrode 17
having a stacked structure of two polysilicon layers (first and
second charge-storage layers 17a and 17b) is formed. The sidewalls
of the second polysilicon layer are formed more inwardly than those
of the first polysilicon layer (see FIG. 5).
[0034] The TEOS film 18 and the HDP film are etched using an
etching material that allows an adequate selection ratio between
the material and the polysilicon layers and also allows the TEOS
and HDP films to be etched to the same extent. The TEOS film 18 and
HDP film are etched together such that the top surface of the HDP
film is located higher than that of the first charge-storage layers
17a (See FIG. 6).
[0035] A gate-to-gate insulation film (e.g., ONO film) 19 is
deposited on the entire surface of the resultant structure and then
control gate electrodes 20 are self-aligned. An n-type diffusion
layer 21 is formed in the surface area of each of element regions
15 between the control gate electrodes 20. Accordingly, a
nonvolatile semiconductor memory device having memory cells as
shown in FIG. 1 is completed.
[0036] As described above, the width of the second charge-storage
layer 17b of the floating gate electrode 17 in the second direction
is set narrower than the first charge-storage layer 17a thereof in
the second direction. The top surface of the element isolating
insulation film 13 is located higher than that of the first
charge-storage layer 17a. Thus, the width of the first
charge-storage layer 17a is left as conventional design pitches,
and the apparent distance between adjacent memory cells MC arranged
in the second direction along the control gate electrodes 20, which
corresponds to the gate-to-gate insulation film 19 on the element
isolating insulation film 13, can be lengthened. Consequently, even
though the distance between the floating gate electrodes 17 is
shortened due to microfabrication, an interference effect that
occurs between adjacent memory cells with increases in capacity
coupling between the floating gate electrodes 17 can be reduced
without decreasing cell current, and the deterioration of cell
characteristics due to the microfabrication can easily be
avoided.
[0037] In the foregoing embodiment, the polysilicon layer serving
as the second charge-storage layer 17b is formed by selective
epitaxial growth. The present invention is not limited to this. It
can be formed by CVD or the like.
[0038] The present invention is not limited to a nonvolatile
semiconductor memory device to be manufactured by the gate
first-forming technique. It can be applied to a nonvolatile
semiconductor memory device to be manufactured by a gate
last-forming technique.
[0039] The stacked structure of the floating gate electrode 17 is
not limited to two layers of the first and second charge-storage
layers 17a and 17b. For example, it can be two or more
charge-storage layers stacked one on another. In this case, the
width of the lowermost charge-storage layer in the second direction
is almost equal to that of the element region, and the width of
each of upper charge-storage layers in the second direction is
smaller than that of the lowermost charge-storage layer in the
second direction, or the charge-storage layers can be gradually
decreased in width.
[0040] The semiconductor layer is not limited to the p-type silicon
substrate (or p well region). It can be applied to an n-type
silicon substrate (or n well region).
[0041] The present invention is not limited to the NAND type flash
EEPROM. It can be applied to various types of nonvolatile
semiconductor memory device configured by memory cells of MOS
transistors each having a double-gate structure, such as NOR and
AND memory devices.
[0042] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
* * * * *