U.S. patent application number 11/516187 was filed with the patent office on 2007-01-04 for thin film transistor array panel and manufacturing method thereof.
Invention is credited to Seung-Soo Baek, Dong-Gyu Kim, Young-Mi Tak, Joo-Ae Youn.
Application Number | 20070004103 11/516187 |
Document ID | / |
Family ID | 32322261 |
Filed Date | 2007-01-04 |
United States Patent
Application |
20070004103 |
Kind Code |
A1 |
Tak; Young-Mi ; et
al. |
January 4, 2007 |
Thin film transistor array panel and manufacturing method
thereof
Abstract
A TFT array panel includes: first and second gate members
connected to each other; a gate insulating layer formed on the
first and the second gate members; first and second semiconductor
members formed on the gate insulating layer opposite the first and
the second gate members, respectively; first and second source
members connected to each other and located near the first and the
second semiconductor members, respectively; first and second drain
members located near the first and the second semiconductor
members, respectively, and located opposite the first and the
second source members with respect to the first and the second gate
members, respectively; and a pixel electrode connected to the first
and the second drain members. The first gate, semiconductor,
source, and drain members form a first TFT, and the second gate,
semiconductor, source, and drain members form a second TFT.
Inventors: |
Tak; Young-Mi; (Seoul,
KR) ; Baek; Seung-Soo; (Suwon-city, KR) ;
Youn; Joo-Ae; (Seongnam-city, KR) ; Kim;
Dong-Gyu; (Yongin-city, KR) |
Correspondence
Address: |
F. CHAU & ASSOCIATES, LLC
130 WOODBURY ROAD
WOODBURY
NY
11797
US
|
Family ID: |
32322261 |
Appl. No.: |
11/516187 |
Filed: |
September 6, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10718309 |
Nov 20, 2003 |
7138655 |
|
|
11516187 |
Sep 6, 2006 |
|
|
|
Current U.S.
Class: |
438/149 ;
257/E27.111 |
Current CPC
Class: |
H01L 27/124 20130101;
H01L 29/78696 20130101; H01L 27/1288 20130101 |
Class at
Publication: |
438/149 |
International
Class: |
H01L 21/84 20060101
H01L021/84 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 20, 2002 |
KR |
2002-0072288 |
Claims
1. A method of manufacturing a thin film transistor array panel,
the method comprising: forming a pair of first and second gate
members; forming a gate insulating layer on the first and the
second gate members; forming a pair of first and second
semiconductor members on the gate insulating layer; forming a pair
of first and second source members and a pair of first and second
drain members; and forming a pixel electrode connected to the first
and the second drain members, wherein at least one pair of the
first and the second gate members, the first and the second
semiconductor members, the first and the second source members, and
the first and the second drain members are formed using a
divisional light exposure, and a boundary line between shots in the
divisional light exposure is located between the first gate member
and the second gate member, between the first semiconductor member
and the second semiconductor member, between the first source
member and the second source member, or between the first drain
member and the second drain member.
2. The method of claim 1, wherein the at least one pair has a shape
symmetrical with respect to the boundary line.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a Divisional of U.S. patent application
Ser. No. 10/718,309 filed on Nov. 20, 2003, and which claims
priority to Korean Patent Application No. 2002-72288, filed Nov.
20, 2002 in the Korean Intellectual Property Office (KIPO), both of
which are fully incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] (a) Field of the Invention
[0003] The present invention relates to a thin film transistor
array panel and a manufacturing method thereof.
[0004] (b) Description of the Related Art
[0005] Generally, a liquid crystal display (LCD) is one of the most
widely used flat panel displays. The LCD has two panels provided
with electrodes formed thereon and a liquid crystal layer
interposed between the two panels. Voltages are applied to the
electrodes to re-orient liquid crystal molecules in the liquid
crystal layer, thereby controlling the transmittance of light.
[0006] The electrodes are supplied with the voltages through
switching elements called thin film transistors (TFTs). The TFTs
are required to have high current driving capacity as the LCD
becomes large, and it is preferable that channel width of the TFTs
are increased.
[0007] In the meantime, photo-etching processes are performed to
form various patterns on the panels of the LCD through light
exposure.
[0008] When a backplane for LCDs is too large to use an exposure
mask, the entire exposure is accomplished by repeating a divisional
exposure called step-and-repeat process. One divisional exposure
unit or area is called a shot. Since transition, rotation,
distortion, and etc. are generated during light exposure, the shots
are not aligned accurately. Accordingly, parasitic capacitances
generated between wires and pixel electrodes differ depending on
the shots, and this causes the bright difference between the shots,
which is recognized at the pixels located at a boundary between the
shots. Therefore, the stitch defect is generated on the screen of
the LCD due to brightness discontinuity between the shots.
SUMMARY OF THE INVENTION
[0009] A thin film transistor array panel is provided, which
includes: first and second gate members connected to each other; a
gate insulating layer formed on the first and the second gate
members; first and second semiconductor members formed on the gate
insulating layer opposite the first and the second gate members,
respectively; first and second source members connected to each
other and located near the first and the second semiconductor
members, respectively; first and second drain members located near
the first and the second semiconductor members, respectively, and
located opposite the first and the second source members with
respect to the first and the second gate members, respectively; and
a pixel electrode connected to the first and the second drain
members, wherein the first gate member, the first semiconductor
member, the first source member, and the first drain members form a
first thin film transistor, and the second gate member, the second
semiconductor member, the second source member, and the second
drain members form a second thin film transistor.
[0010] Preferably, the first thin film transistor and the second
thin film transistor are symmetrically aligned, particularly with
respect to a predetermined line such as a boundary line between
shots in light exposure.
[0011] The thin film transistor array panel may further include a
third thin film transistor different from the first and the second
thin film transistors.
[0012] The alignment of the first and the second thin film
transistors are located opposite each other with respect to a
boundary line between shots in light exposure.
[0013] Channels of the first and the second thin film transistors
have curved shapes, preferably U or C shapes.
[0014] The first and the second semiconductor members may have
substantially the same planar shapes as the first and the second
source and drain members except for channel portions of the first
and the second thin film transistors.
[0015] A method of manufacturing a thin film transistor array panel
is provided, which includes: forming a pair of first and second
gate members; forming a gate insulating layer on the first and the
second gate members; forming a pair of first and second
semiconductor members on the gate insulating layer; forming a pair
of first and second source members and a pair of first and second
drain members; and forming a pixel electrode connected to the first
and the second drain members, wherein at least one pair of the
first and the second gate members, the first and the second
semiconductor members, the first and the second source members, and
the first and the second drain members are formed using a
divisional light exposure, and a boundary line between shots in the
divisional light exposure is located between the first gate member
and the second gate member, between the first semiconductor member
and the second semiconductor member, between the first source
member and the second source member, or between the first drain
member and the second drain member.
[0016] The at least one pair has a shape symmetrical with respect
to the boundary line.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The present invention will become more apparent by
describing embodiments thereof in detail with reference to the
accompanying drawings in which:
[0018] FIG. 1 is a layout view of an exemplary TFT array panel for
an LCD according to an embodiment of the present invention;
[0019] FIG. 2 is a sectional view of the TFT array panel shown in
FIG. 1 taken along the line II-II';
[0020] FIGS. 3A, 4A, 5A and 6A are layout views of the TFT array
panel shown in FIGS. 1 and 2 in intermediate steps of a
manufacturing method thereof according to an embodiment of the
present invention;
[0021] FIGS. 3B, 4B, 5B and 6B are sectional views of the TFT array
panel shown in FIGS. 3A, 4A, 5A and 6A taken along the lines
IIIB-IIIB', IVB-IVB', VB-VB' and VIB-VIB', respectively;
[0022] FIG. 7 is a layout view of an exemplary TFT array panel for
an LCD according to another embodiment of the present
invention;
[0023] FIGS. 8 and 9 are sectional views of the TFT array panel
shown in FIG. 7 taken along the lines VIII-VIII' and IX-IX',
respectively;
[0024] FIG. 10A is a layout view of a TFT array panel shown in
FIGS. 7-9 in the first step of a manufacturing method thereof
according to an embodiment of the present invention;
[0025] FIGS. 10B and 10C are sectional views of the TFT array panel
shown in FIG. 10A taken along the lines XB-XB' and XC-XC',
respectively;
[0026] FIGS. 11A and 11B are sectional views of the TFT array panel
shown in FIG. 10A taken along the lines XB-XB' and XC-XC',
respectively, and illustrate the step following the step shown in
FIGS. 10B and 10C;
[0027] FIG. 12A is a layout view of the TFT array panel in the step
following the step shown in FIGS. 11A and 11B;
[0028] FIGS. 12B and 12C are sectional views of the TFT array panel
shown in FIG. 12A taken along the lines XIIB-XIIB' and XIIC-XIIC',
respectively;
[0029] FIGS. 13A, 14A and 15A, and FIGS. 13B, 14B and 14B are
respective sectional views of the TFT array panel shown in FIG. 12A
taken along the lines XIIB-XIIB' and XIIC-XIIC', respectively, and
illustrate the steps following the step shown in FIGS. 12B and
12C;
[0030] FIG. 16A is a layout view of a TFT array panel in the step
following the step shown in FIGS. 15A and 15B; and
[0031] FIGS. 16B and 16C are sectional views of the TFT array panel
shown in FIG. 16A taken along the lines XVIB-XVIB' and XVIC-XVIC',
respectively;
DETAILED DESCRIPTION OF EMBODIMENTS
[0032] The present invention now will be described more fully
hereinafter with reference to the accompanying drawings, in which
preferred embodiments of the invention are shown. The present
invention may, however, be embodied in many different forms and
should not be construed as limited to the embodiments set forth
herein.
[0033] In the drawings, the thickness of layers, films and regions
are exaggerated for clarity. Like numerals refer to like elements
throughout. It will be understood that when an element such as a
layer, film, region or substrate is referred to as being "on"
another element, it can be directly on the other element or
intervening elements may also be present. In contrast, when an
element is referred to as being "directly on" another element,
there are no intervening elements present.
[0034] Now, TFT array panels and manufacturing methods thereof
according to embodiments of the present invention will be described
with reference to the accompanying drawings.
[0035] First, a TFT array panel for an LCD according to an
embodiment of the present invention is described in detail with
reference to FIGS. 1 and 2.
[0036] FIG. 1 is a layout view of an exemplary TFT array panel for
an LCD according to an embodiment of the present invention, and
FIG. 2 is a sectional view of the TFT array panel shown in FIG. 1
taken along the line II-II'.
[0037] A plurality of gate lines 121 for transmitting gate signals
are formed on an insulating substrate 110. Each gate line 121
extends substantially in a transverse direction and a plurality of
upwardly protruding portions of each gate line 121 form a plurality
of gate electrodes 123. The gate electrodes 123 include two gate
members 1231 and 1232. Each gate line 121 includes a plurality of
expansions protruding downward.
[0038] The gate lines 121 include two films having different
physical characteristics, a lower film 201 and an upper film 202.
The upper film 202 is preferably made of low resistivity metal
including Al containing metal such as Al and Al alloy for reducing
signal delay or voltage drop in the gate lines 121. On the other
hand, the lower film 201 is preferably made of material such as Cr,
Mo and Mo alloy having good contact characteristics with other
materials such as ITO (indium tin oxide) or IZO (indium zinc
oxide). A good exemplary combination of the lower film material and
the upper film material is Cr and Al--Nd alloy.
[0039] The lateral sides of the upper film 202 and the lower film
201 are tapered, and the inclination angle of the lateral sides
with respect to a surface of the substrate 110 ranges about 30-80
degrees.
[0040] A gate insulating layer 140 preferably made of silicon
nitride (SiNx) is formed on the gate lines 121.
[0041] A plurality of semiconductor stripes 150 preferably made of
hydrogenated amorphous silicon (abbreviated to "a-Si") are formed
on the gate insulating layer 140. Each semiconductor stripe 150
extends substantially in a longitudinal direction and has a
plurality of projections branched out toward the gate electrodes
123. Each semiconductor stripe 150 includes two semiconductor
members 1501 and 1502. The width of each semiconductor stripe 150
becomes large near the gate lines 121 such that the semiconductor
stripe 150 covers large areas of the gate lines 121.
[0042] A plurality of ohmic contact stripes and islands 163 and 165
preferably made of silicide or n+hydrogenated a-Si heavily doped
with n type impurity are formed on the semiconductor stripes 150.
Each ohmic contact stripe 163 has a plurality of projections, and
the projections and the ohmic contact islands 165 are located in
pairs on the projections of the semiconductor stripes 150.
[0043] The lateral sides of the semiconductor stripes 150 and the
ohmic contacts 163 and 165 are tapered, and the inclination angles
thereof are preferably in a range between about 30-80 degrees.
[0044] A plurality of data lines 171, a plurality of drain
electrodes 175, and a plurality of storage capacitor conductors 177
are formed on the ohmic contacts 163 and 165 and the gate
insulating layer 140.
[0045] The data lines 171 for transmitting data voltages extend
substantially in the longitudinal direction and intersect the gate
lines 121. A plurality of branches 1731 and 1732 of each data line
171, which project toward the drain electrodes 175, form a
plurality of source electrodes 173. Each drain electrode 175 has
two drain members 1751 and 1752 extending parallel to each other in
the transverse direction and located on the gate electrode 123, and
each source electrode 173 has three branches 1731 and 1732 forming
two source members 173a and 173b having a semicircle shape partly
surrounding the respective drain members 1751 and 1752 of the drain
electrode 175. The branches 1731 and 1732 extend substantially
parallel to the drain members 1751 and 1752 in the transverse
direction. The source members 173a and 173b of a source electrode
173, the drain members 1751 and 1752 of a drain electrode 175, the
gate members 1231 and 1232 of a gate electrode 123 located
therebetween along with the semiconductor members 1501 and 1502 of
a semiconductor stripe 150 and portions 1631, 1632, 1651 and 1652
form twin TFTs TFT1 and TFT2 connected in parallel. The planar
shape of the twin TFTs TFT1 and TFT2 are symmetrical to the middle
branch 1732 of the source electrode 173. Since twin transistors
TFT1 and TFT2 have U shaped channels, their channel widths are
increased such that they have high current driving capacity.
[0046] The storage capacitor conductors 177 overlap the expansions
of the gate lines 121.
[0047] The data lines 171, the drain electrodes 175, and the
storage capacitor conductors 177 include a conductive film
preferably made of Mo, Mo alloy, Cr, Al, Al alloy, Al or Al alloy.
However, they may have triple-layered structure including (1) Mo or
Mo ally, (2) Al, and (3) Mo or Mo alloy.
[0048] Like the gate lines 121, the data lines 171, the drain
electrodes 175, and the storage capacitor conductors 177 have
tapered lateral sides, and the inclination angles thereof range
about 30-80 degrees.
[0049] The ohmic contacts 163 and 165 are interposed only between
the underlying semiconductor stripes 150 and the overlying data
lines 171 and the overlying drain electrodes 175 thereon and reduce
the contact resistance therebetween. The semiconductor stripes 150
include a plurality of exposed portions, which are not covered with
the data lines 171 and the drain electrodes 175, such as portions
located between the source electrodes 173 and the drain electrodes
175. Although the semiconductor stripes 150 are narrower than the
data lines 171 at most places, the width of the semiconductor
stripes 150 becomes large near the gate lines as described above,
to enhance the insulation between the gate lines 121 and the data
lines 171.
[0050] A passivation layer 180 is formed on the data lines 171, the
drain electrodes 175, the storage conductors 177, and the exposed
portions of the semiconductor stripes 150. The passivation layer
180 is preferably made of photosensitive organic material having a
good flatness characteristic, low dielectric insulating material
such as a-Si:C:O and a-Si:O:F formed by plasma enhanced chemical
vapor deposition (PECVD), or inorganic material such as silicon
nitride. The passivation layer 180 may have a double-layered
structure including an inorganic lower film and an organic upper
film. In this case, the organic film is preferably removed from pad
areas provided with end portions of the gate pads 125 and the data
pads 179, and this configuration is specifically advantageous to a
COG (chip on glass) type LCD including gate driving ICs and data
driving ICs directly mounted on a TFT array panel.
[0051] The passivation layer 180 has a plurality of contact holes
185, 187 and 189 exposing the drain electrodes 175, the storage
conductors 177, and end portions 179 of the data lines 171,
respectively. The passivation layer 180 and the gate insulating
layer 140 have a plurality of contact holes 182 exposing end
portions 125 of the gate lines 121.
[0052] The contact holes 182, 185, 187 and 189 expose the gate
lines 121, the data lines 171, the drain electrodes 175, and the
storage capacitor conductors 177, respectively.
[0053] A plurality of pixel electrodes 190 and a plurality of
contact assistants 92 and 97, which are preferably made of
transparent conductive material such as ITO and IZO or reflective
conductive material such as Al and Ag, are formed on the
passivation layer 180.
[0054] The pixel electrodes 190 are physically and electrically
connected to the drain electrodes 175 through the contact holes 185
and to the storage capacitor conductors 177 through the contact
holes 187 such that the pixel electrodes 190 receive the data
voltages from the drain electrodes 175 and transmit the received
data voltages to the storage capacitor conductors 177. The pixel
electrodes 190 supplied with the data voltages generate electric
fields in cooperation with a common electrode (not shown) on an
opposite panel (not shown), which reorient liquid crystal molecules
in the liquid crystal layer disposed therebetween.
[0055] The pixel electrode 190 and the common electrode form a
liquid crystal capacitor C.sub.LC, which stores applied voltages
after turn-off of the TFT Q. An additional capacitor called a
"storage capacitor," which is connected in parallel to the liquid
crystal capacitor C.sub.LC, is provided for enhancing the voltage
storing capacity. The storage capacitors are implemented by
overlapping the pixel electrodes 190 with the gate lines 121
adjacent thereto (called "previous gate lines"). The capacitances
of the storage capacitors, i.e., the storage capacitances are
increased by providing the expansions at the gate lines 121 for
increasing overlapping areas and by providing the storage capacitor
conductors 177, which are connected to the pixel electrodes 190 and
overlap the expansions, under the pixel electrodes 190 for
decreasing the distance between the terminals.
[0056] The pixel electrodes 190 overlap the gate lines 121 and the
data lines 171 to increase aperture ratio but it is optional.
[0057] The contact assistants 92 and 97 are connected to the
exposed end portions 125 of the gate lines 121 and the exposed end
portions 179 of the data lines 171 through the contact holes 182
and 189, respectively. The contact assistants 92 and 97 are not
requisites but preferred to protect the exposed portions 125 and
179 and to complement the adhesiveness of the exposed portion 125
and 179 and external devices.
[0058] An LCD according to an embodiment of the present invention
includes a TFT array panel shown in FIGS. 1 and 2, a common
electrode panel (not shown) facing the TFT array panel with a
predetermined gap, and a liquid crystal layer (not shown) filled in
the gap between the TFT array panel and the common electrode
panel.
[0059] The liquid crystal layer may be aligned in a twisted nematic
(TN) mode where liquid crystal molecules in the liquid crystal
layer are aligned parallel to surfaces of the panels and rotate
along a direction normal to the surfaces of the panels in the
absence of electric field. Alternatively, the liquid crystal layer
may be aligned in a vertically aligned (VA) mode where the liquid
crystal molecules are aligned vertical to the surfaces of the
panels in the absence of electric field.
[0060] The LCD further includes one or two polarizers attached to
the panels and it optionally includes one or more retardation
films.
[0061] A method of manufacturing the TFT array panel shown in FIGS.
1 and 2 according to an embodiment of the present invention will be
now described in detail with reference to FIGS. 3A to 6B as well as
FIGS. 1 and 2.
[0062] FIGS. 3A, 4A, 5A and 6A are layout views of the TFT array
panel shown in FIGS. 1 and 2 in intermediate steps of a
manufacturing method thereof according to an embodiment of the
present invention, and FIGS. 3B, 4B, 5B and 6B are sectional views
of the TFT array panel shown in FIGS. 3A, 4A, 5A and 6A taken along
the lines IIIB-IIIB', IVB-IVB', VB-VB' and VIB-VIB',
respectively.
[0063] Referring to FIGS. 3A and 3B, two conductive films, a lower
conductive film 201 and an upper conductive film 202 are sputtered
in sequence on an insulating substrate 110 such as transparent
glass. The lower conductive film 201 is preferably made of Al, and
preferably has a thickness of about 2,000 .ANG.-4,000 .ANG.. The
upper conductive film 202 is preferably made of Mo, Mo alloy and
Cr, and preferably has a thickness of about 500 .ANG.-2,000
.ANG..
[0064] The upper conductive film 202 and the lower conductive film
201 are patterned in sequence using step and repeat divisional
photolithography to form a plurality of gate lines 121 including a
plurality of gate electrodes 123 and a plurality of expansions. The
boundary line BL of the shots in the divisional exposure extends
substantially in a transverse direction.
[0065] Referring to FIGS. 4A and 4B, after sequential deposition of
a gate insulating layer 140, an intrinsic a-Si layer, and an
extrinsic a-Si layer, the extrinsic a-Si layer and the intrinsic
a-Si layer are patterned by using step and repeat divisional
photolithography to form a plurality of extrinsic semiconductor
stripes 168 and a plurality of intrinsic semiconductor stripes 150
on the gate insulating layer 140. Like the previous step, the
boundary line BL of the shots in the divisional exposure extends
substantially in the transverse direction.
[0066] Referring to FIGS. 5A and 5B, a metal film is sputtered and
photo-etched by using divisional exposure to form a plurality of
data lines 171 including a plurality of source electrodes 173 with
a plurality of branches 1731 and 1732 extending substantially in
the transverse direction, a plurality of drain electrodes 175
including a plurality of projections 1751 and 1752 extending
substantially in the transverse direction, and a plurality of
storage capacitor conductors 177. Like the previous steps, the
boundary line BL of the shots in the divisional exposure extends
substantially in the transverse direction such that it is parallel
to the extension directions of the branches 1731 and 1732 and the
projections 1751 and 1752. In addition, the boundary line BL is
located on middle branches 1732 of the source electrodes 173.
[0067] Thereafter, portions of the extrinsic semiconductor stripes
168, which are not covered with the data lines 171, the drain
electrodes 175, and the storage capacitor conductors 177, are
removed to complete a plurality of ohmic contact stripes 1631 and
1632 including a plurality of projections and a plurality of ohmic
contact islands 1651 and 1652 and to expose portions of the
intrinsic semiconductor stripes 150. Oxygen plasma treatment
preferably follows thereafter in order to stabilize the exposed
surfaces of the semiconductor stripes 150.
[0068] As shown in FIGS. 6A and 6B, after depositing a passivation
layer 180, the passivation layer 180 and the gate insulating layer
140 are dry-etched using photolithography to form a plurality of
contact holes 182, 185, 187 and 189 exposing end portions 125 of
the gate lines 121, the drain electrodes 175, the storage capacitor
conductors 177, and end portions 179 of the data lines 171,
respectively. When the gate lines 121, the drain electrodes 175,
the storage capacitor conductors 177, and the data lines 171 have a
multi-layered structure including Al, it is preferable not to
expose Al in consideration of the contact with ITO or IZO.
[0069] Finally, as shown in FIGS. 1 and 2, a plurality of pixel
electrodes 190 and a plurality of contact assistants 92 and 97 are
formed on the passivation layer 180 by sputtering and photo-etching
an ITO or IZO layer with a thickness of about 900 .ANG.. Like the
previous steps, the boundary line BL of the shots in the divisional
exposure extends substantially in the transverse direction.
[0070] As described above, all the boundary lines BL in the
above-described steps extend substantially in the transverse
direction such that they are parallel to the extension directions
of the branches 1731 and 1732 and the projections 1751 and 1752. In
addition, the boundary lines BL are located on middle branches 1732
of the source electrodes 173. Then, the twin TFTs are substantially
symmetrical to the boundary lines BL and thus the deviation of the
boundary lines BL between the shots, particularly in the
longitudinal direction, may not make result in significant
deviation of the parasitic capacitances between the conductive
members such as the gate lines 121 including the gate electrodes
121, the data lines 171 including the source electrodes 173, the
drain electrodes 175, and the pixel electrodes 190.
[0071] The twin TFT configuration may be partly applied to the TFT
array panel. In particular, the twin TFTs are located near the
boundaries BL between the shots.
[0072] A TFT array panel for an LCD according to another embodiment
of the present invention will be described in detail with reference
to FIGS. 7-9.
[0073] FIG. 7 is a layout view of an exemplary TFT array panel for
an LCD according to another embodiment of the present invention,
and FIGS. 8 and 9 are sectional views of the TFT array panel shown
in FIG. 7 taken along the line VIII-VIII' and the line IX-IX',
respectively.
[0074] As shown in FIGS. 7-9, a layered structure of a TFT array
panel of an LCD according to this embodiment is almost the same as
that shown in FIGS. 1 and 2. That is, a plurality of gate lines 121
including a plurality of gate electrodes 123 are formed on a
substrate 110, and a gate insulating layer 140, a plurality of
semiconductor stripes 152 including a plurality of projections, and
a plurality of ohmic contact stripes 163 including a plurality of
projections and a plurality of ohmic contact islands 165 are
sequentially formed thereon. A plurality of data lines 171
including a plurality of source electrodes 173 and a plurality of
drain electrodes 175 are formed on the ohmic contacts 163 and 165,
and a passivation layer 180 is formed thereon. A plurality of
contact holes 182, 185 and 189 are provided at the passivation
layer 180 and/or the gate insulating layer 140, and a plurality of
pixel electrodes 190 and a plurality of contact assistants 92 and
97 are formed on the passivation layer 180.
[0075] Different from the TFT array panel shown in FIGS. 1 and 2,
the TFT array panel according to this embodiment provides a
plurality of storage electrode lines 131, which are separated from
the gate lines 121, on the same layer as the gate lines 121, and
overlaps the storage electrode lines 131 with the drain electrodes
175 to form storage capacitors without expansions of the gate lines
121 and the storage capacitor conductors 177. The storage electrode
lines 131 are supplied with a predetermined voltage such as the
common voltage. The storage electrode lines 131 may be omitted if
the storage capacitance generated by the overlapping of the gate
lines 121 and the pixel electrodes 190 is sufficient.
[0076] In addition, the planar shapes of twin TFTs TFT1 and TFT2
are substantially symmetrical with respect to a longitudinal line.
In detail, each source electrode 173 includes a pair of portions
1731 and 1732 forming a pair of parentheses and a connecting
portion connecting the portions 1731 and 1732. Each drain electrode
175 has two projections extending toward the centers of the
parentheses.
[0077] Furthermore, the gate lines 121 in this embodiment have a
single-layered structure.
[0078] The semiconductor stripes 152 have almost the same planar
shapes as the data lines 171 and the drain electrodes 175 as well
as the underlying ohmic contacts 163 and 165, except for the
projections where TFTs are provided. In detail, the semiconductor
stripes 152 have substantially the same planar shape as the data
lines 171 and the drain electrodes 175, except for portions located
between the source electrodes 173 and the drain electrodes 175.
[0079] Now, a method of manufacturing the TFT array panel shown in
FIGS. 7-9 according to an embodiment of the present invention will
be described in detail with reference to FIGS. 10A-16 C as well as
FIGS. 7-9.
[0080] FIG. 10A is a layout view of a TFT array panel shown in
FIGS. 7-9 in the first step of a manufacturing method thereof
according to an embodiment of the present invention; FIGS. 10B and
10C are sectional views of the TFT array panel shown in FIG. 10A
taken along the lines XB-XB' and XC-XC', respectively; FIGS. 11A
and 11B are sectional views of the TFT array panel shown in FIG.
10A taken along the lines XB-XB' and XC-XC', respectively, and
illustrate the step following the step shown in FIGS. 10B and 10C;
FIG. 12A is a layout view of the TFT array panel in the step
following the step shown in FIGS. 11A and 11B; FIGS. 12B and 12C
are sectional views of the TFT array panel shown in FIG. 12A taken
along the lines XIIB-XIIB' and XIIC-XIIC', respectively; FIGS. 13A,
14A and 15A and FIGS. 13B, 14B and 15B are respective sectional
views of the TFT array panel shown in FIG. 12A taken along the
lines XIIB-XIIB' and XIIC-XIIC', respectively, and illustrate the
steps following the step shown in FIGS. 12B and 12C; FIG. 16A is a
layout view of a TFT array panel in the step following the step
shown in FIGS. 15A and 15B; and FIGS. 16B and 16C are sectional
views of the TFT array panel shown in FIG. 16A taken along the
lines XVIB-XVIB' and XVIC-XVIC', respectively.
[0081] Referring to FIGS. 10A-10C, a plurality of gate lines 121
including a plurality of gate electrodes 123 and a plurality of
storage electrode lines 131 are formed on a substrate 110 by photo
etching with division exposure.
[0082] As shown in FIGS. 11A and 11B, a gate insulating layer 140,
an intrinsic a-Si layer 150, and an extrinsic a-Si layer 160 are
sequentially deposited by CVD such that the layers 140, 150 and 160
bear thickness of about 1,000 .ANG., about 500-2,000 .ANG. and
about 300-600 .ANG., respectively. A conductive layer 170 having a
thickness of about 1,500 .ANG. to 3,000 .ANG. is deposited by
sputtering, and a photoresist film 210 with the thickness of about
1-2 microns is coated on the conductive layer 170.
[0083] The photoresist film 210 is exposed to light through an
exposure mask (not shown) by step and repeat process, and developed
such that the developed photoresist has a position dependent
thickness. The photoresist shown in FIGS. 12B and 12C includes a
plurality of first to third portions with decreased thickness. The
first portions 212 located on wire areas A and the second portions
214 located on channel areas C are indicated by reference numerals
212 and 214, respectively, and no reference numeral is assigned to
the third portions located on remaining areas B since they have
substantially zero thickness to expose underlying portions of the
conductive layer 170. The thickness ratio of the second portions
214 to the first portions 212 is adjusted depending upon the
process conditions in the subsequent process steps. It is
preferable that the thickness of the second portions 214 is equal
to or less than half of the thickness of the first portions 212,
and in particular, equal to or less than 4,000 .ANG..
[0084] The position-dependent thickness of the photoresist is
obtained by several techniques, for example, by providing
translucent areas on the exposure mask as well as transparent areas
and light blocking opaque areas. The translucent areas may have a
slit pattern, a lattice pattern, a thin film(s) with intermediate
transmittance or intermediate thickness. When using a slit pattern,
it is preferable that the width of the slits or the distance
between the slits is smaller than the resolution of a light exposer
used for the photolithography. Another example is to use reflowable
photoresist. In detail, once a photoresist pattern made of a
reflowable material is formed by using a normal exposure mask only
with transparent areas and opaque areas, it is subject to reflow
process to flow onto areas without the photoresist, thereby forming
thin portions.
[0085] The different thickness of the photoresist 212 and 214
enables to selectively etch the underlying layers when using
suitable process conditions. Therefore, a plurality of data lines
171 including a plurality of source electrodes 173 and a plurality
of drain electrodes 175 as well as a plurality of ohmic contact
stripes 163 including a plurality of projections, a plurality of
ohmic contact islands 165, and a plurality of semiconductor stripes
152 including a plurality of projections are obtained by a series
of etching steps as shown in FIG. 12A.
[0086] For descriptive purpose, portions of the conductive layer
170, the extrinsic a-Si layer 160, and the intrinsic a-Si layer 150
on the wire areas A are called first portions, portions of the
conductive layer 170, the extrinsic a-Si layer 160, and the
intrinsic a-Si layer 150 on the channel areas C are called second
portions, and portions of the conductive layer 170, the extrinsic
a-Si layer 160, and the intrinsic a-Si layer 150 on the remaining
areas B are called third portions.
[0087] An exemplary sequence of forming such a structure is as
follows:
[0088] (1) Removal of third portions of the conductive layer 170,
the extrinsic a-Si layer 160 and the intrinsic a-Si layer 150 on
the wire areas A;
[0089] (2) Removal of the second portions 214 of the
photoresist;
[0090] (3) Removal of the second portions of the conductive layer
170 and the extrinsic a-Si layer 160 on the channel areas C;
and
[0091] (4) Removal of the first portions 212 of the
photoresist.
[0092] Another exemplary sequence is as follows:
[0093] (1) Removal of the third portions of the conductive layer
170;
[0094] (2) Removal of the second portions 214 of the
photoresist;
[0095] (3) Removal of the third portions of the extrinsic a-Si
layer 160 and the intrinsic a-Si layer 150;
[0096] (4) Removal of the second portions of the conductive layer
170;
[0097] (5) Removal of the first portions 212 of the photoresist;
and
[0098] (6) Removal of the second portions of the extrinsic a-Si
layer 160.
[0099] The first example is described in detail.
[0100] As shown in FIGS. 13A and 13B, the exposed third portions of
the conductive layer 170 on the remaining areas B are removed by
wet or dry etching to expose the underlying third portions of the
extrinsic a-Si layer 160.
[0101] Reference numeral 178 indicates portions of the conductive
layer 170 including the data lines 171 and the drain electrode 175
connected to each other. The dry etching may etch out the top
portions of the photoresist 212 and 214.
[0102] Referring to FIGS. 14A and 14B, the third portions of the
extrinsic a-Si layer 160 on the areas B and of the intrinsic a-Si
layer 150 are removed preferably by dry etching and the second
portions 214 of the photoresist are removed to expose the second
portions of the conductors 178. The removal of the second portions
214 of the photoresist are performed either simultaneously with or
independent from the removal of the third portions of the extrinsic
a-Si layer 160 and of the intrinsic a-Si layer 150. For example, a
gas mixture of SF.sub.6 and HCL or SF.sub.6 and O.sub.2, which has
almost equal etching ratio for photoresist and amorphous silicon,
is suitable for simultaneous etching of the second portions 214 of
the photoresist and the third portions of the extrinsic a-Si layer
160 and of the intrinsic a-Si layer 150. Residue of the second
portions 214 of the photoresist remained on the channel areas C is
removed by ashing.
[0103] The semiconductor stripes 152 are completed in this step,
and reference numeral 168 indicates portions of the extrinsic a-Si
layer 160 including the ohmic contact stripes and islands 163 and
165 connected to each other, which are called "extrinsic
semiconductor stripes."
[0104] As shown in FIGS. 15A and 15B, the second portions of the
conductors 178 and the extrinsic a-Si stripes 168 on the channel
areas C as well as the first portion 212 of the photoresist are
removed.
[0105] As shown in FIG. 15B, top portions of the projections of the
intrinsic semiconductor stripes 152 on the channel areas C may be
removed to cause thickness reduction, and the first portions 212 of
the photoresist are etched to a predetermined thickness. A gas
mixture including CF.sub.4 and O.sub.2 may enable to make remaining
portions of the intrinsic semiconductor stripes 152 on the channel
areas C have uniform thickness.
[0106] In this way, each conductor 178 is divided into a data line
171 and a plurality of drain electrodes 175 to be completed, and
each extrinsic semiconductor stripe 168 is divided into an ohmic
contact stripe 163 and a plurality of ohmic contact islands 165 to
be completed.
[0107] Next, a passivation layer 180 is formed by
chemical-vapor-depositing silicon nitride at a temperature in a
range of about 250-1500.degree. C., by growing low dielectric
material such as a-Si:C:O or a-Si:O:F, by CVD of silicon nitride,
or by coating an organic insulating material such as acryl-based
material having a good planarization characteristic. Referring to
FIGS. 16A and 16B, the passivation layer 180 as well as the gate
insulating layer 140 is photo-etched to form a plurality of contact
holes 182, 185 and 189.
[0108] Finally, as shown in FIGS. 7-9, an ITO or IZO layer with a
thickness in a range between about 500 .ANG. and about 1,000 .ANG.
is sputtered and photo-etched with divisional light exposure to
form a plurality of pixel electrodes 190 and a plurality of contact
assistants 92 and 97.
[0109] The boundaries BL in each divisional light exposure extend
in the longitudinal direction such that they pass through the
center of the twin TFTs TFT1 and TFT2. Accordingly, the deviation
of the boundary lines BL between the shots may not make result in
significant deviation of the parasitic capacitances between the
conductive members since the twin TFTs are substantially
symmetrical to the boundary lines BL.
[0110] This embodiment simplifies the manufacturing process by
forming the data lines 171 and the drain electrodes 175 as well as
the ohmic contacts 163 and 165 and the semiconductor stripes 152
using a single photolithography step.
[0111] While the present invention has been described in detail
with reference to the preferred embodiments, those skilled in the
art will appreciate that various modifications and substitutions
can be made thereto without departing from the spirit and scope of
the present invention as set forth in the appended claims.
* * * * *