U.S. patent application number 11/496843 was filed with the patent office on 2006-12-07 for semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry.
Invention is credited to Charles H. Dennison.
Application Number | 20060273459 11/496843 |
Document ID | / |
Family ID | 22519198 |
Filed Date | 2006-12-07 |
United States Patent
Application |
20060273459 |
Kind Code |
A1 |
Dennison; Charles H. |
December 7, 2006 |
Semiconductor processing methods of forming contact openings,
methods of forming electrical connections and interconnections, and
integrated circuitry
Abstract
Methods of forming contact openings, making electrical
interconnections, and related integrated circuitry are described.
Integrated circuitry formed through one or more of the inventive
methodologies is also described. In one implementation, a
conductive runner or line having a contact pad with which
electrical communication is desired is formed over a substrate
outer surface. A conductive plug is formed laterally proximate the
contact pad and together therewith defines an effectively widened
contact pad. Conductive material is formed within a contact opening
which is received within insulative material over the effectively
widened contact pad. In a preferred implementation, a pair of
conductive plugs are formed on either side of the contact pad
laterally proximate thereof. The conductive plug(s) can extend away
from the substrate outer surface a distance which is greater or
less than a conductive line height of a conductive line adjacent
which the plug is formed. In the former instance and in accordance
with one aspect, such plug(s) can include a portion which overlaps
with the contact pad of the associated conductive line.
Inventors: |
Dennison; Charles H.;
(Meridian, ID) |
Correspondence
Address: |
WELLS ST. JOHN P.S.
601 W. FIRST AVENUE, SUITE 1300
SPOKANE
WA
99201
US
|
Family ID: |
22519198 |
Appl. No.: |
11/496843 |
Filed: |
July 31, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11218004 |
Sep 1, 2005 |
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11496843 |
Jul 31, 2006 |
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10268737 |
Oct 9, 2002 |
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11218004 |
Sep 1, 2005 |
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09565197 |
May 4, 2000 |
6476490 |
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10268737 |
Oct 9, 2002 |
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09146840 |
Sep 3, 1998 |
6242302 |
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09565197 |
May 4, 2000 |
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Current U.S.
Class: |
257/734 ;
257/E23.019 |
Current CPC
Class: |
H01L 21/76895 20130101;
H01L 21/76897 20130101; H01L 2924/0002 20130101; H01L 21/76802
20130101; H01L 23/5226 20130101; H01L 23/485 20130101; H01L
2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/734 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Claims
1-51. (canceled)
52. Integrated circuitry comprising: a semiconductive substrate
having an outer surface; a conductive line disposed over the outer
surface and having a conductive portion which defines a contact pad
with which electrical connection is desired; at least one
conductive plug disposed laterally proximate the contact pad and
having a plug portion disposed elevationally over a portion of the
contact pad; and conductive material disposed over the contact pad
and in electrical communication with at least a portion of the
conductive plug.
53. Integrated circuitry comprising: a semiconductive substrate
having an outer surface; a conductive line disposed over the outer
surface and having a first line width at one location and a second
line width which is different from the first line width at another
location; at least a portion of the second line width defining a
contact pad with which electrical connection is desired; a
conductive plug disposed laterally proximate the contact pad and
defining therewith an effective contact pad having an effective
contact pad width which is greater than the second line width; and
conductive material disposed over the effective contact pad and
making electrical connection with at least a portion of the
conductive plug.
54. Integrated circuitry comprising: a semiconductive substrate
having an outer surface; a conductive line disposed over the outer
surface and having a conductive line width and a target area with
which electrical communication is desired; a pair of conductive
plugs disposed over the outer surface on either side of the
conductive line laterally proximate the target area and
self-aligned to the substrate adjacent the conductive line, the
plugs and target area defining an effectively widened target area;
and conductive material disposed over and in electrical
communication with at least a portion of the effectively widened
target area which includes the conductive line target area.
Description
TECHNICAL FIELD
[0001] This invention relates to semiconductor processing methods
of forming contact openings, methods of forming electrical
connections and interconnections, and integrated circuitry
comprising such contact openings and electrical connections and
interconnections.
BACKGROUND OF THE INVENTION
[0002] Referring to FIGS. 1 and 2, a semiconductor wafer fragment
is indicated generally at 10 and comprises a semiconductive
substrate 12. In the context of this document, the term
"semiconductive substrate" is defined to mean any construction
comprising semiconductive material, including, but not limited to,
bulk semiconductive materials such as a semiconductive wafer
(either alone or in assemblies comprising other materials thereon),
and semiconductive material layers (either alone or in assemblies
comprising other materials). The term "substrate" refers to any
supporting structure, including, but not limited to, the
semiconductive substrates described above. Substrate 12 comprises a
field oxide region 13 having an outer surface 14 (FIG. 2) over
which a plurality of conductive runners or conductive lines 16, 18,
and 20 are formed. The illustrated conductive lines or runners
include conductive portions and insulative portions. Exemplary
conductive portions are constituted, in this example, by a
respective polysilicon layer 22 and an overlying silicide layer 24.
The insulative portions of the runners or lines are constituted by
respective overlying caps 26 and associated sidewall spacers 28.
Exemplary materials for the insulative portions include oxides and
nitrides.
[0003] An insulative layer 30 such as borophosphosilicate glass is
formed over runners 16, 18, and 20 and a contact opening 32 is
formed through a masked etch of layer 30 to outwardly expose a
portion of silicide layer 24. Thereafter, conductive material such
as conductively doped polysilicon is formed within contact opening
32 to provide a conductive contact 34 to conductive line 18. A
metal layer 36 is provided thereover to form an electrical
connection with conductive line 18.
[0004] A typical practice within the semiconductor industry is to
provide a conductive line or runner with a widened landing pad in
order to accommodate mask misalignments when contact openings are
formed. An exemplary widened landing pad is shown in FIGS. 1 and 2
at 38. By having a widened landing pad, contact opening 32 can
shift left or right some distance relative to the position shown in
FIGS. 1 and 2 without making undesirable contact with the
substrate. For purposes of the ongoing discussion, landing pad 38
includes the conductive and insulative portions of conductive line
18; and the conductive portions of conductive line 18 define a
contact pad with which electrical communication is desired.
Accordingly, in the illustrated example a contact pad is defined by
polysilicon layer 22 and silicide layer 24 of conductive line 18.
The contact pad defines a target area A inside of which it is
desirable to form a contact opening. An electrical connection
through contact opening 32 can be formed anywhere within target
area A and still effectively make a desirable connection with the
conductive contact pad. Hence, the target area tolerates a contact
opening mask misalignment on either side of the illustrated and
desired contact opening 32. A tradeoff for improved mask
misalignment tolerance is a reduction in wafer real estate
available for supporting conductive lines and other integrated
circuitry components. This is due largely in part to the increased
area which is occupied by the widened landing pad 38. This also
adversely impacts the conductive line spacing such that desired
minimum spacing adjacent conductive lines is not achieved. Hence,
integrated circuitry cannot be packed as densely upon a wafer as is
desirable when the widened landing pads are used.
[0005] This invention grew out of concerns associated with
enhancing the efficiency with which wafer real estate is used to
support integrated circuitry. This invention also grew out of
concerns associated with improving the methods and structures
through which contact is made relative to conductive lines.
SUMMARY OF THE INVENTION
[0006] Methods of forming contact openings, making electrical
interconnections, and related integrated circuitry are described.
Integrated circuitry formed through one or more of the inventive
methodologies is also described. In one implementation, a
conductive runner or line having a contact pad with which
electrical communication is desired is formed over a substrate
outer surface. A conductive plug is formed laterally proximate the
contact pad and together therewith defines an effectively widened
contact pad. Conductive material is formed within a contact opening
which is received within insulative material over the effectively
widened contact pad. In a preferred implementation, a pair of
conductive plugs are formed on either side of the contact pad
laterally proximate thereof. The conductive plug(s) can extend away
from the substrate outer surface a distance which is greater or
less than a conductive line height of a conductive line adjacent
which the plug is formed. In the former instance and in accordance
with one aspect, such plug(s) can include a portion which overlaps
with the contact pad of the associated conductive line.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Preferred embodiments of the invention are described below
with reference to the following accompanying drawings.
[0008] FIG. 1 is a top plan view of a prior art semiconductor wafer
fragment and a plurality of conductive lines supported thereon.
[0009] FIG. 2 is a view which is taken along line 2-2 in FIG. 1 at
a subsequent processing step.
[0010] FIG. 3 is a diagrammatic sectional view of a semiconductor
wafer fragment at one processing step in accordance with one
implementation of the invention.
[0011] FIG. 4 is a view of the FIG. 3 wafer fragment at another
processing step.
[0012] FIG. 5 is a view of the FIG. 3 wafer fragment at another
processing step.
[0013] FIG. 6 is a view of the FIG. 3 wafer fragment at another
processing step.
[0014] FIG. 7 is a view which is similar to the FIG. 6 view, but
which shows an alternate embodiment in accordance with another
implementation of the invention.
[0015] FIG. 8 is a view of the FIG. 3 wafer fragment at another
processing step.
[0016] FIGS. 9 and 10 are top plan views of semiconductor wafer
fragments which have been processed in accordance with the
inventive methodologies.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0017] This disclosure of the invention is submitted in furtherance
of the constitutional purposes of the U.S. Patent Laws "to promote
the progress of science and useful arts" (Article 1, Section
8).
[0018] Referring to FIG. 3, like numerals from the above-described
embodiment are utilized where appropriate, with differences being
indicated by the suffix "a" or with different numerals.
Accordingly, a plurality of conductive runners or lines 16a, 18a,
and 20a are formed over outer surface 14, and can be formed over
oxide isolation regions 40. Exemplary isolation regions include
shallow trench isolation regions or field oxide regions formed
through LOCOS techniques. The conductive lines comprise respective
outermost surfaces 44 portions of which define respective
conductive line heights h outwardly of outer surface 14. Diffusion
regions 42 can be provided between the conductive lines, and
preferably comprise n-regions having doping concentrations of
1.times.10.sup.18 cm.sup.-3. The diffusion regions can be provided
in a separate doping step, or through outdiffusion of dopant from
conductive material which will become more apparent below. An outer
contact opening target area B is defined by conductive line
18a.
[0019] Referring to FIG. 4, an insulating material layer 46 is
formed over substrate 12. An exemplary material is
borophosphosilicate glass.
[0020] Referring to FIG. 5, at least one, and preferably a pair of
contact openings 48, 50 are formed through layer 46 and preferably
outwardly expose respective portions of outer surface 14. The
contact openings can be formed through a suitable masked etch of
layer 46. Preferably, the individual contact openings are
essentially self-aligned at and to the substrate at two locations
48a, 48b, and 50a, 50b respectively, along a line extending
laterally from conductive runner or line 18a. In a preferred
implementation, one of the two locations for the individual contact
openings is defined by conductive runner 18a. Even more preferably,
the other of the two respective locations are defined by respective
next adjacent conductive lines 16a, 20a.
[0021] Referring to FIG. 6, and in accordance with a first
implementation, first conductive material 52, 54 is formed within
contact openings 48, 50, between the illustrated conductive lines
and laterally proximate or adjacent the contact pad defined by
conductive line 18a. An exemplary and preferred first conductive
material is conductively doped polysilicon, which can serve as a
source of outdiffused dopant for regions 42. The polysilicon can be
chemical vapor deposited over the substrate and subsequently
removed through conventional processing to provide conductive plugs
56, 58. Such conventional processing can include planarization
processing to isolate conductive material within the respective
contact openings, followed by a suitable timed etch to recess the
conductive material within the contact openings. In the illustrated
example, conductive plugs are formed on both sides of conductive
line 18a. It is possible, however, for only one conductive plug to
be formed on either side of conductive line 18a. The individual
conductive plugs are essentially self-aligned at and to the
substrate at the same locations as are the contact openings in
which each is formed.
[0022] Referring still to FIG. 6, the illustrated conductive plugs
are formed to preferably extend outwardly from outer surface 14 a
distance which is greater than conductive runner height h. Because
the plugs in this example are formed atop the same surface (outer
surface 14) atop which the conductive lines are formed, each
extends elevationally beyond the respective conductive line
heights. Such plugs could, however, be formed to extend from outer
surface 14 a distance which is less than or no further than the
conductive runner height. This could, for example, be done by
conducting a timed etch for a longer period of time than is
suitable for forming the illustrated FIG. 6 plugs. An exemplary
construction is shown in FIG. 7.
[0023] In one implementation, individual conductive plugs include
portions which overlap with portions of conductive line 18a and the
respective next adjacent conductive lines 16a, 20a. In a preferred
implementation, the respective plugs overlap with the outermost
surfaces of the conductive lines adjacent which each is formed.
Accordingly, portions of at least one, and preferably both
conductive plugs can overlap target area B. Collectively, the
conductive material of conductive plugs 56, 58, and the conductive
material of conductive line 18a define an effective contact pad
having an outermost surface 60, which defines an effectively
widened target area A'. The widened target area reduces the wafer
area which was formerly required by the prior art widened landing
pad (FIGS. 1 and 2) described above.
[0024] Alternately considered, effective contact pad outermost
surface 60 defines a generally non-planar surface. In a preferred
implementation, at least one of the conductive plugs, and
preferably both, define a region of outermost surface 60 having a
higher topographical elevation than the region defined by the
contact pad of line 18a.
[0025] Referring to FIG. 8, a layer 62 of insulative material is
formed over the substrate and the effective contact pad. A contact
opening 64 is etched or otherwise formed through layer 62 to
outwardly expose portions of the effective contact pad. Preferably,
the contact pad of line 18a is exposed, with any mask misalignment
resulting in exposure of conductive material of either or both of
conductive plugs 56, 58. Subsequently, a second conductive material
66 is formed within contact opening 64 and in electrical
communication with at least portions of the contact pad and, if
exposed, an associated portion of a conductive plug. A bit line 68
can then be formed over the substrate and in electrical
communication with material 66.
[0026] Referring to FIG. 9, conductive lines 16a, 18a and 20a have
first respective line widths w.sub.1 at respective first locations
and second line widths w.sub.2 at respective second locations, an
exemplary second line width and location being shown for line 18a.
The second line width corresponds to a line location where at least
a portion of contact opening 64 is formed. In one implementation,
the first and second line widths are essentially the same or
equivalent. This is made possible because the above-described
conductive plugs 56, 58 (shown in dashed lines in FIGS. 9 and 10)
reduce, if not eliminate, the requirement of the FIG. 1 widened
landing pad. The illustrated conductive plugs provide an effective
contact pad width which is greater than second line width w.sub.2,
and include respective portions proximate the first line width
w.sub.1 which overlap with or extend elevationally over the
conductive portions, e.g. the contact pad, of line 18a. The plugs
can also include portions which overlap with corresponding portions
of conductive lines 16a, 20a. This compensates for a contact
opening mask misalignment by enabling desired contact to be made
through a respective one of the conductive plugs as discussed
above.
[0027] Referring to FIG. 10 and in accordance with another
implementation, localized first and second line widths w.sub.1,
w.sub.2 respectively, are different with second line width w.sub.2
being greater than first line width w.sub.1. In this example, the
second line width defines a portion of a landing pad which is
smaller in dimension than the FIG. 1 landing pad. Portions of
conductive lines 16b and 20b laterally proximate respective
conductive plugs 56, 58 can be tapered or otherwise configured to
accommodate the somewhat wider landing pad.
[0028] In compliance with the statute, the invention has been
described in language more or less specific as to structural and
methodical features. It is to be understood, however, that the
invention is not limited to the specific features shown and
described, since the means herein disclosed comprise preferred
forms of putting the invention into effect. The invention is,
therefore, claimed in any of its forms or modifications within the
proper scope of the appended claims appropriately interpreted in
accordance with the doctrine of equivalents.
* * * * *