U.S. patent application number 11/500951 was filed with the patent office on 2006-11-30 for semiconductor device and method of fabricating the same.
Invention is credited to Kazuhiko Asakawa, Wataru Shimizu.
Application Number | 20060270249 11/500951 |
Document ID | / |
Family ID | 32923147 |
Filed Date | 2006-11-30 |
United States Patent
Application |
20060270249 |
Kind Code |
A1 |
Asakawa; Kazuhiko ; et
al. |
November 30, 2006 |
Semiconductor device and method of fabricating the same
Abstract
A semiconductor device includes a semiconductor substrate which
has a major surface, and a MOS transistor which has a gate and
first and second diffusion regions and which is formed on the major
surface. The semiconductor device also includes a laminated
structure of an SOG layer, wherein the laminated structure is
composed of a base layer and a surface layer formed on the base
layer. The laminated structure is formed over the MOS transistor,
and the surface layer is denser than the base layer.
Inventors: |
Asakawa; Kazuhiko; (Tokyo,
JP) ; Shimizu; Wataru; (Tokyo, JP) |
Correspondence
Address: |
VOLENTINE FRANCOS, & WHITT PLLC
ONE FREEDOM SQUARE
11951 FREEDOM DRIVE SUITE 1260
RESTON
VA
20190
US
|
Family ID: |
32923147 |
Appl. No.: |
11/500951 |
Filed: |
August 9, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10862331 |
Jun 8, 2004 |
7105464 |
|
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11500951 |
Aug 9, 2006 |
|
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09497499 |
Feb 4, 2000 |
6787886 |
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10862331 |
Jun 8, 2004 |
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Current U.S.
Class: |
438/783 ;
257/632; 257/E21.576; 257/E21.654; 257/E23.134; 257/E27.086 |
Current CPC
Class: |
H01L 21/76802 20130101;
H01L 23/5258 20130101; H01L 2924/0002 20130101; H01L 21/76825
20130101; H01L 21/76801 20130101; H01L 2924/19041 20130101; H01L
27/10873 20130101; H01L 2924/0002 20130101; H01L 23/3192 20130101;
H01L 21/76897 20130101; H01L 27/10808 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
438/783 ;
257/632 |
International
Class: |
H01L 23/58 20060101
H01L023/58; H01L 21/31 20060101 H01L021/31 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 7, 1999 |
JP |
192584/99 |
Claims
1. A semiconductor device comprising: a semiconductor substrate
which has a major surface; an MOS transistor which has a gate and
first and second diffusion regions, the MOS transistor formed on
the major surface; and a laminated structure of an SOG layer, said
laminated structure composed of a base layer and a surface layer
formed on the base layer, and over the MOS transistor, the surface
layer being denser than the base layer.
2. The semiconductor device of claim 1, wherein the laminated
structure has a first contact hole defined therein, the first
contact hole exposing the first diffusion region of the MOS
transistor, wherein a first conductive material is formed within
the first contact hole.
3. The semiconductor device of claim 2, wherein the first diffusion
region is a source or a drain of the MOS transistor.
4. The semiconductor device of claim 2, wherein the laminated
structure has a second contact hole defined therein, the second
contact hole exposing the second diffusion region of the MOS
transistor, wherein a second conductive material is formed within
the second contact hole.
5. The semiconductor device of claim 4, wherein the second
diffusion region is a source or a drain of the MOS transistor.
6. The semiconductor device of claim 5, wherein the first
conductive material is a bit line and the second conductive
material is an electrode of a capacitor.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional application of application Ser. No.
10/862,331, filed Jun. 8, 2004, which is a divisional application
of application Ser. No. 09/497,499, filed Feb. 4, 2000, now U.S.
Pat. No. 6,787,886, which are hereby incorporated by reference in
their entirety for all purposes.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention generally relates to a semiconductor
device and a method of fabricating the same, and more particularly,
to a semiconductor device, such as a semiconductor integrated
circuit device, having Spin On Glass film (it is called hereinafter
SOG film) that is suitable for multilevel interconnection structure
to achieve high integration and a method of fabricating
thereof.
[0004] This application is a counterpart of Japanese patent
application, Serial Number 192584/1999, filed Nov. 7, 1999, the
subject matter of which is incorporated herein by reference.
[0005] 2. Description of the Related Art
[0006] In a multilevel interconnection technique of a semiconductor
device, a multilevel interconnection structure can be obtained by
forming an interlevel insulator between a lower wiring and an upper
wiring, wherein the lower wiring is formed over a semiconductor
substrate and the upper wiring is formed over the lower wiring. An
integration of the semiconductor device can be improved by the
multilevel interconnection structure.
[0007] In general, an electrical junction part is formed in a
contact hole which is provided in the interlevel insulator so as to
expose an active region of the semiconductor substrate.
[0008] There is a self-alignment contact technique to provide such
contact hole. This self-alignment technique is executed by
following steps.
[0009] First, a pair of gate electrodes whose side surfaces and
upper surfaces are covered with protection films, e.g., a silicon
nitride film, is formed over a semiconductor substrate.
[0010] Next, an interlevel insulator is formed over the entire
surface of the semiconductor substrate so as to cover the gate
electrodes and the protection films.
[0011] Next, an etching mask having an opening is formed on a
surface of the interlevel insulator so that the opening corresponds
to an active region of the semiconductor substrate between the gate
electrodes.
[0012] Then, an etching process is executed by using the etching
mask to form a contact hole extending from the active region to an
upper surface of the interlevel insulator. At this time, since the
protection films have a high etching-resistance characteristic
against an etching gas, or the like, the protection films are
prevented from being etching. This means that the protection films
function as an etching mask.
[0013] In the self-alignment contact technique, even though the
etching mask is formed on a position which is slightly different
from a desired position, the contact hole exposing the active
region can be obtained because of a mask function of the protection
film.
[0014] However, an anisotropic etching is used for a selective
etching process using the etching mask wherein the anisotropic
etching is an etching that an etching rate in a direction
horizontal is relatively smaller than the etching rate in a
direction vertical. Therefore, when a large amount of mask
misalignment occurs, there is a possibility that an area of the
exposed active region becomes smaller than an area having a desired
value.
[0015] The reduction of the exposed active region causes an
increase in the contact resistance between the exposed active
region and a conductive part which is formed within the contact
hole. This means also that electrical characteristics become uneven
among contact holes.
[0016] In order to overcome such problems mentioned above, an idea
that an isotropic etching is used for the selective etching instead
of the anisotropic etching may arise. However, when only the
isotropic etching is simply applied to the selective etching to
form the contact hole in the interlayer insulator, it is difficult
to control the area of the exposed active region and the depth of
the contact hole. This means that a required contact hole is not
obtained.
[0017] Another idea that both of the isotropic etching and the
anisotropic etching is applied to the selective etching may also
arise. However, it is not realistic that the interlayer insulator
having single etching-resistance property is subjected to different
kinds of etching methods, i.e., the isotropic etching and the
anisotropic etching.
[0018] Consequently, there has been a need for a semiconductor
device having improved electric characteristics and a method of
fabricating the same.
SUMMARY OF THE INVENTION
[0019] It is an object of the present invention is to provide a
semiconductor device and a method of fabricating the same that may
improve electric characteristics among contact holes formed
therein.
[0020] It is another object of the present invention is to provide
a semiconductor device and a method of fabricating the same that
may improve a moisture absorption property.
[0021] According to one aspect of the present invention, for
achieving one or more of the above objects, there is provided a
semiconductor device which includes a semiconductor substrate which
has a major surface and a MOS transistor which has a gate and first
and second diffusion regions and which is formed on the major
surface. The semiconductor device also includes a laminated
structure of a SOG layer, wherein the laminated structure is
composed of a base layer and a surface layer formed on the base
layer and is formed over the MOS transistor and wherein the surface
layer is denser than the base layer.
[0022] According to another aspect of the present invention, for
achieving one or more of the above objects, there is provided a
method of fabricating a semiconductor device which includes forming
a SOG layer over a MOS transistor formed on a semiconductor
substrate; converting a surface portion of the SOG layer into to a
dense layer which is denser than a bottom portion of the SOG layer;
removing a first portion of the dense layer to expose a surface of
the bottom portion of the SOG layer by a first etching; removing a
second portion which corresponds to the exposed surface of the
bottom portion of the SOG layer to expose a diffusion region of the
MOS transistor by a second etching; and forming a conductive
material within a space in which the first and second portions are
removed.
[0023] The above and further objects and novel features of the
invention will more fully appear from the following detailed
description, appended claims and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] FIG. 1 (a) through FIG. 1 (c) are cross sectional views
showing a semiconductor device according to a first preferred
embodiment of the present invention.
[0025] FIG. 2 is a cross sectional view showing a semiconductor
device according to a second preferred embodiment of the present
invention.
[0026] FIG. 3 (a) through FIG. 3 (c) are cross sectional views
showing a semiconductor device according to a third preferred
embodiment of the present invention.
[0027] FIG. 4 is a schematic cross sectional view of FIG. 3(c).
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Preferred Embodiment
[0028] A semiconductor device according to preferred embodiment of
the present invention will be explained hereinafter with reference
to figures. In order to simplify explanations, like elements are
given like or corresponding reference numerals through this
specification and figures. Dual explanations of the same elements
are avoided.
[0029] FIG. 1 (a) through FIG. 1 (c) are cross sectional views
showing a semiconductor device according to a first preferred
embodiment of the present invention.
[0030] FIGS. 1 (a) through 1 (c) show an example in which a SOG
film substantially composed of two layers (the SOG film is also
called hereinafter a lamination structure) is applied to a
self-alignment contact technique. FIGS. 1 (a) through 1 (c) include
fabrication steps for fabricating MOS transistors.
[0031] As shown in FIG. 1 (a), an element isolation region 11 made
of a field oxide is formed on a semiconductor substrate 10, e.g., a
semiconductor material such as silicon, by using, for example,
LOCOS (Local oxidation of silicon) technique. This element
isolation region 11 defines active regions 12 on which active
elements such as transistor or passive elements such as resistor
are formed.
[0032] A pair of gate electrodes 14 is formed over the active
region 12 through gate oxide films 13, and the gate electrodes 14
are arranged apart from each other. Protective films 15 (15a and
15b) made of silicon nitride are formed on upper and side surfaces
of the gate electrodes 14. This structure is well known as the
conventional self-alignment contact technique.
[0033] Impurity regions 16 serve as source or drain regions and are
formed on the active region 12 adjacent to the gate electrodes 14.
The impurity regions 16 are formed by using an ion implantation
technique. At this time, the protective films 15 function as an ion
implantation mask. Furthermore, mask oxide films 17 are utilized in
this ion implantation technique to prevent the active region 12
from being damaged due to the ion implanting. Such mask oxide film
17 is well known in this technical field. The mask oxide films 17
are removed by using etchant after the impurity regions 16 are
formed. In this embodiment, the etchant containing hydrofluoric
acid which has concentration of 0.3 percent is used. The
hydrofluoric acid is the principal ingredient in the etchant.
[0034] Next, as shown in FIG. 1 (b), the mask oxide films 17 are
removed. Then, a SOG film 18 (18a and 18b) is formed over the
entire surface including the element isolation region 11, the
active region 12, the gate electrodes 14, and protect films 15.
[0035] The SOG film 18 is formed by carrying out following steps.
First, a silicon compound is dissolved in an organic solvent to
obtain a SOG solution. Next, the obtained SOG solution is coated on
the entire surface. Then, the coated SOG solution is baked and thus
the SOG film 18 is finally obtained. Since the SOG film 18 is
introduced as the interlayer insulator, the interlayer insulator
having a planarized surface can be obtained even though step
portions such as the gate electrodes 14 and the protect film 15
(15a and 15b) exist in the interlayer insulator. Therefore, upper
wirings can be patterned on the SOG film 18 accurately without
considering an error in a photolithography process, a break of
wiring, or the like due to an uneven surface of the interlayer
insulator.
[0036] Next, an ion such as Ar ion is implanted into the surface of
the SOG film 18 and a portion adjacent to the surface of the SOG
film 18 before providing a contact hole to expose the impurity
region 16 located between the gate electrodes 14. Thus, the
ion-implanted portion of the SOG film 18 is converted into a dense
layer 18b. As a result, the laminated structure composed of a base
layer 18a of ion non-implanted and a surface layer 18b (the dense
layer) which is denser than the base layer 18a is finally
obtained.
[0037] Such ion implantation for obtaining the laminated structure
of the SOG film is described in Japanese Laid Open Patent Number
69562/1997, published Mar. 11, 1997 in Japan. The publication
states that the reason why the dense layer is formed by ion
implantation in the SOG film. In the publication, the reason is
that organic compositions in the SOG film 18 are decomposed, and
moisture and hydroxyl group in the SOG film 18 are decreased
because of the ion implantation. Therefore, the ion which is used
to obtain the dense layer in the SOG film 18 may be not only the
argon but also a variety of ions. For example, an ion of fluoride
such as silicon fluoride and boron fluoride, a boron ion, an
nitrogen ion, an inert gas ion, any one of ions such as IIIb
element ion, IVb element ion, Vb element ion, VIb element ion, VIIb
element ion, IVa element ion, and Va element ion, or an ion of a
compound made up of any mixture of at least two kinds of elements
selected from IIIb element, IVb element, Vb element, Vb element,
VIIb element, IVa element, and Va element may be used in the ion
implantation. That is, the kind of ions used in the ion
implantation depends on a process.
[0038] It is easy to control depth of ions to be implanted into the
SOG film 18. Furthermore, this control is more accurate than a
thermal diffusion technique. Consequently, the surface layer 18b
having a desired thickness can be formed by controlling ion
implantation energy. Since the surface layer 18b is denser than the
base layer 18a, the surface layer 18b has higher
etching-resistance.
[0039] Next, as illustrated in FIG. 1 (b), a resist pattern 19 is
formed on the surface layer 18b to carry out an etching process
which utilizes the etching-resistance. The resist pattern 19 can be
formed by a photolithography technique well known as a conventional
technique.
[0040] The resist pattern 19 has an opening 19a provided on the
surface of the surface layer 18b. The opening 19a is not located
right above the impurity region 16a. That is, the opening 19a is
shifted in the direction of the left against the impurity region
16a as illustrated in FIG. 1 (b). An amount of this shift is
relatively large. First, in spite of this shift, in order to obtain
a contact hole exposing the impurity region 16a, a first etching
hole 20a which extends from the surface of the surface layer 18b to
the surface of the base layer 18a is formed in the surface layer
18b by using a dry etching process having an anisotropic
property.
[0041] In this dry etching process for obtaining the first etching
hole 29a, reactive gas such as C.sub.3F.sub.3, CC1.sub.4, Ar, and
the like are used. The protect film 15 (15a and 15b) made of
silicon nitride has a higher etching rate to the etching gas than
that of the dense surface layer 18b. This means that an etching
selective rate is high. Therefore, the surface film 18b can be
etched without providing any large damage to the protect film 15
because of the high etching selective rate.
[0042] Furthermore, the etching gas described above has the
anisotropic property to the dense surface layer 18b. Consequently,
the first etching hole 20a, which corresponds to the opening 19a,
can be formed within the surface layer 18b accurately by using the
selective etching process that the anisotropic dry etching uses the
resist pattern 19 as the etching mask. The first etching hole 20a
may extend in the base layer 18a unless penetrating through the
base layer 18a.
[0043] After the etching hole 20a is formed, an exposed surface of
the base layer 18a is subjected to an etchant such as hydrogen
fluoride. The base layer 18a, the surface layer 18b, and the
protect film 15 (15a and 15b) have etching rates to the etchant in
that order. For, example, an etching rate of the hydrogen fluoride
having concentration of 5% to the base layer 18a and an etching
rate of the hydrogen fluoride having concentration of 5% to the
surface layer 18b are 3000-4000 .ANG./min and 300-350 .ANG./min,
respectively. An etching rate of the hydrogen fluoride having
concentration of 5% to the protect film 15 is not more than that of
the base layer 18b. Therefore, a second etching hole 20b can be
formed at a position which extends from the first etching hole 20a,
which is located at the base layer 18a, and which is located
between the side walls 15a and 15b by a wet etching process using
such an etchant. At this time, the surface layer 18b and the
protect film 15 (15a and 15b) are prevented from being damaged.
[0044] Furthermore, since the etchant has an isotropic property to
the base layer 18a and the side walls 15a and 15b function as a
mask which is often used in the self-alignment technique, a portion
of the base layer 18a between the side walls 15a and 15b can be
removed properly by the etchant having the isotropic property.
[0045] Therefore, even though the opening 19a is slightly shifted
to the horizontal direction with respect to the impurity region 16a
to be exposed, e.g., the left direction in FIG. 1 (b), the impurity
region 16a can be exposed by the second etching hole 20b so that
its exposed surface has a desired area. That is, an etching hole 20
which exposes the desired area of the impurity region 16a can be
formed by using the first etching hole 20a and the second etching
hole 20b extending from the first etching hole 20a. This etching
hole 20 is also called "a contact hole".
[0046] Next, as shown in FIG. 1 (c), a conductive part 21, which is
well known, is formed within the etching hole 20. As described
above, the etching hole 19a can expose the desired area in the
impurity region 16a even though the shift between the position of
the opening 19a and the position of the impurity region 16a occurs.
Therefore, it is possible to prevent the contact area between the
conductive part 21 and the impurity region 16a from being reduced
and from being uneven in entire surface of the semiconductor
substrate 10 in spite of this shift.
[0047] A MOS transistor having the gate electrode 14 and a pair of
impurity regions 16 and 16a formed on the side surfaces of the gate
electrode 14 can control a channel, which occurs below the gate
electrode 14 and between the impurity regions 16 and 16a, by
controlling a voltage applied to the gate electrode 14. This is
well known as a conventional technique.
[0048] In this MOS transistor, a channel current controlled by the
gate voltage flows into the conductive part 21. At this time, since
the contact resistance between the conductive part 21 and the
impurity region 16 can be set at substantially the same value on
the entire semiconductor substrate 10, the uneven electric
characteristics of the MOS transistors due to the uneven contact
resistance can be improved.
Second Preferred Embodiment
[0049] A semiconductor device according to a second preferred
embodiment of the present invention will be explained hereinafter
with reference to FIG. 2.
[0050] FIG. 2 shows an example in which the laminated structure of
the present invention is applied to a semiconductor memory device
such as a DRAM.
[0051] As shown in FIG. 2, the impurity regions 16 are formed on
the active region 12 between gate electrodes 14 and formed on the
active region 12 outside of the gate electrodes 14. A MOS
transistor which functions as a switching element is composed of
the gate electrode 14 and a pair of impurity regions 16 which is
positioned on both sides of the gate electrode 14. In FIG. 2, two
MOS transistors share one impurity region 16a. A memory cell is
made up of the MOS transistor having the gate electrode 14, the
impurity region 16a, and the impurity region 16 and a capacitor
associated with the impurity region 16.
[0052] The SOG film 18 having the laminated structure (18a and 18b)
which is the same as that of the first preferred embodiment is
formed over the gate electrodes 14 so as to cover the gate
electrodes 14. The conductive part 21 as a bit line is formed
between the gate electrodes 14. The conductive part 21 is the same
as that of the first preferred embodiment. The two memory cells
share conductive part 21. The conductive part 21 as the bit line
can be formed in the same manner as explained in FIG. 1 (a) through
FIG. 1 (c).
[0053] After that, as shown in FIG. 2, an interlevel insulator 22
made of CVD silicon oxide film is formed on the conductive part 21
and the SOG film 18.
[0054] Etching holes 23 which go through the interlevel insulator
22 and the SOG film 18 are formed in the interlevel insulator 22
and the SOG film 18 to expose the impurity regions 16. In the
formation of the etching hole 23, the interlevel insulator 22 and
the surface layer 18b are subjected to a selective etching process
similar to that of the first preferred embodiment, which is the dry
etching process having the anisotropic property. First etching
holes 23a corresponding to an etching mask 19 of a resist pattern
(not shown) are formed within the interlevel insulator 22 and the
surface layer 18b by the dry etching process. This process is
similar to that of the first preferred embodiment.
[0055] After forming the first etching holes 23a, the etching
process is applied to the base layer 18a formed under the surface
layer 18b of the SOG film 18 in the laminated structure.
[0056] The wet etching having the isotropic property is used in the
etching process of the base layer 18a, wherein the etching process
is done substantially in the same manner of the first preferred
embodiment.
[0057] In this wet etching process, the element isolation region 11
of silicon dioxide film (thermal oxidation film) only has an
etching rate which is equal to or slightly larger than that of the
surface layer 18b.
[0058] Therefore, second etching holes 23b which expose the
impurity regions 16 between the side walls 15a and the element
isolation regions 11 are formed within the base layer 18a by the
wet etching process. The second etching holes 23b are cavities
having relatively large capacity.
[0059] Conductive parts 24 as a storage electrode of the capacitor
are formed on side surfaces of the etching hole 23, wherein the
side surfaces are defined by the first etching hole 23a and the
second etching hole 23b.
[0060] In the second preferred embodiment, both of the dry etching
process having the anisotropic property to the surface layer 18b
and the wet etching process having the isotropic property to the
base layer 18a are used for forming the etching hole 20 in which
the conductive part 21 as the bit line is provided and for forming
the etching hole 23 in which the conductive part 24 as storage
electrode of the capacitor is provided.
[0061] The etching hole 20 for the conductive part 21 and the
etching hole 23 for the conductive part 24 which expose a desired
area in the active region 12 (the impurity regions 16 and 16a) can
be formed by using this two step etching even though the mask shift
occurs or the mask pattern has a circular shape or a rectangular
shape.
[0062] In the present invention, the contact resistance between the
bit lines and the impurity regions can be almost even in all of the
contacts. Also the contact resistance between the storage
electrodes and the impurity regions can be almost even in all of
the contacts. Therefore, a DRAM having fine electric
characteristics can be fabricated easily.
[0063] Using the hydrofluoric acid in the wet etching process
having the isotropic property, and the protect film 15 (15a and
15b) made of silicon nitride, are shown as an example. However, any
etching acid having isotropic property other than hydrofluoric acid
may be used instead. Any kind of materials which have an etching
rate lower than that of the base layer 18a can be used as the
protect film 15. These etching rates depend on the etching acid
used in the wet etching process.
[0064] In the first and second preferred embodiments, utilizing the
difference between the density of the base layer of the SOG film
and the density of the surface layer of the SOG layer is explained
as an example. In a third preferred embodiment of the present
invention explained hereinafter, utilizing the difference between a
coefficient of moisture absorption of the base layer in the SOG
film and a coefficient of moisture absorption of the surface layer
in the SOG film will be explained as an example.
Third Preferred Embodiment
[0065] A semiconductor device according to a third preferred
embodiment of the present invention will be explained hereinafter
with reference to FIG. 3 (a) through FIG. 3 (c) and FIG. 4.
[0066] FIG. 3 (a) through FIG. 3 (c) show an example in which the
laminated structure of the present invention is applied to a
semiconductor device such as a semiconductor memory. FIG. 4 is a
schematic cross sectional view of FIG. 3 (c).
[0067] A redundant circuit having a redundant memory cell which is
substituted for a defective memory cell is provided in the
semiconductor device such as DRAM. A selecting circuit for carrying
out a substitution operation (it is also called a replacing
operation) that the redundant memory cell is substituted for the
defective memory cell is also incorporated in the semiconductor
device. Laser blown fuses are incorporated in this selecting
circuit. The substitution operation is achieved by blowing the
laser blown fuses.
[0068] FIG. 3 (a) through FIG. 3 (c) show fabrication steps of the
semiconductor device in which the laser blown fuses for the
redundant circuit are incorporated.
[0069] Referring to FIG. 3 (a), the laser blown fuses 32 for the
redundant circuit are formed over a semiconductor substrate 30
through an insulator 31. The insulator 31 is made of silicon oxide
film formed by using, for example, a CVD method. The fuse 32 is
preferably made of tungsten silicide layer having 150 nm in
thickness.
[0070] An insulator 33 which is made of silicon oxide film is
formed on the fuses 32 and the insulator 31 so as to cover the
fuses 32.
[0071] A tungsten layer having 500 nm in thickness is deposited on
the insulator 33 by using the CVD method. Photolithography and
etching are applied to the deposited tungsten layer. Thus, wirings
for selecting circuit, wirings for bit lines, or the like are
obtained. Furthermore, a dummy layer 34 is obtained by the
deposited tungsten layer. As illustrated in FIG. 4, the dummy layer
34 has a frame shape and is formed on the insulator 33 so as to
surround a region where the fuses 32 are located. The dummy layer
34 prevents moisture from being introducing into an internal
circuit of the semiconductor device.
[0072] A SOG layer 35 which relates to the present invention is
formed over the wirings including fuses 32. An insulator 36 which
has 500 nm in thickness and covers the dummy layer 34 is formed on
the insulator 33 and the dummy layer 34 in order to improve degree
of adhesion between the SOG layer 35 and the dummy layer 34. The
insulator 36 is formed by using plasma CVD method.
[0073] After forming the insulator 36, the SOG film 35 covering the
dummy layer 34 and the insulator 36 is obtained by the following
manner. First, a silicon compound is dissolved in an organic
solvent to obtain a SOG solution. Next, the obtained SOG solution
is coated on the entire surface. Then, the coated SOG solution is
baked at about 300.degree. C. and thus the SOG film 35 is finally
obtained. The SOG layer 35 has a relatively high coefficient of
moisture absorption.
[0074] After that, the surface of the SOG layer 35 is subject to
the ion implantation as explained above. The surface of the SOG
film 35 located above the dummy layer 34 is converted into a
surface layer 35b as a dense layer. The surface layer 35b is
relatively denser than a base layer located under the surface layer
35a. As a result, as illustrated in FIG. 3 (b), the SOG film 35 is
converted into the laminated structure which is composed of the
surface layer 35b as a denser layer and the base layer 35a having
relatively higher moisture absorption property than the surface
layer 35b.
[0075] The surface layer 35b located above the dummy layer 34 and
the dummy layer 34 function as a dam for preventing moisture from
passing therethrough.
[0076] Next, the insulator 37 and a cover film 38 as explained
hereinafter, each of which has a coefficient of moisture absorption
relatively lower than that of the SOG layer 35, are formed over the
insulator 37 and the cover film 38.
[0077] When the SOG film 35 having the relatively high moisture
absorption property exists between the top surface of the dummy
layer 34 and the insulator 37, the SOG film 35 may act as a path
through which the moisture passes. In the conventional technique,
the SOG film 35 located between the top surface of the dummy layer
34 and the insulator 37 is removed by etching back the entire
surface of the SOG film 35 to overcome the moisture passing
problem. Then, the insulator 37 and the cover film 38 are formed
over the etched surface of the SOG film 35.
[0078] In this preferred embodiment of the invention, the insulator
37 and the cover film 38 can be formed over the surface layer 35b
of the SOG film 35 without etching back the SOG film 35.
[0079] The insulator 37 is made of, for example, a plasma oxide
film having about 400 nm in thickness and can be formed by using
the plasma CVD method. The cover film 38 has about 1000 nm in
thickness as well known in this technical field and can be formed
by using the CVD method.
[0080] Contact holes which expose surfaces of wirings located under
corresponding contact holes are formed within the insulator 37 (not
shown in FIG. 3 (a) through FIG. 3 (c) and FIG. 4). Conductive
parts are formed within the corresponding contact holes.
[0081] Next, after forming the insulator 37 and the cover film 38,
an opening 39 extending from the surface of the cover film 38 to a
position adjacent to the fuses 32 is formed by using a selective
etching process. The opening 39 functions as a laser blow window
for blowing the fuses 32. Thus, blowing the fuses 32 by the laser
beam can be achieved easily.
[0082] The SOG film 35 of relatively high moisture absorption
property is exposed at edges of the opening 39 due to the formation
of the opening 39. However, since the coefficient of the moisture
absorption of the surface layer 35b located on the top surface of
the dummy layer 34 is reduced by the ion implantation, both of the
surface layer 35b and the dummy layer 34 function as the effective
dam against the moisture which is entered into the semiconductor
device at the edges of the opening 39. Therefore, a moisture
cutting off structure accurately functioning as the dam can be
obtained without etching back the SOG film.
[0083] In the third preferred embodiment of the present invention,
applying the moisture cutting off structure which is comprised of
the laminated structure and the dummy layer to the redundant
circuit of the memory device is explained. However, the moisture
cutting off structure of the present invention can be applied to
any moisture cutting off structures, for example, an opening
associated with a grid line, an edge portion of a semiconductor
chip having a multilevel wiring structure, or the like.
[0084] While the preferred form of the present invention has been
described, it is to be understood that modifications will be
apparent to those skilled in the art without departing from the
spirit of the invention. The scope of the invention is to be
determined solely by the following claims.
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