U.S. patent application number 11/459792 was filed with the patent office on 2006-11-16 for zralxoy dielectric layers.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Kie Y. Ahn, Leonard Forbes.
Application Number | 20060255470 11/459792 |
Document ID | / |
Family ID | 34225819 |
Filed Date | 2006-11-16 |
United States Patent
Application |
20060255470 |
Kind Code |
A1 |
Ahn; Kie Y. ; et
al. |
November 16, 2006 |
ZrAlxOy DIELECTRIC LAYERS
Abstract
A ZrAl.sub.xO.sub.y dielectric layer structured as one or more
monolayers and a method of fabricating such a dielectric layer
produce a reliable dielectric layer having an equivalent oxide
thickness thinner than attainable using SiO.sub.2. Various
embodiments include a ZrAl.sub.xO.sub.y dielectric film in a
variety of electronic arrangements including, but not limited to,
capacitors, transistors, memories, and electronic systems.
Inventors: |
Ahn; Kie Y.; (Chappaqua,
NY) ; Forbes; Leonard; (Corvallis, OR) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH, P.A.
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
34225819 |
Appl. No.: |
11/459792 |
Filed: |
July 25, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10403734 |
Mar 31, 2003 |
|
|
|
11459792 |
Jul 25, 2006 |
|
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Current U.S.
Class: |
257/776 ;
257/E21.193; 257/E21.645 |
Current CPC
Class: |
H01L 29/518 20130101;
H01L 21/28194 20130101; H01L 21/02178 20130101; H01L 21/28167
20130101; H01L 21/02189 20130101; H01L 21/02194 20130101; H01L
27/1052 20130101; C23C 16/45531 20130101; H01L 21/31641 20130101;
H01L 2924/0002 20130101; H01L 21/0228 20130101; H01L 29/517
20130101; H01L 21/3141 20130101; H01L 2924/0002 20130101; H01L
21/02205 20130101; C23C 16/40 20130101; H01L 29/513 20130101; H01L
2924/00 20130101 |
Class at
Publication: |
257/776 |
International
Class: |
H01L 23/52 20060101
H01L023/52 |
Claims
1. An electronic device comprising: a substrate; and a dielectric
layer disposed above the substrate, the dielectric layer having a
layer of ZrAl.sub.xO.sub.y, the layer of ZrAl.sub.xO.sub.y arranged
as a layered structure of one or more monolayers.
2. The device of claim 1, wherein the layer of ZrAl.sub.xO.sub.y is
substantially a Zr.sub.4AlO.sub.9 layer.
3. The device of claim 2, wherein an interfacial layer of silicon
oxide or a silicate formed between the substrate and the
Zr.sub.4AlO.sub.9 is less than about 1 nm.
4. The device of claim 1, wherein an interfacial layer between the
substrate and the layer of ZrAl.sub.xO.sub.y is less than about 1
nm.
5. The device of claim 1, wherein the substrate is a silicon-based
substrate.
6. A capacitor, comprising: a first conductive layer disposed above
a substrate; a dielectric layer containing a ZrAl.sub.xO.sub.y film
disposed on the first conductive layer, the ZrAl.sub.xO.sub.y film
arranged as a layered structure of one or more monolayers; and a
second conductive layer disposed on the dielectric layer.
7. The capacitor of claim 6, wherein the dielectric layer includes
Zr.sub.4AlO.sub.9.
8. The capacitor of claim 6, wherein the dielectric layer has an
equivalent oxide thickness of 9 .ANG. or less.
9. The capacitor of claim 6, wherein an interfacial layer between
the first conductive layer and the ZrAl.sub.xO.sub.y is less than
about 1 nm.
10. A transistor comprising: a body region in a substrate between a
source region and a drain region; a dielectric layer disposed above
the body region between the source region and the drain region, the
dielectric layer having a ZrAl.sub.xO.sub.y film, the
ZrAl.sub.xO.sub.y film arranged as a layered structure of one or
more monolayers; and a gate coupled to the dielectric layer.
11. The transistor of claim 10, wherein the dielectric layer is
substantially the ZrAl.sub.xO.sub.y film.
12. The transistor of claim 10, wherein the dielectric layer is a
floating gate dielectric interposed between a floating gate and a
control gate of the transistor.
13. The transistor of claim 10, wherein the dielectric layer is a
gate dielectric interposed between a floating gate and the body
region.
14. The transistor of claim 10, wherein an interfacial layer
between the substrate and the ZrAl.sub.xO.sub.y is less than about
1 nm.
15. The transistor of claim 10, wherein the dielectric layer has an
equivalent oxide thickness (t.sub.eq) of less than about 10
Angstroms.
16. A memory comprising: a substrate; and an array of memory cells,
a memory cell of the array having a dielectric layer containing a
ZrAl.sub.xO.sub.y layer, the dielectric layer disposed above the
substrate, the ZrAl.sub.xO.sub.y layer arranged as a layered
structure of one or more monolayers.
17. The memory of claim 16, wherein the dielectric layer includes
Zr.sub.4AlO.sub.9.
18. The memory of claim 16, wherein the dielectric layer is a
capacitor dielectric of a capacitor in the memory cell.
19. The memory of claim 16, wherein the dielectric layer is a
floating gate dielectric interposed between a floating gate and a
control gate of a transistor in the memory cell.
20. The memory of claim 16, wherein the dielectric layer is a gate
dielectric interposed between a floating gate and a channel of a
transistor in the memory cell.
21. The memory of claim 16, wherein an interfacial layer between
the substrate and the ZrAl.sub.xO.sub.y is less than about 1
nm.
22. The memory of claim 16, wherein the dielectric layer has an
equivalent oxide thickness (t.sub.eq) of less than about 10
Angstroms.
23. The memory of claim 16, wherein the substrate is a silicon
based substrate.
24. An electronic system comprising: a processor; a system bus; and
a memory coupled to the processor by the system bus, the memory
including an array of memory cells, a memory cell including a
dielectric layer containing a ZrAl.sub.xO.sub.y film, the
ZrAl.sub.xO.sub.y film arranged as a layered structure of one or
more monolayers, the dielectric layer disposed above a
substrate.
25. The electronic system of claim 24, wherein the dielectric layer
includes Zr.sub.4AlO.sub.9.
26. The electronic system of claim 24, wherein the dielectric layer
is a capacitor dielectric of a storage capacitor in the memory
cell.
27. The electronic system of claim 24, wherein the dielectric layer
is disposed above a channel of a transistor in the memory cell.
28. The electronic system of claim 24, wherein an interfacial layer
between the substrate and the ZrAl.sub.xO.sub.y is less than about
1 nm.
29. The electronic system of claim 24, wherein the electronic
system includes an information handling device.
30. The electronic system of claim 24, wherein the information
handling device includes a wireless device.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a divisional of U.S. application
Ser. No. 10/403,734, filed 31 Mar. 2003, which is herein
incorporated by reference in its entirety.
[0002] This application is related to the following commonly
assigned U.S. patent applications, which are herein incorporated by
reference in their entirety:
[0003] U.S. application Ser. No. 10/137,058, entitled: "Atomic
Layer Deposition and Conversion," filed 2 May 2002;
[0004] U.S. application Ser. No. 10/137,168, entitled: "Methods,
Systems, and Apparatus for Atomic-Layer Deposition of Aluminum
Oxides in Integrated Circuits," filed 2 May 2002; and
[0005] U.S. application Ser. No. 09/797,324, entitled: "Methods,
Systems, and Apparatus for Uniform Chemical-Vapor Depositions,"
filed 1 Mar. 2001, now issued as U.S. Pat. No. 6,852,167.
TECHNICAL FIELD
[0006] This application relates generally to semiconductor devices
and device fabrication and, more particularly, to dielectric layers
and their method of fabrication.
BACKGROUND
[0007] The semiconductor device industry has a market driven need
to improve speed performance, improve its low static (off-state)
power requirements, and adapt to a wide range of power supply and
output voltage requirements for its silicon based microelectronic
products. In particular, there is continuous pressure to reduce the
size of devices such as transistors. The ultimate goal is to
fabricate increasingly smaller and more reliable integrated
circuits (ICs) for use in products such as processor chips, mobile
telephones, and memory devices such as dynamic random access
memories (DRAMs). The smaller devices are frequently powered by
batteries. There is also pressure to reduce the size of the
batteries, and to extend the time between battery charges. This
forces the industry to not only design smaller transistors, but to
design them to operate reliably with lower power supplies.
[0008] Currently, the semiconductor industry relies on the ability
to reduce or scale the dimensions of its basic devices, primarily,
the silicon based metal-oxide-semiconductor field effect transistor
(MOSFET). A common configuration of such a transistor is shown in
FIG. 1. While the following discussion uses FIG. 1 to illustrate a
transistor from the prior art, one skilled in the art will
recognize that the present subject matter could be incorporated
into the transistor shown in FIG. 1 to form a transistor according
to the present subject matter. A transistor 100 is fabricated in a
substrate 110 that is typically silicon, but could be fabricated
from other semiconductor materials as well. Transistor 100 has a
source region 120 and a drain region 130. A body region 132 is
located between source region 120 and drain region 130, where body
region 132 defines a channel of the transistor with a channel
length 134. A gate dielectric 140 is located on body region 132
with a gate 150 located over gate dielectric 140. Although gate
dielectric 140 may be formed from materials other than oxides, gate
dielectric 140 is typically an oxide, and is commonly referred to
as a gate oxide. Gate 150 may be fabricated from polycrystalline
silicon (polysilicon), or other conducting materials such as metal
may be used.
[0009] In fabricating transistors to be smaller in size and
reliably operate on lower power supplies, one design criteria is
gate dielectric 140. The mainstay for forming the gate dielectric
has been silicon dioxide, SiO.sub.2. A thermally grown amorphous
SiO.sub.2 layer provides an electrically and thermodynamically
stable material, where the interface of the SiO.sub.2 layer with
underlying Si provides a high quality interface as well as superior
electrical isolation properties. In typical processing, use of
SiO.sub.2 on Si has provided defect charge densities on the order
of 10.sup.10/cm.sup.2, midgap interface state densities of
approximately 10.sup.10/cm.sup.2 eV, and breakdown voltages in the
range of 15 MV/cm. With such qualities, there would be no apparent
need to use a material other than SiO.sub.2, but increased scaling
and other requirements for gate dielectrics create the need to find
other dielectric materials to be used for a gate dielectric.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 shows a configuration of a transistor having a gate
dielectric containing atomic layer deposited ZrAl.sub.xO.sub.y
according to various embodiments of the present subject matter.
[0011] FIG. 2A shows an atomic layer deposition system for
processing a dielectric layer containing ZrAl.sub.xO.sub.y,
according to various embodiments of the present subject matter.
[0012] FIG. 2B shows a gas-distribution fixture of an atomic layer
deposition system for processing a dielectric layer containing
ZrAl.sub.xO.sub.y.
[0013] FIG. 3 illustrates a flow diagram of elements for an
embodiment of a method to process a ZrAl.sub.xO.sub.y dielectric
layer by atomic layer deposition.
[0014] FIG. 4 illustrates a flow diagram of elements for an
embodiment of a method to process a dielectric layer containing
ZrAl.sub.xO.sub.y by atomic layer deposition.
[0015] FIG. 5A shows an embodiment of a configuration of a
transistor having an atomic layer deposited ZrAl.sub.xO.sub.y
dielectric layer.
[0016] FIG. 5B shows an embodiment of a configuration of a
capacitor having an atomic layer deposited ZrAl.sub.xO.sub.y
dielectric layer.
[0017] FIG. 6 shows an embodiment of a personal computer
incorporating devices having an atomic layer deposited
ZrAl.sub.xO.sub.y dielectric layer.
[0018] FIG. 7 illustrates a schematic view of an embodiment of a
central processing unit incorporating devices having an atomic
layer deposited ZrAl.sub.xO.sub.y dielectric layer.
[0019] FIG. 8 illustrates a schematic view of an embodiment of a
DRAM memory device having an atomic layer deposited
ZrAl.sub.xO.sub.y dielectric layer.
DETAILED DESCRIPTION
[0020] The following detailed description refers to the
accompanying drawings that show, by way of illustration, specific
aspects and embodiments in which the present subject matter may be
practiced. These embodiments are described in sufficient detail to
enable those skilled in the art to practice the present subject
matter. Other embodiments may be utilized and structural, logical,
and electrical changes may be made without departing from the scope
of the present subject matter. The various embodiments disclosed
herein are not necessarily mutually exclusive, as some disclosed
embodiments can be combined with one or more other disclosed
embodiments to form new embodiments.
[0021] The terms wafer and substrate used in the following
description include any structure having an exposed surface with
which to form the integrated circuit (IC) structure of the present
subject matter. The term substrate is understood to include
semiconductor wafers. The term substrate is also used to refer to
semiconductor structures during processing, and may include other
layers that have been fabricated thereupon. Both wafer and
substrate include doped and undoped semiconductors, epitaxial
semiconductor layers supported by a base semiconductor or
insulator, as well as other semiconductor structures well known to
one skilled in the art. The term conductor is understood to include
semiconductors, and the term insulator or dielectric is defined to
include any material that is less electrically conductive than the
materials referred to as conductors.
[0022] The term "horizontal" as used in this application is defined
as a plane parallel to the conventional plane or surface of a wafer
or substrate, regardless of the orientation of the wafer or
substrate. The term "vertical" refers to a direction perpendicular
to the horizontal as defined above. Prepositions, such as "on",
"side" (as in "sidewall"), "higher", "lower", "over" and "under"
are defined with respect to the conventional plane or surface being
on the top surface of the wafer or substrate, regardless of the
orientation of the wafer or substrate. The following detailed
description is, therefore, not to be taken in a limiting sense, and
the scope of the present subject matter is defined only by the
appended claims, along with the full scope of equivalents to which
such claims are entitled.
[0023] A gate dielectric 140 of FIG. 1, when operating in a
transistor, has both a physical gate dielectric thickness and an
equivalent oxide thickness (t.sub.eq). The equivalent oxide
thickness quantifies the electrical properties, such as
capacitance, of a gate dielectric 140 in terms of a representative
physical thickness. The equivalent oxide thickness, t.sub.eq, is
defined as the thickness of a theoretical SiO.sub.2 layer that
would have the same capacitance density as a given dielectric,
ignoring leakage current and reliability considerations.
[0024] A SiO.sub.2 layer of thickness, t, deposited on a Si surface
as a gate dielectric will have a t.sub.eq larger than its
thickness, t. This t.sub.eq results from the capacitance in the
surface channel on which the SiO.sub.2 is deposited due to the
formation of a depletion/inversion region. This depletion/inversion
region may result in t.sub.eq being from 3 to 6 Angstroms (.ANG.)
larger than the SiO.sub.2 thickness, t. Thus, with the
semiconductor industry driving to scale the gate dielectric
equivalent oxide thickness to under 10 521 , the physical thickness
for a SiO.sub.2 layer used for a gate dielectric would be need to
be approximately 4 to 7 .ANG..
[0025] Additional characteristics for a SiO.sub.2 layer depend on
the gate electrode used in conjunction with the SiO.sub.2 gate
dielectric. Using a conventional polysilicon gate results in an
additional increase in t.sub.eq for the SiO.sub.2 layer. This
additional thickness could be eliminated by using a metal gate
electrode, though metal gates are not currently used in typical
complementary metal-oxide-semiconductor field effect transistor
(CMOS) technology. Thus, future devices would be designed towards a
physical SiO.sub.2 gate dielectric layer of about 5 .ANG. or less.
Such a small thickness for a SiO.sub.2 oxide layer creates
additional problems.
[0026] Silicon dioxide is used as a gate dielectric, in part, due
to its electrical isolation properties in a SiO.sub.2--Si based
structure. This electrical isolation is due to the relatively large
bandgap of SiO.sub.2 (8.9 eV) making it a good insulator from
electrical conduction. Signification reductions in its bandgap
would eliminate it as a material for a gate dielectric. As the
thickness of a SiO.sub.2 layer decreases, the number of atomic
layers, or monolayers of the SiO.sub.2 decreases. At a certain
thickness, the number of monolayers will be sufficiently small that
the SiO.sub.2 layer will not have a complete arrangement of atoms
as in a larger or bulk layer. As a result of incomplete formation
relative to a bulk structure, a thin SiO.sub.2 layer of only one or
two monolayers will not form a full bandgap. The lack of a full
bandgap in a SiO.sub.2 gate dielectric could cause an effective
short between an underlying Si channel and an overlying polysilicon
gate. This undesirable property sets a limit on the physical
thickness to which a SiO.sub.2 layer may be scaled. The minimum
thickness due to this monolayer effect is thought to be about 7-8
.ANG.. Therefore, for future devices to have a t.sub.eq less than
about 10 .ANG., dielectrics other than SiO.sub.2 need to be
considered for use as a gate dielectric.
[0027] For a typical dielectric layer used as a gate dielectric,
the capacitance is determined as one for a parallel plate
capacitance: C=.kappa..epsilon..sub.0A/t, where .kappa. is the
dielectric constant, .epsilon..sub.0 is the permittivity of free
space, A is the area of the capacitor, and t is the thickness of
the dielectric. The thickness, t, of a material is related to its
t.sub.eq for a given capacitance, with SiO.sub.2 having a
dielectric constant .kappa..sub.ox=3.9, as
t=(.kappa./.kappa..sub.ox)t.sub.eq=(.kappa./3.9)t.sub.eq. Thus,
materials with a dielectric constant greater than that of
SiO.sub.2, 3.9, will have a physical thickness that may be
considerably larger than a desired t.sub.eq, while providing the
desired equivalent oxide thickness. For example, an alternate
dielectric material with a dielectric constant of 10 could have a
thickness of about 25.6 .ANG. to provide a t.sub.eq of 10 .ANG.,
not including any depletion/inversion layer effects. Thus, a
reduced t.sub.eq for transistors may be realized by using
dielectric materials with higher dielectric constants than
SiO.sub.2. The thinner t.sub.eq for lower transistor operating
voltages and smaller transistor dimensions may be realized by a
significant number of materials, but additional fabricating
characteristics makes determining a suitable replacement for
SiO.sub.2 difficult.
[0028] The current view for the microelectronics industry is still
for Si based devices. Thus, the gate dielectric employed will grow
on a silicon substrate or silicon layer, which places significant
restraints on the substitute dielectric material. During the
formation of the dielectric on the silicon layer, there exists the
possibility that a small layer of SiO.sub.2 could be formed in
addition to the desired dielectric. The result would effectively be
a dielectric layer consisting of two sublayers in parallel with
each other and the silicon layer on which the dielectric is formed.
In such a case, the resulting capacitance would be that of two
dielectrics in series. As a result, the t.sub.eq of the dielectric
layer would be the sum of the SiO.sub.2 thickness and a
multiplicative factor of the thickness of the dielectric being
formed, written as
t.sub.eq=t.sub.SiO.sub.2+(.kappa..sub.ox/.kappa.)t. Thus, if a
SiO.sub.2 layer is formed in the process, the t.sub.eq is again
limited by a SiO.sub.2 layer. Thus, use of a ultra-thin silicon
oxide interface layer should be limited to significantly less than
ten angstroms. In the event that a barrier layer is formed between
the silicon layer and the desired dielectric in which the barrier
layer prevents the formation of a SiO.sub.2 layer, the t.sub.eq
would be limited by the layer with the lowest dielectric constant.
However, whether a single dielectric layer with a high dielectric
constant or a barrier layer with a higher dielectric constant than
SiO.sub.2 is employed, the layer interfacing with the silicon layer
must provide a high quality interface to maintain a high channel
carrier mobility.
[0029] One of the advantages for using SiO.sub.2 as a gate
dielectric has been that the formation of the SiO.sub.2 layer
results in an amorphous gate dielectric. Having an amorphous
structure for a gate dielectric is advantageous because grain
boundaries in polycrystalline gate dielectrics provide high leakage
paths. Additionally, grain size and orientation changes throughout
a polycrystalline gate dielectric may cause variations in the
layer's dielectric constant. Many materials having a high
dielectric constant relative to SiO.sub.2 also have a disadvantage
of a crystalline form, at least in a bulk configuration. Thus, the
best candidates for replacing SiO.sub.2 as a gate dielectric are
those with high dielectric constant, a relatively large bandgap,
and are able to be fabricated as a thin layer with an amorphous
form.
[0030] Materials such as Ta.sub.2O.sub.3, TiO.sub.2,
Al.sub.2O.sub.3, ZrO.sub.2, ZrSi.sub.xO.sub.y, HfSi.sub.xO.sub.y,
and barium strontium titanate (BST) have been proposed as
replacements for SiO.sub.2 as gate dielectric materials. However,
application of such materials may depend on characteristics of a
dielectric material useful for application as a gate dielectric
that include a sharp interface with a silicon substrate, which
favours a low density of interface states, a large bandgap that is
comparable to that of silicon oxide, a large energy barrier from
the conduction band to the Fermi level of the gate electrode used,
and physicochemical and structural stability in subsequent device
processing procedures.
[0031] Many materials with high dielectric constant have low
bandgaps relative to the bandgap of silicon oxide (8.9 eV). The
materials ZrO.sub.2 and Al.sub.2O.sub.3 have dielectric constants
of 25 and 9, respectively, and bandgaps of 7.8 eV and 8.7 eV,
respectively. See G. D. Wilk et al., Journal of Applied Physics
vol. 89: no. 10, pp. 5243-5275 (2001). Thus, a dielectric layer
containing ZrAl.sub.xO.sub.y provides a high dielectric constant
and large bandgap characteristics. However, other considerations
for selecting the material and method for forming a dielectric
layer for use in electronic devices and systems concern the
suitability of the material for applications requiring that the
dielectric layer have an ultra-thin equivalent oxide thickness,
form conformally on a substrate, and/or be engineered to specific
thickness and elemental concentrations.
[0032] Another consideration concerns the roughness of the
dielectric layer on a substrate. Surface roughness of the
dielectric layer has a significant effect on the electrical
properties of the gate oxide, and the resulting operating
characteristics of the transistor. Leakage current through a
physical 1.0 nm gate oxide has been found to be increased by a
factor of 10 for every 0.1 increase in the root-mean-square (RMS)
roughness.
[0033] During a conventional sputtering deposition process stage,
particles of the material to be deposited bombard the surface at a
high energy. When a particle hits the surface, some particles
adhere, and other particles cause damage. High-energy impacts
remove body region particles creating pits. The surface of such a
deposited layer may have a rough contour due to the rough interface
at the body region.
[0034] In an embodiment, a ZrAl.sub.xO.sub.y dielectric layer
having a substantially smooth surface relative to other processing
techniques is formed using atomic layer deposition (ALD). Further,
forming a dielectric layer using atomic layer deposition provides
for controlling transitions between material layers. Thus, atomic
layer deposited ZrAl.sub.xO.sub.y dielectric layers may have an
engineered transition with a substrate surface that has an
interfacial SiO.sub.2 layer or an interfacial silicate layer
substantially limited in thickness to provide an effective
dielectric constant for the dielectric layer that is significantly
greater than that of a silicon oxide layer. Further, the ALD
deposited ZrAl.sub.xO.sub.y dielectric layers provide conformal
coverage on the surfaces on which they are deposited.
[0035] ALD, also known as atomic layer epitaxy (ALE), was developed
in the early 1970's as a modification of chemical vapor deposition
(CVD) and is also called "alternatively pulsed-CVD." In ALD,
gaseous precursors are introduced one at a time to the substrate
surface mounted within a reaction chamber (or reactor). This
introduction of the gaseous precursors takes the form of pulses of
each gaseous precursor. Between the pulses, the reaction chamber is
purged with a gas, which in many cases is an inert gas, and/or
evacuated.
[0036] In a chemisorption-saturated ALD (CS-ALD) process, during
the first pulsing phase, reaction with the substrate occurs with
the precursor saturatively chemisorbed at the substrate surface.
Subsequent pulsing with a purging gas removes precursor excess from
the reaction chamber.
[0037] The second pulsing phase introduces another precursor on the
substrate where the growth reaction of the desired layer takes
place. Subsequent to the layer growth reaction, reaction
by-products and precursor excess are purged from the reaction
chamber. With favourable precursor chemistry where the precursors
adsorb and react with each other on the substrate aggressively, one
ALD cycle may be performed in less than one second in properly
designed flow type reaction chambers. Typically, precursor pulse
times range from about 0.5 sec to about 2 to 3 seconds.
[0038] In ALD, the saturation of all the reaction and purging
phases makes the growth self-limiting. This self-limiting growth
results in large area uniformity and conformality, which has
important applications for such cases as planar substrates, deep
trenches, and in the processing of porous silicon and high surface
area silica and alumina powders. Thus, ALD provides for controlling
layer thickness in a straightforward manner by controlling the
number of growth cycles.
[0039] ALD was originally developed to manufacture luminescent and
dielectric layers needed in electroluminescent displays.
Significant efforts have been made to apply ALD to the growth of
doped zinc sulfide and alkaline earth metal sulfide layers.
Additionally, ALD has been studied for the growth of different
epitaxial II-V and II-VI layers, nonepitaxial crystalline or
amorphous oxide and nitride layers and multilayer structures of
these. There also has been considerable interest towards the ALD
growth of silicon and germanium layers, but due to the difficult
precursor chemistry, this has not been very successful.
[0040] The precursors used in an ALD process may be gaseous, liquid
or solid. However, liquid or solid precursors must be volatile. The
vapor pressure must be high enough for effective mass
transportation. Also, solid and some liquid precursors need to be
heated inside the reaction chamber and introduced through heated
tubes to the substrates. The necessary vapor pressure must be
reached at a temperature below the substrate temperature to avoid
the condensation of the precursors on the substrate. Due to the
self-limiting growth mechanisms of ALD, relatively low vapor
pressure solid precursors may be used though evaporation rates may
somewhat vary during the process because of changes in their
surface area.
[0041] There are several other characteristics for precursors used
in ALD. The precursors must be thermally stable at the substrate
temperature because their decomposition would destroy the surface
control and accordingly the advantages of the ALD method that
relies on the reaction of the precursor at the substrate surface. A
slight decomposition, if slow compared to the ALD growth, may be
tolerated.
[0042] The precursors have to chemisorb on or react with the
surface, though the interaction between the precursor and the
surface as well as the mechanism for the adsorption is different
for different precursors. The molecules at the substrate surface
must react aggressively with the second precursor to form the
desired solid layer. Additionally, precursors should not react with
the layer to cause etching, and precursors should not dissolve in
the layer. Using highly reactive precursors in ALD contrasts with
the selection of precursors for conventional CVD.
[0043] The by-products in the reaction must be gaseous in order to
allow their easy removal from the reaction chamber. Further, the
by-products should not react or adsorb on the surface.
[0044] In a reaction sequence ALD (RS-ALD) process, the
self-limiting process sequence involves sequential surface chemical
reactions. RS-ALD relies on chemistry between a reactive surface
and a reactive molecular precursor. In an RS-ALD process, molecular
precursors are pulsed into the ALD reaction chamber separately. The
metal precursor reaction at the substrate is typically followed by
an inert gas pulse to remove excess precursor and by-products from
the reaction chamber prior to pulsing the next precursor of the
fabrication sequence.
[0045] By RS-ALD, layers can be layered in equal metered sequences
that are all identical in chemical kinetics, deposition per cycle,
composition, and thickness. RS-ALD sequences generally deposit less
than a full layer per cycle. Typically, a deposition or growth rate
of about 0.25 to about 2.00 .ANG. per RS-ALD cycle may be
realized.
[0046] The characteristics of RS-ALD include continuity at an
interface, conformality over a substrate, use of low temperature
and mildly oxidizing processes, freedom from first wafer effects
and chamber dependence, growth thickness dependent solely on the
number of cycles performed, and ability to engineer multilayer
laminate layers with resolution of one to two monolayers. RS-ALD
allows for deposition control on the order on monolayers and the
ability to deposit monolayers of amorphous layers.
[0047] Herein, a sequence refers to the ALD material formation
based on an ALD reaction of a precursor or a precursor with its
reactant precursor. For example, forming a metal layer from a
precursor containing the metal forms an embodiment of a metal
sequence. Additionally, forming a layer of metal oxide from a
precursor containing the metal and from an oxygen containing
precursor as its reactant precursor forms an embodiment of a
metal/oxygen sequence, which may be referred to as the metal oxide
sequence. A cycle of a metal sequence includes pulsing a precursor
containing the metal and pulsing a purging gas for the precursor.
Further, a cycle of a metal oxide sequence includes pulsing a
precursor containing the metal, pulsing a purging gas for the
precursor, pulsing a reactant precursor, and pulsing a purging gas
for the reactant precursor. Additionally, a cycle for a compound
metal oxide includes pulsing a precursor containing a first metal,
pulsing a purging gas for this precursor, pulsing a reactant
precursor for the first metal precursor, pulsing a purging gas for
the reactant precursor, pulsing a precursor containing a second
metal, pulsing a purging gas for this precursor, pulsing a reactant
precursor for the second metal precursor, and pulsing a purging gas
for this reactant precursor. The order of the metal precursors can
depend on the compatibility of the metals with diffusion of atoms
through the metal to the underlying substrate. Typically, the order
employed limits the amount of unwanted atomic diffusion to the
substrate surface.
[0048] An embodiment for a method for forming a dielectric layer
containing zirconium aluminum oxide, ZrAl.sub.xO.sub.y, by atomic
layer deposition includes pulsing a precursor containing zirconium
onto a substrate, pulsing a first precursor containing oxygen,
pulsing a precursor containing aluminum, and pulsing a second
precursor containing oxygen. In an embodiment, a layer of
ZrAl.sub.xO.sub.y is formed on a substrate by atomic layer
deposition with an interfacial layer of silicon oxide or a silicate
limited to significantly less than ten angstroms.
[0049] A dielectric layer containing ZrAl.sub.xO.sub.y has a larger
dielectric constant than silicon dioxide, a relatively small
leakage current, and good stability with respect to a silicon based
substrate. Such dielectric layers provide a significantly thinner
equivalent oxide thickness compared with a silicon oxide layer
having the same physical thickness. Alternately, such dielectric
layers provide a significantly thicker physical thickness than a
silicon oxide layer having the same equivalent oxide thickness.
Embodiments include structures for capacitors, transistors, memory
devices, and electronic systems with dielectric layers containing
atomic layer deposited ZrAl.sub.xO.sub.y, and methods for forming
such structures.
[0050] In an embodiment, a layer of ZrAl.sub.xO.sub.y is formed on
a substrate mounted in a reaction chamber by ALD using precursor
gases individually pulsed into the reaction chamber. Alternately,
solid or liquid precursors may be used in an appropriately designed
reaction chamber.
[0051] FIG. 2A shows an embodiment of an atomic layer deposition
system 200 for processing a dielectric layer containing
ZrAl.sub.xO.sub.y. The elements depicted are those elements
necessary for discussion of embodiments of the present subject
matter such that those skilled in the art may practice various
embodiments of the present subject matter without undue
experimentation. A further discussion of the ALD reaction chamber
can be found in co-pending, commonly assigned U.S. patent
application: entitled "Methods, Systems, and Apparatus for Uniform
Chemical-Vapor Depositions," Ser. No. 09/797,324, filed 1 Mar.
2001, incorporated herein by reference.
[0052] In FIG. 2A, a substrate 210 is located inside a reaction
chamber 220 of ALD system 200. Also located within reaction chamber
220 is a heating element 230, which is thermally coupled to
substrate 210 to control the substrate temperature. A
gas-distribution fixture 240 introduces precursor gases to the
substrate 210. Each precursor gas originates from individual gas
sources 251-254 whose flow is controlled by mass-flow controllers
256-259, respectively. Each gas source, 251-254, provides a
precursor gas either by storing the precursor as a gas or by
providing a location and apparatus for evaporating a solid or
liquid material to form the selected precursor gas. Furthermore,
additional gas sources may be included, one for each metal
precursor employed and one for each reactant precursor associated
with each metal precursor.
[0053] Also included in the ALD system are purging gas sources 261,
262, each of which is coupled to mass-flow controllers 266, 267,
respectively. Furthermore, additional purging gas sources may be
constructed in ALD system 200, one purging gas source for each
precursor gas. For a process that uses the same purging gas for
multiple precursor gases less purging gas sources are used in ALD
system 200.
[0054] Gas sources 251-254 and purging gas sources 261-262 are
coupled by their associated mass-flow controllers to a common gas
line or conduit 270, which is coupled to the gas-distribution
fixture 240 inside reaction chamber 220. Gas conduit 270 is also
coupled to vacuum pump, or exhaust pump, 281 by mass-flow
controller 286 to remove excess precursor gases, purging gases, and
by-product gases at the end of a purging sequence from gas conduit
270.
[0055] Vacuum pump, or exhaust pump, 282 is coupled by mass-flow
controller 287 to remove excess precursor gases, purging gases, and
by-product gases at the end of a purging sequence from reaction
chamber 220. For convenience, control displays, mounting apparatus,
temperature sensing devices, substrate maneuvering apparatus, and
necessary electrical connections as are known to those skilled in
the art are not shown in FIG. 2A.
[0056] FIG. 2B shows an embodiment of a gas-distribution fixture
240 of atomic layer deposition system 200 for processing a
dielectric layer containing ZrAl.sub.xO.sub.y. Gas-distribution
fixture 240 includes a gas-distribution member 242, and a gas inlet
244. Gas inlet 244 couples gas-distribution member 242 to gas
conduit 270 of FIG. 2A. Gas-distribution member 242 includes
gas-distribution holes, or orifices, 246 and gas-distribution
channels 248. In the illustrated embodiment, holes 246 are
substantially circular with a common diameter in the range of 15-20
microns, gas-distribution channels 248 have a common width in the
range of 20-45 microns. The surface 249 of gas distribution member
242 having gas-distribution holes 246 is substantially planar and
parallel to substrate 210 of FIG. 2A. However, other embodiments
use other surface forms as well as shapes and sizes of holes and
channels. The distribution and size of holes may also affect
deposition thickness and thus might be used to assist thickness
control. Holes 246 are coupled through gas-distribution channels
248 to gas inlet 244. Though ALD system 200 is well suited for
practicing the present subject matter, other ALD systems
commercially available may be used.
[0057] Those of ordinary skill in the art of semiconductor
fabrication understand the use, construction and fundamental
operation of reaction chambers for deposition of material layers.
Embodiments of the present subject matter may be practiced on a
variety of such reaction chambers without undue experimentation.
Furthermore, one of ordinary skill in the art will comprehend the
necessary detection, measurement, and control techniques in the art
of semiconductor fabrication upon reading the disclosure.
[0058] The elements of ALD system 200 may be controlled by a
computer. To focus on the use of ALD system 200 in the various
embodiments of the present subject matter, the computer is not
shown. Those skilled in the art can appreciate that the individual
elements such as pressure control, temperature control, and gas
flow within ALD system 200 may be under computer control. In an
embodiment, a computer executes instructions stored in a computer
readable medium to accurately control the integrated functioning of
the elements of ALD system 200 to form a dielectric layer
containing ZrAl.sub.xO.sub.y.
[0059] FIG. 3 illustrates a flow diagram of elements for an
embodiment of a method to process a ZrAl.sub.xO.sub.y dielectric
layer by atomic layer deposition. This embodiment to form
ZrAl.sub.xO.sub.y by atomic layer deposition includes pulsing a
precursor containing zirconium onto a substrate, at block 310,
pulsing a first precursor containing oxygen, at block 320, pulsing
a precursor containing aluminum, at block 330, and pulsing a second
precursor containing oxygen, at block 340. In an embodiment,
pulsing a precursor containing zirconium onto a substrate, at block
310 and pulsing a first precursor containing oxygen, at block 320,
is performed with a single precursor containing zirconium and
oxygen. In an embodiment, pulsing a precursor containing aluminum,
at block 330, and pulsing a second precursor containing oxygen, at
block 340, is performed with a single precursor containing aluminum
and oxygen. In an embodiment, an interface layer formed between the
substrate and the ZrAl.sub.xO.sub.y layer is limited to less than
about 1 nm (10 angstroms). In an embodiment, the ZrAl.sub.xO.sub.y
layer contains Zr.sub.4AlO.sub.9. In an embodiment, an interface
layer formed between the substrate and the ZrAl.sub.xO.sub.y layer
includes silicon oxide or a silicate limited to less than about 1
nm (10 angstroms).
[0060] Performing each atomic layer deposition includes pulsing one
or more precursors into a reaction chamber for a predetermined
period. The predetermined period is individually controlled for
each precursor pulsed into the reaction chamber. Further the
substrate is maintained at a selected temperature for each pulsing
of a precursor, where the selected temperature is set independently
for pulsing each precursor. Additionally, each precursor may be
pulsed into the reaction under separate environmental conditions.
Appropriate temperatures and pressures are maintained dependent on
the nature of the precursor, whether the precursor is a single
precursor or a mixture of precursors.
[0061] Using atomic layer deposition, the pulsing of the precursor
gases is separated by purging the reaction chamber with a purging
gas following each pulsing of a precursor. In an embodiment,
nitrogen gas is used as the purging gas following the pulsing of
each precursor used in a cycle to form a layer of
ZrAl.sub.xO.sub.y. Additionally, the reaction chamber may also be
purged by evacuating the reaction chamber.
[0062] FIG. 4 illustrates a flow diagram of elements for an
embodiment of a method to process a dielectric layer containing
ZrAl.sub.xO.sub.y by atomic layer deposition. This embodiment may
be implemented with the atomic layer deposition system 200 of FIG.
2A, B.
[0063] At block 405, substrate 210 is prepared. The substrate used
for forming a transistor is typically a silicon or silicon
containing material. In other embodiments, germanium, gallium
arsenide, silicon-on-sapphire substrates, or other suitable
substrates may be used. This preparation process may include
cleaning of substrate 210 and forming layers and regions of the
substrate, such as drains and sources of a metal oxide
semiconductor (MOS) transistor, prior to forming a gate dielectric.
In an embodiment, the substrate is cleaned to provide an initial
substrate depleted of its native oxide. In an embodiment, the
initial substrate is cleaned to provide a hydrogen-terminated
surface. In an embodiment, a silicon substrate undergoes a final
hydrofluoric acid, HF, rinse prior to ALD processing to provide the
silicon substrate with a hydrogen-terminated surface without a
native silicon oxide layer.
[0064] In an embodiment, substrate 210 is prepared as a chemical
oxide-terminated silicon surface prior to forming the
ZrAl.sub.xO.sub.y dielectric layer by atomic layer deposition. This
preparation allows for forming an interface layer of about five
angstroms to provide a structure that aids in reducing the leakage
current through the dielectric layer.
[0065] The sequencing of the formation of the regions of the
transistor being processed follows typical sequencing that is
generally performed in the fabrication of a MOS transistor as is
well known to those skilled in the art. Included in the processing
is the masking of substrate regions to be protected during the gate
dielectric formation, as is typically performed in MOS fabrication.
In this embodiment, the unmasked region may include a body region
of a transistor; however one skilled in the art will recognize that
other semiconductor device structures may utilize this process.
Additionally, substrate 210 in its ready for processing form is
conveyed into a position in reaction chamber 220 for ALD
processing.
[0066] At block 410, a zirconium-containing precursor is pulsed
into reaction chamber 220. In an embodiment, ZrCl.sub.4 is used as
a precursor. In another embodiment, ZrI.sub.4 is used as a
precursor. The ZrCl.sub.4 precursor is pulsed into reaction chamber
220 through the gas-distribution fixture 240 on substrate 210.
Mass-flow controller 256 regulates the flow of the ZrCl.sub.4 from
gas source 251. In an embodiment, the substrate temperature is
maintained at about 180.degree. C. In another embodiment, the
substrate temperature is maintained between about 300.degree. C.
and about 500.degree. C. The ZrCl.sub.4 reacts with the surface of
the substrate 210 in the desired region defined by the unmasked
areas of the substrate 210.
[0067] At block 415, a first purging gas is pulsed into reaction
chamber 220. In an embodiment, nitrogen with a purity of about
99.999% is used as a purging gas. Mass-flow controller 266
regulates the nitrogen flow from the purging gas source 261 into
the gas conduit 270. Using the pure nitrogen purge avoids overlap
of the precursor pulses and possible gas phase reactions.
[0068] A first oxygen-containing precursor is pulsed onto substrate
210, at block 420. In an embodiment, water vapor (H.sub.2O) is used
as a precursor. In another embodiment, H.sub.2O.sub.2 is used as a
precursor. In another embodiment, an H.sub.2O--H.sub.2O.sub.2
mixture is used as a precursor. The water vapor precursor is pulsed
into reaction chamber 220 through the gas-distribution fixture 240
on substrate 210. Mass-flow controller 257 regulates the flow of
the water vapor from gas source 252. In an embodiment, the
substrate temperature is maintained at about 180.degree. C. In
another embodiment, the substrate temperature is maintained between
about 300.degree. C. and about 500.degree. C. The water vapor
reacts with at the surface of substrate 210 in the desired region
defined by the unmasked areas of the substrate 210.
[0069] After pulsing the first oxygen-containing precursor, a
second purging gas is pulsed, at block, 425. In an embodiment,
nitrogen is used as the second purging gas. Excess precursor gas,
and reaction by-products are removed from the system by the purge
gas in conjunction with the exhausting of reaction chamber 220
using vacuum pump 282 through mass-flow controller 287, and
exhausting of the gas conduit 270 by the vacuum pump 281 through
mass-flow controller 286.
[0070] In an embodiment using a ZrCl.sub.4/H.sub.2O vapor sequence,
the substrate is held between about 300.degree. C. and about
500.degree. C. by the heating element 230. The ZrCl.sub.4 pulse
time ranges from about 0.2 sec to above 1.0 sec. After the
ZrCL.sub.4 pulse, the zirconium/water vapor sequence continues with
a purge pulse followed by a H.sub.2O pulse followed by a purge
pulse. In an embodiment, the H.sub.2O vapor pulse time may range
from about 0.2 sec to above 1.0 sec, and the ZrCl.sub.4 and the
H.sub.2O vapor purging pulse times are each range from about 0.2
sec to about 4.0 sec.
[0071] In an embodiment using a ZrI.sub.4/H.sub.2O--H.sub.2O.sub.2
vapor sequence, the substrate is held between about 230.degree. C.
and about 500.degree. C. by the heating element 230 with reaction
chamber 220 held at about 250 Pa. In an embodiment, the ZrI.sub.4
pulse time is about 2.0 sec. After the ZrI.sub.4 pulse, the
ZrI.sub.4/H.sub.2O--H.sub.2O.sub.2 vapor sequence continues with a
purge pulse followed by an H.sub.2O-H.sub.2O.sub.2 vapor pulse
followed by a purge pulse. In an embodiment, the
H.sub.2O-H.sub.2O.sub.2 vapor pulse time is about 2.0 sec, and the
ZrI.sub.4 and the H.sub.2O--H.sub.2O.sub.2 vapor purging pulse
times are each at about 2.0 sec.
[0072] After pulsing the second purging gas, an aluminum-containing
precursor is pulsed into reaction chamber 220, at block 430. In an
embodiment, the aluminum-containing precursor is trimethylaluminum
(TMA), Al(CH.sub.3).sub.3. In another embodiment, the
aluminum-containing precursor is DMEAA, an adduct of alane
(AlH.sub.3) and dimethylehtylamine
{N(CH.sub.3).sub.2(C.sub.2H.sub.5)}. The trimethylaluminum
precursor is pulsed into reaction chamber 220 through the
gas-distribution fixture 240 on substrate 210. Mass-flow controller
258 regulates the flow of the trimethylaluminum from gas source
253. In an embodiment, the substrate temperature is maintained
between about 300.degree. C. and about 500.degree. C. The
trimethylaluminum aggressively reacts at the current surface of
substrate 210.
[0073] At block 435, a third purging gas is introduced into the
system. Nitrogen gas may also be used as a purging and carrier gas.
The nitrogen flow is controlled by mass-flow controller 267 from
the purging gas source 262 into the gas conduit 270 and
subsequently into reaction chamber 220. In another embodiment,
argon gas may be used as the purging gas.
[0074] A second oxygen-containing precursor is pulsed on substrate
210, at block 440. In an embodiment, water vapor (H.sub.2O) is used
as a precursor. In another embodiment, H.sub.2O.sub.2 is used as a
precursor. In another embodiment, an H.sub.2O--H.sub.2O.sub.2
mixture is used as a precursor. The water vapor precursor is pulsed
into reaction chamber 220 through the gas-distribution fixture 240
on substrate 210. Mass-flow controller 259 regulates the flow of
the water vapor from gas source 254. The water vapor reacts
aggressively at the current surface of substrate 210.
[0075] After pulsing the second oxygen-containing precursor, a
fourth purging gas is pulsed, at block, 445. In an embodiment,
nitrogen is used as the second purging gas. Excess precursor gas,
and reaction by-products are removed from the system by the purge
gas in conjunction with the exhausting of reaction chamber 220
using vacuum pump 282 through mass-flow controller 287, and
exhausting of the gas conduit 270 by the vacuum pump 281 through
mass-flow controller 286. With the conclusion of the fourth purging
gas pulse, a cycle forming atomic layer deposited ZrAl.sub.xO.sub.y
is completed.
[0076] During the TMA/water vapor sequence, the substrate is held
between about 350.degree. C. and about 450.degree. C. by the
heating element 230. The process pressure is maintained at about
230 mTorr during the pulsing of the precursor gases and at about
200 mTorr for the purging gases. Pulse times for the TMA and the
water vapor were about 1 sec for both precursors, with purging
pulse times of about 15 s.
[0077] As an alternate aluminum sequence, a DMEAA/oxygen sequence
can be employed rather than the TMA/water vapor sequence with the
substrate held between about 100.degree. C. and about 125.degree.
C. by the heating element 230. In an embodiment, the substrate is
held at about 350.degree. C. during the DMEAA/oxygen sequence. The
process pressure during the DMEAA/oxygen sequence is maintained at
about 30 mTorr.
[0078] At block 450, a determination is made as to whether a
desired number of cycles has been performed, that is, whether the
number of completed cycles is equal to a predetermined number. The
predetermined number corresponds to a predetermined thickness for
the ALD ZrAl.sub.xO.sub.y dielectric layer. If the number of
completed cycles is less than the predetermined number, the
zirconium-containing precursor is pulsed into reaction chamber 220,
at block 410, and the process continues. If the total number of
cycles to form the desired thickness has been completed, the
dielectric layer containing ZrAl.sub.xO.sub.y may be annealed. To
avoid the diffusion of oxygen during annealing to the semiconductor
substrate surface, any annealing may be performed in an oxygen-free
environment for short periods of time. An embodiment of an
annealing environment may include a nitrogen atmosphere. In
addition to limiting or avoiding oxygen diffusion to the
semiconductor substrate, the relatively low temperatures employed
by atomic layer deposition of a ZrAl.sub.xO.sub.y dielectric layer
allows for the formation of an amorphous ZrAl.sub.xO.sub.y
dielectric layer.
[0079] The thickness of a ZrAl.sub.xO.sub.y layer is determined by
a fixed growth rate for the pulsing periods and precursors used,
set at a value such as N nm/cycle. For a desired ZrAl.sub.xO.sub.y
layer thickness, t, in an application such as forming a gate
dielectric of a MOS transistor, the ALD process is repeated for t/N
total cycles. Once the t/N cycles have completed, no further ALD
processing for ZrAl.sub.xO.sub.y is performed. In an embodiment,
ALD processing provides for the engineering of a dielectric layer
containing ZrAl.sub.xO.sub.y having a dielectric constant in the
range from about 9 to about 25.
[0080] At block 455, after forming the ZrAl.sub.xO.sub.y,
processing the device having the dielectric layer containing
ZrAl.sub.xO.sub.y is completed. In an embodiment, completing the
device includes completing the formation of a transistor. In an
embodiment, completing the device includes completing the formation
of a capacitor. Alternately, completing the process includes
completing the construction of a memory device having an array with
access transistors formed with gate dielectrics containing atomic
layer deposited ZrAl.sub.xO.sub.y. In an embodiment, completing the
process includes the formation of an electronic system including an
information handling device that uses electronic devices with
transistors formed with dielectric layers containing atomic layer
deposited ZrAl.sub.xO.sub.y. Typically, information handling
devices such as computers include many memory devices, having many
access transistors.
[0081] Upon reading and comprehending this disclosure, it can be
appreciated by those skilled in the art that the elements of a
method for forming an atomic layer deposited ZrAl.sub.xO.sub.y
layer in the embodiment of FIG. 4 may be performed under various
other environmental conditions, including various pressures and
temperatures, and pulse periods depending on the ZrAl.sub.xO.sub.y
layer to be formed for a given application and the system used to
fabricate the ZrAl.sub.xO.sub.y layer. Determination of the
environmental conditions, precursors used, purging gases employed,
and pulse periods for the precursors and purging gases may be made
without undue experimentation.
[0082] Atomic layer deposition of a ZrAl.sub.xO.sub.y dielectric
layer may be processed in an atomic layer deposition system such as
ALD system 200 under computer control to perform various
embodiments, and operated under computer-executable instructions to
perform these embodiments. In an embodiment, a computerized method
and the computer-executable instructions for a method for forming a
ZrAl.sub.xO.sub.y dielectric layer by atomic layer deposition
includes pulsing a precursor containing zirconium onto a substrate,
pulsing a first precursor containing oxygen, pulsing a precursor
containing aluminum, and pulsing a second precursor containing
oxygen. In an embodiment, pulsing the precursor containing
zirconium and pulsing the first precursor containing oxygen
includes pulsing a precursor containing both zirconium and oxygen
in one pulsing process. In an embodiment, pulsing the precursor
containing aluminum and pulsing the second precursor containing
oxygen includes pulsing a precursor containing both aluminum and
oxygen in one pulsing process.
[0083] In an embodiment, a computerized method and the
computer-executable instructions for a method for forming a
ZrAl.sub.xO.sub.y dielectric layer include forming the
ZrAl.sub.xO.sub.y dielectric layer by atomic layer deposition,
where each precursor is pulsed into a reaction chamber for a
predetermined period. The predetermined period is individually
controlled for each precursor pulsed into the reaction chamber.
Further, the substrate may be maintained at a selected temperature
for each pulsing of a precursor, where the selected temperature is
set independently for pulsing each precursor. In addition, each
pulsing of a precursor is followed by purging the reaction chamber
with a purging gas.
[0084] In an embodiment, a computerized method and the
computer-executable instructions for a method for forming a
dielectric layer include regulating the deposition of zirconium,
aluminum, and oxygen to form a dielectric layer having a dielectric
constant in the range from about 9 to about 25.
[0085] In an embodiment, a computerized method and the
computer-executable instructions for a method for forming a
dielectric layer containing ZrAl.sub.xO.sub.y include controlling
an environment of a reaction chamber. Additionally, the
computerized method controls the pulsing of purging gases, one for
each precursor gas and pulsing each purging gas after pulsing the
associated precursor gas. Using a computer to control parameters
for growing the ZrAl.sub.xO.sub.y dielectric layer provides for
processing the ZrAl.sub.xO.sub.y dielectric layer over a wide range
of parameters allowing for the determination of an optimum
parameter set for the ALD system used. The computer-executable
instructions may be provided in any computer-readable medium. Such
computer-readable medium may include, but is not limited to, floppy
disks, diskettes, hard disks, CD-ROMS, flash ROMS, nonvolatile ROM,
and RAM.
[0086] An embodiment of this method may be realized using ALD
system 200 of FIG. 2A, where the controls for the individual
elements of ALD system 200 are coupled to a computer, not shown in
FIG. 2A. The computer provides control of the operation for
processing a ZrAl.sub.xO.sub.y dielectric layer by regulating the
flow of precursor gases into reaction chamber 220. The computer
controls the flow rate of precursor gases and the pulsing periods
for these gases by controlling mass-flow controllers 256-259.
Additionally, the computer controls the temperature of gas sources
251-254. Further, the pulse period and flow of purging gases from
purging gas sources 261, 262 is regulated through computer control
of mass-flow controllers 266, 267, respectively.
[0087] The computer also regulates the environment of reactor
chamber 220 in which a dielectric layer is being formed on
substrate 210. The computer regulates the pressure in reaction
chamber 220 within a predetermined pressure range by controlling
vacuum pumps 281, 282 through mass-flow controllers 286, 287,
respectively. The computer also regulates the temperature range for
substrate 210 within a predetermined range by controlling heater
230.
[0088] For convenience, the individual control lines to elements of
ALD 200, as well as a computer, are not shown in FIG. 2A. The above
description of the computer control in conjunction with FIG. 2A
provides information for those skilled in the art to practice
embodiments for forming a dielectric layer containing
ZrAl.sub.xO.sub.y using a computerized method as described
herein.
[0089] The embodiments described herein provide a process for
growing a ZrAl.sub.xO.sub.y dielectric layer having a wide range of
useful equivalent oxide thickness, t.sub.eq, associated with a
dielectric constant in the range from about 9 to about 25. The
t.sub.eq range in accordance with embodiments of the present
subject matter are shown in the following: TABLE-US-00001 Physical
Physical Physical Physical Thickness Thickness Thickness Thickness
t = 1.0 nm t = 2.0 nm t = 5.0 nm t = 10.0 nm (10 .ANG.) (20 .ANG.)
(50 .ANG.) (100 .ANG.) .kappa. t.sub.eq (.ANG.) t.sub.eq (.ANG.)
t.sub.eq (.ANG.) t.sub.eq (.ANG.) 9 4.33 8.67 21.67 43.33 12 3.25
6.50 16.25 32.50 15 2.60 5.20 13.00 26.00 20 1.95 3.90 9.75 19.50
25 1.56 3.12 7.80 15.60
[0090] The relatively large dielectric constant for
ZrAl.sub.xO.sub.y layers allows for the engineering of dielectric
layers having a physical thickness in the 10 nm (100 .ANG.) range,
while achieving a t.sub.eq of less than 5 nm (50 .ANG.). From
above, it is apparent that a layer containing ZrAl.sub.xO.sub.y may
be attained with a t.sub.eq ranging from about 1.5 .ANG. to about 9
.ANG.. Further, an atomic layer deposited ZrAl.sub.xO.sub.y layer
may provide a t.sub.eq significantly less than 2 or 3 .ANG., even
less than 1.5 .ANG..
[0091] Attainment of a t.sub.eq in the thickness range of one to a
several monolayers is associated with an interfacial layer between
a semiconductor substrate surface and the ZrAl.sub.xO.sub.y
dielectric layer that is exceptionally small or composed of a
material having a dielectric constant approaching that of the
ZrAl.sub.xO.sub.y value. To obtain the smallest possible t.sub.eq,
the formation of a SiO.sub.2 interfacial layer should be avoided.
However, having a silicon oxide layer or a silicate layer between
the substrate and the ZrAl.sub.xO.sub.y layer can aid in the
reduction of leakage current. In an embodiment, an interfacial
layer of silicon oxide or a silicate is limited to about 5
angstroms. In an embodiment, other materials can be used to form an
interfacial layer between the substrate and the ZrAl.sub.xO.sub.y
layer. Such an interfacial layer aids in providing a low density of
electronic states at the substrate interface, in reducing leakage
current, and in providing a diffusion barrier depending on the
material forming the interfacial layer. In an embodiment, the
interfacial layer is limited to less than about 1 nm (10 .ANG.).
However, an interfacial layer of material having a dielectric
constant less than that of the ZrAl.sub.xO.sub.y layer formed
reduces the overall dielectric constant of the effective dielectric
layer containing the ZrAl.sub.xO.sub.y layer and the interfacial
layer.
[0092] Dielectric layers containing ZrAl.sub.xO.sub.y using
embodiments of the present subject matter may be engineered with
various structures and compositions including an amorphous
structure with an approximate average composition
Zr.sub.4AlO.sub.9, a uniform distribution of the elements of the
oxide through the film with an abrupt interface with a silicon
substrate, a dielectric material whose properties are similar to a
double oxide, Zr--O and Al--O, without ZrO.sub.2--AL.sub.2O.sub.3
present in the dielectric layer, and/or a thin silicon oxide or a
silicate interface layer with a thickness significantly less than 1
nm (10 .ANG.).
[0093] Any micro-roughness associated with thin layers of
ZrAl.sub.xO.sub.y may be due to partial monolayer formation of the
dielectric layer across the substrate surface. With some areas of
the dielectric layer forming a monolayer in two or three cycles,
while another area or region of the layer forms a monolayer in one
or two cycles, the surface of the ZrAl.sub.xO.sub.y dielectric
layer may exhibit some micro-roughness. As can be understood by
those skilled in the art, particular growth rates and processing
conditions for providing a ZrAl.sub.xO.sub.y dielectric layer with
reduced or substantially eliminated micro-roughness may be
determined during normal initial testing of the ALD system for
processing a ZrAl.sub.xO.sub.y dielectric layer for a given
application without undue experimentation.
[0094] Further, ZrAl.sub.xO.sub.y dielectric layers formed by
atomic layer deposition may provide not only ultra thin t.sub.eq
layers, but also layers with relatively low leakage current. In
addition to using ALD to provide precisely engineered layer
thicknesses with engineered dielectric constants, good breakdown
electric field properties, and relatively low leakage currents, ALD
processing provides for dielectric layers that provide conformal
layering on selected substrate surfaces.
[0095] Embodiments of processes described above for performing
atomic layer deposition of ZrAl.sub.xO.sub.y are used to precisely
control the thickness of the dielectric layer formed, where, in
addition to providing an ultra thin t.sub.eq, the atomic layer
deposition process provides for relatively smooth surfaces and
limited interfacial layer formation. Additionally, these
embodiments for ALD processing of ZrAl.sub.xO.sub.y dielectric
layers may be implemented to form transistors, capacitors, memory
devices, and other electronic systems including electro-optic
devices, microwave devices, and information handling devices. With
careful preparation and engineering of the ZrAl.sub.xO.sub.y layer,
limiting the size of interfacial regions, a teq less than about 10
.ANG. for these devices is anticipated.
[0096] A transistor 100 as depicted in FIG. 1 may be constructed by
forming a source region 120 and a drain region 130 in a silicon
based substrate 110 where source and drain regions 120, 130 are
separated by a body region 132. Body region 132 defines a channel
having a channel length 134. A dielectric layer is disposed on
substrate 110 formed as a layer containing ZrAl.sub.xO.sub.y by
atomic layer deposition. The resulting ZrAl.sub.xO.sub.y dielectric
layer forms gate dielectric 140.
[0097] A gate 150 is formed over gate dielectric 140. Typically,
forming gate 150 may include forming a polysilicon layer, though a
metal gate may be formed in an alternative process. An interfacial
layer 133 formed between gate dielectric 140 and body region 132 is
limited to a thickness less than 1 nm (10 .ANG.). In an embodiment,
interfacial layer 133 is eliminated or reduced to a thickness that
can not be measured or determined to have a significant effect on
the dielectric constant of the region between gate 150 and body
region 132. Forming the substrate, the source and drain regions,
and the gate is performed using standard processes known to those
skilled in the art. Additionally, the sequencing of the various
elements of the process for forming a transistor is conducted with
standard fabrication processes, also as known to those skilled in
the art.
[0098] The method for forming an atomic layer deposited
ZrAl.sub.xO.sub.y in various embodiments may be applied to other
transistor structures having dielectric layers. FIG. 5A shows an
embodiment of a configuration of a transistor 500 having an atomic
layer deposited ZrAl.sub.xO.sub.y dielectric layer. Transistor 500
includes a silicon based substrate 510 with a source 520 and a
drain 530 separated by a body region 532. Body region 532 between
source 520 and drain 530 defines a channel region having a channel
length 534. Located above body region 532 is a stack 555 including
a gate dielectric 540, a floating gate 552, a floating gate
dielectric 542, and a control gate 550. Gate dielectric 540 may be
formed containing atomic layer deposited ZrAl.sub.xO.sub.y
described above with the remaining elements of the transistor 500
formed using processes known to those skilled in the art.
Alternately, both gate dielectric 540 and floating gate dielectric
542 may be formed as dielectric layers containing ZrAl.sub.xO.sub.y
in various embodiments as described herein. An interfacial layer
533 formed between gate dielectric 540 and body region 532 is
limited to a thickness less than 1 nm (10 .ANG.). In an embodiment,
interfacial layer 533 is eliminated or reduced to a thickness that
can not be measured or determined to have a significant effect on
the dielectric constant of the region between floating gate 552 and
body region 532. In an embodiment with floating gate dielectric 542
formed containing ZrAl.sub.xO.sub.y, an interfacial layer between
floating gate dielectric 542 and floating gate 552 is limited to
less than 1 nm (10 .ANG.) or effectively eliminated.
[0099] The embodiments of methods for forming ZrAl.sub.xO.sub.y
dielectric layers may also be applied to forming capacitors in
various integrated circuits, memory devices, and electronic
systems. In an embodiment for forming a capacitor 560 illustrated
in FIG. 5B, a method includes forming a first conductive layer 570,
forming a dielectric layer 580 containing ZrAl.sub.xO.sub.y on
first conductive layer 570 by atomic layer deposition, and forming
a second conductive layer 590 on dielectric layer 580. An
interfacial layer 575 formed between dielectric layer 580 and first
conductive layer 570 is limited to a thickness less than 1 nm (10
.ANG.). In an embodiment, interfacial layer 575 is eliminated or
reduced to a thickness that can not be measured or determined to
have a significant effect on the dielectric constant of the region
between first conductive layer 570 and second conductive layer 590.
ALD formation of the ZrAl.sub.xO.sub.y dielectric layer allows the
dielectric layer to be engineered within a predetermined
composition providing a desired dielectric constant.
[0100] Transistors, capacitors, and other devices having
ZrAl.sub.xO.sub.y dielectric layers formed by atomic layer
deposition using methods described herein may be implemented into
memory devices and electronic systems including information
handling devices. Such information devices may include wireless
systems, telecommunication systems, and computers. An embodiment of
a computer having a ZrAl.sub.xO.sub.y dielectric layer formed by
atomic layer deposition using methods described herein is shown in
FIGS. 6-8 and described below. While specific types of memory
devices and computing devices are shown below, it will be
recognized by one skilled in the art that several types of memory
devices and electronic systems including information handling
devices utilize the present subject matter.
[0101] A personal computer 600, as shown in FIGS. 6 and 7, includes
a monitor 601, keyboard input 602, and a central processing unit
604. Central processor unit 604 typically includes microprocessor
706, memory bus circuit 708 having a plurality of memory slots
712(a-n), and other peripheral circuitry 710. Peripheral circuitry
710 permits various peripheral devices 724 to interface
processor-memory bus 720 over input/output (I/O) bus 722. The
personal computer shown in FIGS. 6 and 7 also includes at least one
transistor having a ZrAl.sub.xO.sub.y dielectric layer formed by
atomic layer deposition using methods described herein according to
an embodiment of the present subject matter.
[0102] Microprocessor 706 produces control and address signals to
control the exchange of data between memory bus circuit 708 and
microprocessor 706 and between memory bus circuit 708 and
peripheral circuitry 710. This exchange of data is accomplished
over high speed memory bus 720 and over high speed I/O bus 722.
[0103] Coupled to memory bus 720 are pluralities of memory slots
712(a-n), which receive memory devices well known to those skilled
in the art. For example, single in-line memory modules (SIMMs) and
dual in-line memory modules (DIMMs) may be used in the
implementation of an embodiment of the present subject matter.
[0104] These memory devices may be produced in a variety of designs
that provide different methods of reading from and writing to the
dynamic memory cells of memory slots 712. One such method is the
page mode operation. Page mode operations in a DRAM are defined by
the method of accessing a row of a memory cell arrays and randomly
accessing different columns of the array. Data stored at the row
and column intersection may be read and output while that column is
accessed. Page mode DRAMs use access steps, which limit the
communication speed of memory circuit 708.
[0105] An alternate type of device is the extended data output
(EDO) memory, which allows data stored at a memory array address to
be available as output after the addressed column has been closed.
This memory may increase some communication speeds by allowing
shorter access signals without reducing the time in which memory
output data is available on memory bus 720. Other alternative types
of devices include SDRAM, DDR SDRAM, SLDRAM and Direct RDRAM as
well as others such as SRAM or Flash memories.
[0106] FIG. 8 illustrates a schematic view of an embodiment of a
DRAM memory device 800 having an atomic layer deposited
ZrAl.sub.xO.sub.y dielectric layer formed according to an
embodiment described herein. Illustrative DRAM memory device 800 is
compatible with memory slots 712(a-n). The description of DRAM
memory device 800 has been simplified for purposes of illustrating
a DRAM memory device and is not intended to be a complete
description of all the features of a DRAM. Those skilled in the art
will recognize that a wide variety of memory devices may be used in
the implementation of embodiments of the present subject matter.
The embodiment of a DRAM memory device shown in FIG. 8 includes at
least one transistor having a ZrAl.sub.xO.sub.y dielectric layer
formed by atomic layer deposition using methods described herein
according to the teachings of the present subject matter.
[0107] Control, address and data information provided over memory
bus 720 is further represented by individual inputs to DRAM 800, as
shown in FIG. 8. These individual representations are illustrated
by data lines 802, address lines 804 and various discrete lines
directed to control logic 806.
[0108] As is well known in the art, DRAM 800 includes memory array
810, which in turn comprises rows and columns of addressable memory
cells. Each memory cell in a row is coupled to a common word line.
The word line is coupled to gates of individual transistors, where
at least one transistor has a gate coupled to a gate dielectric
containing ZrAl.sub.xO.sub.y formed by atomic layer deposition in
accordance with the method and structure previously described
above. Additionally, each memory cell in a column is coupled to a
common bit line. Each cell in memory array 810 may include a
storage capacitor and an access transistor as is conventional in
the art.
[0109] DRAM 800 interfaces with, for example, microprocessor 706
through address lines 804 and data lines 802. Alternatively, DRAM
800 may interface with a DRAM controller, a micro-controller, a
chip set or other electronic system. Microprocessor 706 also
provides a number of control signals to DRAM 800, including but not
limited to, row and column address strobe signals RAS and CAS,
write enable signal WE, an output enable signal OE and other
conventional control signals.
[0110] Row address buffer 812 and row decoder 814 receive and
decode row addresses from row address signals provided on address
lines 804 by microprocessor 706. Each unique row address
corresponds to a row of cells in memory array 810. Row decoder 814
may include a word line driver, an address decoder tree, and
circuitry which translates a given row address received from row
address buffers 812 and selectively activates the appropriate word
line of memory array 810 via the word line drivers.
[0111] Column address buffer 816 and column decoder 818 receive and
decode column address signals provided on address lines 804. Column
decoder 818 also determines when a column is defective and the
address of a replacement column. Column decoder 818 is coupled to
sense amplifiers 820. Sense amplifiers 820 are coupled to
complementary pairs of bit lines of memory array 810.
[0112] Sense amplifiers 820 are coupled to data-in buffer 822 and
data-out buffer 824. Data-in buffers 822 and data-out buffers 824
are coupled to data lines 802. During a write operation, data lines
802 provide data to data-in buffer 822. Sense amplifier 820
receives data from data-in buffer 822 and stores the data in memory
array 810 as a charge on a capacitor of a cell at an address
specified on address lines 804.
[0113] During a read operation, DRAM 800 transfers data to
microprocessor 706 from memory array 810. Complementary bit lines
for the accessed cell are equilibrated during a precharge operation
to a reference voltage provided by an equilibration circuit and a
reference voltage supply. The charge stored in the accessed cell is
then shared with the associated bit lines. A sense amplifier of
sense amplifiers 820 detects and amplifies a difference in voltage
between the complementary bit lines. The sense amplifier passes the
amplified voltage to data-out buffer 824.
[0114] Control logic 806 is used to control the many available
functions of DRAM 800. In addition, various control circuits and
signals not detailed herein initiate and synchronize DRAM 800
operation as known to those skilled in the art. As stated above,
the description of DRAM 800 has been simplified for purposes of
illustrating an embodiment of the present subject matter and is not
intended to be a complete description of all the features of a
DRAM. Those skilled in the art will recognize that a wide variety
of memory devices, including but not limited to, SDRAMs, SLDRAMs,
RDRAMs and other DRAMs and SRAMs, VRAMs and EEPROMs, may be used in
the implementation of embodiments of the present subject matter.
The DRAM implementation described herein is illustrative only and
not intended to be exclusive or limiting.
[0115] A ZrAl.sub.xO.sub.y dielectric layer, formed by atomic layer
deposition using methods described herein, provides a reliable
dielectric layer having an equivalent oxide thickness thinner than
attainable using SiO.sub.2. Dielectric layers containing atomic
layer deposited ZrAl.sub.xO.sub.y formed using the methods
described herein are thermodynamically stable such that the
dielectric layers formed will have minimal reactions with a silicon
substrate or other structures during processing.
[0116] Forming ZrAl.sub.xO.sub.y layers by atomic layer deposition
in relatively low processing temperatures allows for
ZrAl.sub.xO.sub.y layers that are amorphous and conformally layered
on a substrate surface. Further, the ALD formation of a
ZrAl.sub.xO.sub.y dielectric layer provides for enhanced dielectric
and electrical properties relative to those attained with an
amorphous SiO.sub.x layer. Additionally, embodiments for the ALD
processing of ZrAl.sub.xO.sub.y layers provide for the formation of
interfacial layers between a substrate and a ZrAl.sub.xO.sub.y
layer that is limited to less than about 1 nm (.ANG.), where the
interfacial layer aids in providing a low density of electronic
states at the substrate interface, in reducing leakage current, and
in providing a diffusion barrier depending on the material forming
the interfacial layer. These properties of ZrAl.sub.xO.sub.y
dielectric layers allow for application as dielectric layers in
numerous devices and systems.
[0117] Capacitors, transistors, electro-optic devices, higher level
ICs or devices, and electronic systems are constructed utilizing
various embodiments of the process for forming a ZrAl.sub.xO.sub.y
dielectric layer having an ultra thin equivalent oxide thickness,
t.sub.eq. Gate dielectric layers or layers containing atomic layer
deposited ZrAl.sub.xO.sub.y are formed having a dielectric constant
substantially higher than that of silicon oxide, where the
ZrAl.sub.xO.sub.y dielectric layers are capable of a t.sub.eq
thinner than 10 .ANG., thinner than the expected limit for
SiO.sub.2 gate dielectrics. The thinner t.sub.eq of these
dielectric layers allows for a higher capacitance than SiO.sub.2
gate dielectrics, which provides further effective scaling for
microelectronic devices and systems. At the same time, the physical
thickness of the atomic layer deposited ZrAl.sub.xO.sub.y
dielectric layer is much larger than the SiO.sub.2 thickness
associated with the t.sub.eq limit of SiO.sub.2. Forming the larger
thickness aids in the manufacturing process for gate dielectrics
and other dielectric layers.
[0118] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement that is calculated to achieve the
same purpose may be substituted for the specific embodiments shown.
This application is intended to cover any adaptations or variations
of the present subject matter. It is to be understood that the
above description is intended to be illustrative, and not
restrictive. Combinations of the above embodiments, and other
embodiments will be apparent to those of skill in the art upon
reviewing the above description. The scope of the present subject
matter includes any other applications in which the above
structures and fabrication methods are used. The scope of the
present subject matter should be determined with reference to the
appended claims, along with the full scope of equivalents to which
such claims are entitled.
* * * * *