U.S. patent application number 11/457987 was filed with the patent office on 2006-11-02 for atomic layer deposited nanolaminates of hfo2/zro2 films as gate dielectrics.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Kie Y. Ahn, Leonard Forbes.
Application Number | 20060246741 11/457987 |
Document ID | / |
Family ID | 31187088 |
Filed Date | 2006-11-02 |
United States Patent
Application |
20060246741 |
Kind Code |
A1 |
Ahn; Kie Y. ; et
al. |
November 2, 2006 |
ATOMIC LAYER DEPOSITED NANOLAMINATES OF HfO2/ZrO2 FILMS AS GATE
DIELECTRICS
Abstract
A dielectric film containing a nanolaminate with a hafnium oxide
layer and a zirconium oxide layer and a method of fabricating such
a dielectric film produce a reliable gate dielectric having an
equivalent oxide thickness thinner than attainable using silicon
oxide.
Inventors: |
Ahn; Kie Y.; (Chappaqua,
NY) ; Forbes; Leonard; (Corvallis, OR) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH, P.A.
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
31187088 |
Appl. No.: |
11/457987 |
Filed: |
July 17, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11148505 |
Jun 9, 2005 |
|
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11457987 |
Jul 17, 2006 |
|
|
|
10209581 |
Jul 30, 2002 |
6921702 |
|
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11148505 |
Jun 9, 2005 |
|
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|
Current U.S.
Class: |
438/785 ;
438/240 |
Current CPC
Class: |
C23C 16/45529 20130101;
H01L 21/02266 20130101; H01L 21/28194 20130101; H01L 21/31645
20130101; H01L 21/31641 20130101; H01L 29/517 20130101; H01L
21/02205 20130101; H01L 21/02181 20130101; H01L 21/02189 20130101;
H01L 29/513 20130101; Y10S 977/891 20130101; Y10S 977/843 20130101;
H01L 21/0228 20130101; H01L 21/022 20130101; H01L 21/02269
20130101; Y10S 977/811 20130101; H01L 21/28185 20130101; C23C
16/405 20130101; H01L 21/31604 20130101; H01L 21/31683 20130101;
H01L 21/02271 20130101; H01L 21/3142 20130101; H01L 21/28229
20130101; H01L 21/28202 20130101 |
Class at
Publication: |
438/785 ;
438/240 |
International
Class: |
H01L 21/31 20060101
H01L021/31; H01L 21/469 20060101 H01L021/469; H01L 21/8242 20060101
H01L021/8242 |
Claims
1. A method comprising: forming a layer of hafnium oxide by
layering one or more individual monolayers of hafnium oxide;
forming a layer of zirconium oxide on the layer of hafnium oxide to
form a nanolaminate including the layer of hafnium oxide and the
layer of zirconium oxide, wherein the layer of zirconium oxide is
formed by one or more of pulsed-laser deposition or jet-vapor
deposition.
2. The method of claim 1, wherein the method includes forming the
layer of hafnium oxide as an initial layer of the nanolaminate and
forming another layer of hafnium oxide as the final layer of the
nanolaminate.
3. The method of claim 1, wherein forming a layer of hafnium oxide
by layering one or more individual monolayers includes forming the
layer of hafnium oxide by atomic layer deposition.
4. The method of claim 3, wherein forming the layer of hafnium
oxide by atomic layer deposition includes using a HfI.sub.4
precursor in the atomic layer deposition.
5. The method of claim 1, wherein the method includes forming the
nanolaminate as a gate dielectric in a transistor.
6. The method of claim 1, wherein the method includes forming the
nanolaminate as a floating gate dielectric in a transistor.
7. The method of claim 1, wherein the method includes forming the
nanolaminate as a dielectric in a transistor of a memory array in a
memory device.
8. The method of claim 7, wherein the method includes providing a
bus to couple the memory device to a processor in an electronic
system.
9. A method comprising: forming a dielectric film on a substrate,
the dielectric layer having a nanolaminate containing a layer of
hafnium oxide and a layer of zirconium oxide, the nanolaminate
fabricated by: forming the layer of hafnium oxide by layering one
or more individual monolayers of hafnium oxide; and forming the
layer of zirconium oxide on the layer of hafnium oxide by
pulsed-laser deposition.
10. The method of claim 9, wherein the method includes forming the
layer of hafnium oxide as an initial layer of the nanolaminate and
forming another layer of hafnium oxide as the final layer of the
nanolaminate.
11. The method of claim 9, wherein forming a layer of hafnium oxide
by layering one or more individual monolayers includes forming the
layer of hafnium oxide by atomic layer deposition.
12. The method of claim 9, wherein forming the layer of zirconium
oxide includes forming the layer of zirconium oxide with a
substrate temperature between about 200.degree. C. to about
800.degree. C.
13. The method of claim 9, wherein forming the layer of zirconium
oxide includes forming the layer of zirconium oxide at an O.sub.2
pressure of about 0.2 Torr.
14. The method of claim 9, wherein forming the layer of zirconium
oxide includes ablating a zirconium target with an excimer
laser.
15. The method of claim 9, wherein forming a layer of hafnium oxide
includes pulsing a precursor containing oxygen to the substrate
after pulsing a HfI.sub.4 precursor to the substrate.
16. The method of claim 15, wherein pulsing a precursor containing
oxygen includes pulsing a vapor solution of
H.sub.2O--H.sub.2O.sub.2.
17. A method comprising: forming a dielectric film on a substrate,
the dielectric layer having a nanolaminate containing a layer of
hafnium oxide and a layer of zirconium oxide, the nanolaminate
fabricated by: forming the layer of hafnium oxide by layering one
or more individual monolayers of hafnium oxide; and forming the
layer of zirconium oxide on the layer of hafnium oxide by jet-vapor
deposition.
18. The method of claim 17, wherein forming a layer of hafnium
oxide by layering one or more individual monolayers includes
forming the layer of hafnium oxide by atomic layer deposition.
19. The method of claim 17, wherein the method includes forming the
layer of hafnium oxide as an initial layer of the nanolaminate on
the substrate and forming another layer of hafnium oxide as the
final layer of the nanolaminate.
20. The method of claim 17, wherein forming the layer of zirconium
oxide includes forming the layer of zirconium oxide at room
temperature.
21. The method of claim 17, wherein forming the layer of hafnium
oxide includes forming the layer of hafnium oxide by atomic layer
deposition using a HfI.sub.4 precursor followed by pulsing a
precursor containing oxygen.
22. The method of claim 21, wherein pulsing a precursor containing
oxygen includes pulsing water vapor.
23. The method of claim 17, wherein the method further includes
annealing the dielectric film after forming the layer of zirconium
oxide using nitrogen rapid thermal annealing.
24. A method of forming a transistor comprising: forming first and
second source/drain regions in a substrate; forming a body region
between the first and second source/drain regions; forming a
dielectric film above the body region between the first and second
source/drain regions, the dielectric film having a nanolaminate
containing a layer of hafnium oxide and a layer of zirconium oxide;
and coupling a gate to the dielectric film, wherein forming the
nanolaminate includes: forming the layer of hafnium oxide by
layering one or more individual monolayers of hafnium oxide; and
forming the layer of zirconium oxide on the layer of hafnium oxide,
wherein the layer of zirconium oxide is formed by one or more of
pulsed-laser deposition or jet-vapor deposition.
25. The method of claim 24, wherein the method includes forming the
layer of hafnium oxide as an initial layer of the nanolaminate and
forming another layer of hafnium oxide as the final layer of the
nanolaminate.
26. The method of claim 24, wherein forming a layer of hafnium
oxide by layering one or more individual monolayers includes
forming the layer of hafnium oxide by atomic layer deposition.
27. The method of claim 26, wherein forming the layer of hafnium
oxide by atomic layer deposition includes using a HfI.sub.4
precursor in the atomic layer deposition.
28. The method of claim 24, wherein forming a layer of zirconium
oxide includes forming the layer of zirconium oxide by pulsed-laser
deposition.
29. The method of claim 24, wherein forming a layer of zirconium
oxide includes forming the layer of zirconium oxide by jet-vapor
deposition.
30. The method of claim 24, wherein the method includes forming the
dielectric film as a gate dielectric contacting the body
region.
31. The method of claim 24, wherein the method includes forming the
dielectric film as a floating gate dielectric contacting a floating
gate and contacting a control gate.
32. A method of forming a memory comprising: forming a transistor,
the transistor including a dielectric film containing a hafnium
oxide/zirconium oxide nanolaminate, the dielectric film formed
above a body region between a first source/drain region and a
second source/drain region, the hafnium oxide/zirconium oxide
nanolaminate formed by: forming a layer of hafnium oxide by
layering one or more individual monolayers of hafnium oxide;
forming a layer of zirconium oxide on the layer of hafnium oxide,
the layer of zirconium oxide formed by one or more of pulsed-laser
deposition or jet-vapor deposition; and forming a word line coupled
to a gate of the transistor.
33. The method of claim 32, wherein the method includes forming the
layer of hafnium oxide as an initial layer of the nanolaminate and
forming another layer of hafnium oxide as the final layer of the
nanolaminate.
34. The method of claim 32, wherein forming a layer of hafnium
oxide by layering one or more individual monolayers includes
forming the layer of hafnium oxide by atomic layer deposition.
35. The method of claim 32, wherein forming a layer of hafnium
oxide includes using a H.sub.2O--H.sub.2O.sub.2 gas mixture as an
oxidizing reactant after pulsing a hafnium-containing precursor to
a substrate on which the memory is being structured.
36. The method of claim 32, wherein the method includes forming the
transistor in a memory cell and forming a capacitor in the memory
cell.
37. The method of claim 32, wherein forming a layer of zirconium
oxide includes forming the layer of zirconium oxide by pulsed-laser
deposition.
38. The method of claim 32, wherein forming a layer of zirconium
oxide includes forming the layer of zirconium oxide by jet-vapor
deposition.
39. A method of forming an electronic system comprising: providing
a processor; coupling a memory to the processor, the memory
including a transistor having a dielectric film containing a
hafnium oxide/zirconium oxide nanolaminate, the dielectric film
formed above a body region between a first source/drain region and
a second source/drain region, the hafnium oxide/zirconium oxide
nanolaminate formed by: forming a layer of hafnium oxide by
layering one or more individual monolayers of hafnium oxide;
forming a layer of zirconium oxide on the layer of hafnium oxide,
the layer of zirconium oxide formed by one or more of pulsed-laser
deposition or jet-vapor deposition; and providing a bus to couple
the processor to the memory.
40. The method of claim 39, wherein the method includes forming the
layer of hafnium oxide as an initial layer of the nanolaminate and
forming another layer of hafnium oxide as the final layer of the
nanolaminate.
41. The method of claim 39, wherein forming a layer of hafnium
oxide by layering one or more individual monolayers includes
forming the layer of hafnium oxide by atomic layer deposition.
42. The method of claim 39, wherein forming a layer of zirconium
oxide includes forming the layer of zirconium oxide by pulsed-laser
deposition.
43. The method of claim 39, wherein forming a layer of zirconium
oxide includes forming the layer of zirconium oxide by jet-vapor
deposition.
44. The method of claim 39, wherein the method includes forming an
information handling system.
45. The method of claim 39, wherein the method includes forming a
wireless system.
Description
RELATED APPLICATIONS
[0001] The present application is a Divisional of U.S. application
Ser. No. 11/148,505 filed on Jun. 9, 2005 that is a Divisional of
U.S. application Ser. No. 10/209,581, filed Jul. 30, 2002, now U.S.
Pat. No. 6,921,702, both applications are incorporated herein by
reference.
[0002] This application is related to the following, co-pending,
commonly assigned applications, incorporated herein by
reference:
[0003] U.S. application Ser. No. 10/163,481, entitled: "Atomic
Layer-Deposited HfAlO.sub.3 Films for Gate Dielectrics;"
[0004] U.S. Pat. No. 7,045,430, entitled: "Atomic Layer-Deposited
LaAlO.sub.3 Films for Gate Dielectrics;"
[0005] U.S. application Ser. No. 10/137,058, entitled: "Atomic
Layer Deposition and Conversion;"
[0006] U.S. application Ser. No. 09/945,535, entitled: "Highly
Reliable Amorphous High-K Gate Oxide ZrO.sub.2;"
[0007] U.S. application Ser. No. 10/137,168, entitled: "Methods,
Systems, and Apparatus for Atomic-Layer Deposition of Aluminum
Oxides in Integrated Circuits;" and
[0008] U.S. Pat. No. 6,852,167, entitled: "Methods, Systems, and
Apparatus for Uniform Chemical-Vapor Depositions."
FIELD OF THE INVENTION
[0009] The invention relates to semiconductor devices and device
fabrication. Specifically, the invention relates to gate dielectric
layers of transistor devices and their method of fabrication.
BACKGROUND OF THE INVENTION
[0010] The semiconductor device industry has a market driven need
to improve speed performance, improve its low static (off-state)
power requirements, and adapt to a wide range of power supply and
output voltage requirements for it silicon based microelectronic
products. In particular, in the fabrication of transistors, there
is continuous pressure to reduce the size of devices such as
transistors. The ultimate goal is to fabricate increasingly smaller
and more reliable integrated circuits (ICs) for use in products
such as processor chips, mobile telephones, or memory devices such
as DRAMs. The smaller devices are frequently powered by batteries,
where there is also pressure to reduce the size of the batteries,
and to extend the time between battery charges. This forces the
industry to not only design smaller transistors, but to design them
to operate reliably with lower power supplies.
[0011] Currently, the semiconductor industry relies on the ability
to reduce or scale the dimensions of its basic devices, primarily,
the silicon based metal-oxide-semiconductor field effect transistor
(MOSFET). A common configuration of such a transistor is shown in
FIG. 1. While the following discussion uses FIG. 1 to illustrate a
transistor from the prior art, one skilled in the art will
recognize that the present invention could be incorporated into the
transistor shown in FIG. 1 to form a novel transistor according to
the invention. The transistor 100 is fabricated in a substrate 110
that is typically silicon, but could be fabricated from other
semiconductor materials as well. The transistor 100 has a first
source/drain region 120 and a second source/drain region 130. A
body region 132 is located between the first source/drain region
and the second source/drain region, where the body region 132
defines a channel of the transistor with a channel length 134. A
gate dielectric, or gate oxide 140 is located on the body region
132 with a gate 150 located over the gate dielectric. Although the
gate dielectric can be formed from materials other than oxides, the
gate dielectric is typically an oxide, and is commonly referred to
as a gate oxide. The gate may be fabricated from polycrystalline
silicon (polysilicon), or other conducting materials such as metal
may be used.
[0012] In fabricating transistors to be smaller in size and
reliably operate on lower power supplies, one important design
criteria is the gate dielectric 140. The mainstay for forming the
gate dielectric has been silicon dioxide, SiO.sub.2. A thermally
grown amorphous SiO.sub.2 layer provides an electrically and
thermodynamically stable material, where the interface of the
SiO.sub.2 layer with underlying Si provides a high quality
interface as well as superior electrical isolation properties. In
typical processing, use of SiO.sub.2 on Si has provided defect
charge densities on the order of 10.sup.10/cm.sup.2, midgap
interface state densities of approximately 10.sup.10/cm.sup.2 eV,
and breakdown voltages in the range of 15 MV/cm. With such
qualities, there would be no apparent need to use a material other
than SiO.sub.2, but increased scaling and other requirements for
gate dielectrics create the need to find other dielectric materials
to be used for a gate dielectric.
[0013] What is needed is an alternate dielectric material for
forming a gate dielectric that has a high dielectric constant
relative to SiO.sub.2, and is thermodynamically stable with respect
to silicon such that forming the dielectric on a silicon layer will
not result in SiO.sub.2 formation, or diffusion of material, such
as dopants, into the gate dielectric from the underlying silicon
layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 shows a common configuration of a transistor in which
an embodiment of a gate dielectric can be formed, according to the
teaching of the present invention.
[0015] FIG. 2A shows an embodiment of an atomic layer deposition
system for processing a layer of HfO.sub.2 and a nanolaminate of
HfO.sub.2/ZrO.sub.2, according to the teachings of the present
invention.
[0016] FIG. 2B shows an embodiment of a gas-distribution fixture of
an atomic layer deposition chamber for processing a layer of
HfO.sub.2 and a nanolaminate of HfO.sub.2/ZrO.sub.2, according to
the teachings of the present invention.
[0017] FIG. 3 illustrates a flow diagram of elements for an
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2, according to the teachings of the present
invention.
[0018] FIG. 4 illustrates a flow diagram of elements for another
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2 by atomic layer deposition, according to the
teachings of the present invention.
[0019] FIG. 5 illustrates a flow diagram of elements for an
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2 using atomic layer deposition and thermal
evaporation/plasma oxidation, according to the teachings of the
present invention.
[0020] FIG. 6 shows an embodiment of an electron beam evaporation
process for forming a layer of zirconium on a layer of HfO.sub.2 to
process a nanolaminate of HfO.sub.2/ZrO.sub.2, according to the
teachings of the present invention.
[0021] FIG. 7A shows an embodiment of a zirconium layer deposited
on a layer of HfO.sub.2, according to the teachings of the present
invention.
[0022] FIG. 7B shows an embodiment of a partially oxidized
zirconium layer deposited on a layer of HfO.sub.2, according to the
teachings of the present invention.
[0023] FIG. 7C shows an embodiment of a ZrO.sub.2 substantially
completely oxidized and formed on a layer of HfO.sub.2 to form a
nanolaminate of HfO.sub.2/ZrO.sub.2, according to the teachings of
the present invention.
[0024] FIG. 8 illustrates a flow diagram of elements for an
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2 using atomic layer deposition and chemical
vapor deposition, according to the teachings of the present
invention.
[0025] FIG. 9 illustrates a flow diagram of elements for an
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2 using atomic layer deposition and pulsed-laser
deposition, according to the teachings of the present
invention.
[0026] FIG. 10 illustrates a flow diagram of elements for an
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2 using atomic layer deposition and jet-vapor
deposition, according to the teachings of the present
invention.
[0027] FIG. 11 shows an embodiment of a configuration of a
transistor capable of being fabricated, according to the teachings
of the present invention.
[0028] FIG. 12 shows an embodiment of a personal computer
incorporating devices, according to the teachings of the present
invention.
[0029] FIG. 13 illustrates a schematic view of an embodiment of a
central processing unit incorporating devices, according to the
teachings of the present invention.
[0030] FIG. 14 illustrates a schematic view of an embodiment of a
DRAM memory device, according to the teachings of the present
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0031] In the following detailed description of the invention,
reference is made to the accompanying drawings which form a part
hereof, and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. These
embodiments are described in sufficient detail to enable those
skilled in the art to practice the invention. Other embodiments may
be utilized and structural, logical, and electrical changes may be
made without departing from the scope of the present invention.
[0032] The terms wafer and substrate used in the following
description include any structure having an exposed surface with
which to form the integrated circuit (IC) structure of the
invention. The term substrate is understood to include
semiconductor wafers. The term substrate is also used to refer to
semiconductor structures during processing, and may include other
layers that have been fabricated thereupon. Both wafer and
substrate include doped and undoped semiconductors, epitaxial
semiconductor layers supported by a base semiconductor or
insulator, as well as other semiconductor structures well known to
one skilled in the art. The term conductor is understood to include
semiconductors, and the term insulator or dielectric is defined to
include any material that is less electrically conductive than the
materials referred to as conductors.
[0033] The term "horizontal" as used in this application is defined
as a plane parallel to the conventional plane or surface of a wafer
or substrate, regardless of the orientation of the wafer or
substrate. The term "vertical" refers to a direction perpendicular
to the horizontal as defined above. Prepositions, such as "on",
"side" (as in "sidewall"), "higher", "lower", "over" and "under"
are defined with respect to the conventional plane or surface being
on the top surface of the wafer or substrate, regardless of the
orientation of the wafer or substrate. The following detailed
description is, therefore, not to be taken in a limiting sense, and
the scope of the present invention is defined only by the appended
claims, along with the full scope of equivalents to which such
claims are entitled.
[0034] A gate dielectric 140 of FIG. 1, when operating in a
transistor, has both a physical gate dielectric thickness and an
equivalent oxide thickness (t.sub.eq). The equivalent oxide
thickness quantifies the electrical properties, such as
capacitance, of a gate dielectric 140 in terms of a representative
physical thickness. t.sub.eq is defined as the thickness of a
theoretical SiO.sub.2 layer that would be required to have the same
capacitance density as a given dielectric, ignoring leakage current
and reliability considerations.
[0035] A SiO.sub.2 layer of thickness, t, deposited on a Si surface
as a gate dielectric will have a t.sub.eq larger than its
thickness, t. This t.sub.eq results from the capacitance in the
surface channel on which the SiO.sub.2 is deposited due to the
formation of a depletion/inversion region. This depletion/inversion
region can result in t.sub.eq being from 3 to 6 Angstroms (.ANG.)
larger than the SiO.sub.2 thickness, t. Thus, with the
semiconductor industry driving to someday scale the gate dielectric
equivalent oxide thickness to under 10 .ANG., the physical
thickness requirement for a SiO.sub.2 layer used for a gate
dielectric would be need to be approximately 4 to 7 .ANG..
[0036] Additional requirements on a SiO.sub.2 layer would depend on
the gate electrode used in conjunction with the SiO.sub.2 gate
dielectric. Using a conventional polysilicon gate would result in
an additional increase in t.sub.eq for the SiO.sub.2 layer. This
additional thickness could be eliminated by using a metal gate
electrode, though metal gates are not currently used in
complementary metal-oxide-semiconductor field effect transistor
(CMOS) technology. Thus, future devices would be designed towards a
physical SiO.sub.2 gate dielectric layer of about 5 .ANG. or less.
Such a small thickness requirement for a SiO.sub.2 oxide layer
creates additional problems.
[0037] Silicon dioxide is used as a gate dielectric, in part, due
to its electrical isolation properties in a SiO.sub.2--Si based
structure. This electrical isolation is due to the relatively large
band gap of SiO.sub.2 (8.9 eV) making it a good insulator from
electrical conduction. Signification reductions in its band gap
would eliminate it as a material for a gate dielectric. As the
thickness of a SiO.sub.2 layer decreases, the number of atomic
layers, or monolayers of the material in the thickness decreases.
At a certain thickness, the number of monolayers will be
sufficiently small that the SiO.sub.2 layer will not have a
complete arrangement of atoms as in a larger or bulk layer. As a
result of incomplete formation relative to a bulk structure, a thin
SiO.sub.2 layer of only one or two monolayers will not form a full
band gap. The lack of a full band gap in a SiO.sub.2 gate
dielectric would cause an effective short between an underlying Si
channel and an overlying polysilicon gate. This undesirable
property sets a limit on the physical thickness to which a
SiO.sub.2 layer can be scaled. The minimum thickness due to this
monolayer effect is thought to be about 7-8 .ANG.. Therefore, for
future devices to have a t.sub.eq less than about 10 .ANG., other
dielectrics than SiO.sub.2 need to be considered for use as a gate
dielectric.
[0038] For a typical dielectric layer used as a gate dielectric,
the capacitance is determined as one for a parallel plate
capacitance: C=.sub..kappa..di-elect cons..sub.0A/t, where .kappa.
is the dielectric constant, .di-elect cons..sub.0 is the
permittivity of free space, A is the area of the capacitor, and t
is the thickness of the dielectric. The thickness, t, of a material
is related to t.sub.eq for a given capacitance with the dielectric
constant of SiO.sub.2, .kappa..sub.ox=3.9, associated with
t.sub.eq, as
t=(.kappa./.kappa..sub.ox)t.sub.eq=(.kappa./3.9)t.sub.eq. Thus,
materials with a dielectric constant greater than that of
SiO.sub.2, 3.9, will have a physical thickness that can be
considerably larger than a desired t.sub.eq, while providing the
desired equivalent oxide thickness. For example, an alternate
dielectric material with a dielectric constant of 10 could have a
thickness of about 25.6 .ANG. to provide a t.sub.eq of 10 .ANG.,
not including any depletion/inversion layer effects. Thus, the
reduced equivalent oxide thickness of transistors can be realized
by using dielectric materials with higher dielectric constants than
SiO.sub.2.
[0039] The thinner equivalent oxide thickness required for lower
transistor operating voltages and smaller transistor dimensions may
be realized by a significant number of materials, but additional
fabricating requirements makes determining a suitable replacement
for SiO.sub.2 difficult. The current view for the microelectronics
industry is still for Si based devices. This requires that the gate
dielectric employed be grown on a silicon substrate or silicon
layer, which places significant restraints on the substitute
dielectric material. During the formation of the dielectric on the
silicon layer, there exists the possibility that a small layer of
SiO.sub.2 could be formed in addition to the desired dielectric.
The result would effectively be a dielectric layer consisting of
two sublayers in parallel with each other and the silicon layer on
which the dielectric is formed. In such a case, the resulting
capacitance would be that of two dielectrics in series. As a
result, the t.sub.eq of the dielectric layer would be the sum of
the SiO.sub.2 thickness and a multiplicative factor of the
thickness of the dielectric being formed, written as
t.sub.eq=t.sub.SiO.sub.2+(.kappa..sub.ox/.kappa.)t. Thus, if a
SiO.sub.2 layer is formed in the process, the t.sub.eq is again
limited by a SiO.sub.2 layer. In the event that a barrier layer is
formed between the silicon layer and the desired dielectric in
which the barrier layer prevents the formation of a SiO.sub.2
layer, the t.sub.eq would be limited by the layer with the lowest
dielectric constant. However, whether a single dielectric layer
with a high dielectric constant or a barrier layer with a higher
dielectric constant than SiO.sub.2 is employed, the layer
interfacing with the silicon layer must provide a high quality
interface to maintain a high channel carrier mobility.
[0040] In a recent article by G. D. Wilk et al., Journal of Applied
Physics, vol. 89: no. 10, pp. 5243-5275 (2001), material properties
of high dielectric materials for gate dielectrics were discussed.
Among the information disclosed was the viability of
Al.sub.2O.sub.3 as a substitute for SiO.sub.2. Al.sub.2O.sub.3 was
disclosed has having favourable properties for use as a gate
dielectric such as high band gap, thermodynamic stability on Si up
to high temperatures, and an amorphous structure. In addition, Wilk
disclosed that forming a layer of Al.sub.2O.sub.3 on silicon does
not result in a SiO.sub.2 interfacial layer. However, the
dielectric constant of Al.sub.2O.sub.3 is only 9, where thin layers
may have a dielectric constant of about 8 to about 10. Though the
dielectric constant of Al.sub.2O.sub.3 is in an improvement over
SiO.sub.2, a higher dielectric constant for a gate dielectric is
desirable. Other dielectrics and their properties discussed by Wilk
include TABLE-US-00001 Dielectric Band gap Material Constant
(.kappa.) E.sub.g (eV) Crystal Structure(s) SiO.sub.2 3.9 8.9
Amorphous Si.sub.3N.sub.4 7 5.1 Amorphous Al.sub.2O.sub.3 9 8.7
Amorphous Y.sub.2O.sub.3 15 5.6 Cubic La.sub.2O.sub.3 30 4.3
Hexagonal, Cubic Ta.sub.2O.sub.5 26 4.5 Orthorhombic TiO.sub.2 80
3.5 Tetrag. (rutile, anatase) HfO.sub.2 25 5.7 Mono., Tetrag.,
Cubic ZrO.sub.2 25 7.8 Mono., Tetrag., Cubic
[0041] One of the advantages using SiO.sub.2 as a gate dielectric
has been that the formation of the SiO.sub.2 layer results in an
amorphous gate dielectric. Having an amorphous structure for a gate
dielectric is advantageous because grain boundaries in
polycrystalline gate dielectrics provide high leakage paths.
Additionally, grain size and orientation changes throughout a
polycrystalline gate dielectric can cause variations in the film's
dielectric constant. The abovementioned material properties
including crystal structure are for the materials in a bulk form.
The materials having the advantage of a high dielectric constants
relative to SiO.sub.2 also have the disadvantage of a crystalline
form, at least in a bulk configuration. The best candidates for
replacing SiO.sub.2 as a gate dielectric are those with high
dielectric constant, which can be fabricated as a thin layer with
an amorphous form.
[0042] In one embodiment, a method of forming a gate dielectric on
a transistor body region includes the formation of
HfO.sub.2/ZrO.sub.2 nanolaminates by atomic layer deposition (ALD)
of HfO.sub.2 using a HfI.sub.4 precursor followed by the formation
of ZrO.sub.2 on the HfO.sub.2 layer. Various embodiments include
forming the ZrO.sub.2 layer by thermal evaporation followed by
krypton/oxygen mixed plasma oxidation, pulsed-laser deposition, or
jet-vapor deposition.
[0043] A gate dielectric formed as nanolaminates of
HfO.sub.2/ZrO.sub.2 has a larger dielectric constant than silicon
dioxide, a relatively small leakage current, and good stability
with respect to a silicon based substrate. Embodiments according to
the teachings of the present invention include forming transistors,
memory devices, and electronic systems having dielectric layers
containing nanolaminates of HfO.sub.2/ZrO.sub.2.
[0044] Other embodiments include structures for transistors, memory
devices, and electronic systems with gate dielectrics containing
nanolaminates of HfO.sub.2/ZrO.sub.2 Such gate dielectrics provide
a significantly thinner equivalent oxide thickness compared with a
silicon oxide gate having the same physical thickness.
Alternatively, such gate dielectrics provide a significantly
thicker physical thickness than a silicon oxide gate dielectric
having the same equivalent oxide thickness.
[0045] In an embodiment according to the teachings of the present
invention, a gate dielectric includes thin layers of HfO.sub.2 and
ZrO.sub.2 forming a nanolaminate. The term "nanolaminate" means a
composite film of ultra thin layers of two or more materials in a
layered stack, where the layers are alternating layers of materials
of the composite film. Typically, nanolaminates have thicknesses of
an order of magnitude in the nanometer range. Each individual
material layer of the nanolaminate can have thicknesses as low as a
monolayer of the material. A nanolaminate of HfO.sub.2 and
ZrO.sub.2 includes at least one thin layer of HfO.sub.2, and one
thin layer of ZrO.sub.2, and is typically written as a nanolaminate
of HfO.sub.2/ZrO.sub.2. In one embodiment, nanolaminates of
HfO.sub.2/ZrO.sub.2 are grown using atomic layer deposition (ALD),
also known as atomic layer epitaxy (ALE).
[0046] ALD was developed in the early 1970's as a modification of
chemical vapor deposition (CVD) and is also called "alternatively
pulsed-CVD." In ALD, gaseous precursors are introduced one at a
time to the substrate surface mounted within a reaction chamber (or
reactor). This introduction of the gaseous precursors takes the
form of pulses of each gaseous precursor. Between the pulses, the
reaction chamber is purged with a gas, which in many cases is an
inert gas, or evacuated.
[0047] In a chemisorption-saturated ALD (CS-ALD) process, during
the first pulsing phase, reaction with the substrate occurs with
the precursor saturatively chemisorbed at the substrate surface.
Subsequent pulsing with a purging gas removes precursor excess from
the reaction chamber.
[0048] The second pulsing phase introduces another precursor on the
substrate where the growth reaction of the desired film takes
place. Subsequent to the film growth reaction, reaction byproducts
and precursor excess are purged from the reaction chamber. With
favourable precursor chemistry where the precursors adsorb and
react with each other on the substrate aggressively, one ALD cycle
can be preformed in less than one second in properly designed flow
type reaction chambers. Typically, precursor pulse times range from
about 0.5 sec to about 2 to 3 seconds.
[0049] In ALD, the saturation of all the reaction and purging
phases makes the growth self-limiting. This self-limiting growth
results in large area uniformity and conformality, which has
important applications for such cases as planar substrates, deep
trenches, and in the processing of porous silicon and high surface
area silica and alumina powders. Significantly, ALD provides for
controlling film thickness in a straightforward, simple manner by
controlling the number of growth cycles.
[0050] ALD was originally developed to manufacture luminescent and
dielectric films needed in electroluminescent displays. Significant
efforts have been made to apply ALD to the growth of doped zinc
sulfide and alkaline earth metal sulfide films. Additionally, ALD
has been studied for the growth of different epitaxial II-V and
II-VI films, nonepitaxial crystalline or amorphous oxide and
nitride films and multilayer structures of these. There also has
been considerable interest towards the ALD growth of silicon and
germanium films, but due to the difficult precursor chemistry, this
has not been very successful.
[0051] The precursors used in an ALD process may be gaseous, liquid
or solid. However, liquid or solid precursors must be volatile. The
vapor pressure must be high enough for effective mass
transportation. Also, solid and some liquid precursors need to be
heated inside the reaction chamber and introduced through heated
tubes to the substrates. The necessary vapor pressure must be
reached at a temperature below the substrate temperature to avoid
the condensation of the precursors on the substrate. Due to the
self-limiting growth mechanisms of ALD, relatively low vapor
pressure solid precursors can be used though evaporation rates may
somewhat vary during the process because of changes in their
surface area.
[0052] There are several other requirements for precursors used in
ALD. The precursors must be thermally stable at the substrate
temperature because their decomposition would destroy the surface
control and accordingly the advantages of the ALD method which
relies on the reactant of the precursor at the substrate surface.
Of course, a slight decomposition, if slow compared to the ALD
growth, can be tolerated.
[0053] The precursors have to chemisorb on or react with the
surface, though the interaction between the precursor and the
surface as well as the mechanism for the adsorption is different
for different precursors. The molecules at the substrate surface
must react aggressively with the second precursor to form the
desired solid film. Additionally, precursors should not react with
the film to cause etching, and precursors should not dissolve in
the film. Using highly reactive precursors in ALD contrasts with
the selection of precursors for conventional CVD.
[0054] The by-products in the reaction must be gaseous in order to
allow their easy removal from the reaction chamber. Further, the
by-products should not react or adsorb on the surface.
[0055] In a reaction sequence ALD (RS-ALD) process, the
self-limiting process sequence involves sequential surface chemical
reactions. RS-ALD relies on chemistry between a reactive surface
and a reactive molecular precursor. In an RS-ALD process, molecular
precursors are pulsed into the ALD reaction chamber separately. The
metal precursor reaction at the substrate is typically followed by
an inert gas pulse to remove excess precursor and by-products from
the reaction chamber prior to pulsing the next precursor of the
fabrication sequence.
[0056] By RS-ALD, films can be layered in equal metered sequences
that are all identical in chemical kinetics, deposition per cycle,
composition, and thickness. RS-ALD sequences generally deposit less
than a full layer per cycle. Typically, a deposition or growth rate
of about 0.25 to about 2.00 .ANG. per RS-ALD cycle can be
realized.
[0057] The advantages of RS-ALD include continuity at an interface,
conformality over a substrate, use of low temperature and mildly
oxidizing processes, growth thickness dependent solely on the
number of cycles performed, and ability to engineer multilayer
laminate films with resolution of one to two monolayers. RS-ALD
allows for deposition control on the order on monolayers and the
ability to deposit monolayers of amorphous films.
[0058] RS-ALD processes provide for the formation of nanolaminates.
These nanolaminates can be engineered in various forms. In one
form, the transition between material layers of the nanolaminate
can be made abrupt. In another form, the transition between
material layers of the nanolaminate can be constructed with a
graded composition. The graded composition can be formed by RS-ALD
due its control of the deposition thickness per cycle.
[0059] In an embodiment, a layer of HfO.sub.2 is formed on a
substrate mounted in a reaction chamber using ALD in a repetitive
sequence including pulsing a hafnium containing precursor into the
reaction chamber followed by pulsing a purging gas, and then
pulsing a first oxygen containing precursor into the chamber. In
one embodiment using ALD, a layer of HfO.sub.2 is formed using
HfI.sub.4 as a hafnium containing precursor, water vapor as a first
oxygen containing precursor, and nitrogen as a purging gas and
carrier gas. After forming a HfO.sub.2 layer, a ZrO.sub.2 layer is
formed on the HfO.sub.2 layer.
[0060] In one embodiment, the layer of ZrO.sub.2 is formed by ALD.
In particular, a repetitive sequence includes using ZrI.sub.4 as a
zirconium containing precursor along with a vapor solution of
HO.sub.2--H.sub.2O.sub.2 as a second oxygen containing precursor,
and nitrogen as a purging gas and carrier gas. In another
embodiment, the ZrO.sub.2 layer is formed by depositing a layer of
zirconium on the HfO.sub.2 layer by thermal evaporation, and
oxidizing the zirconium layer using a krypton(Kr)/oxygen(O.sub.2)
mixed plasma to form a HfO.sub.2/ZrO.sub.2 composite layer. In
another embodiment, the ZrO.sub.2 layer is formed by pulsed-laser
deposition. In yet another embodiment, the ZrO.sub.2 layer is
formed by jet-vapor deposition.
[0061] In one embodiment, precursor gases, in particular HfI.sub.4,
are used to form the HfO.sub.2 layer for the HfO.sub.2/ZrO.sub.2
nanolaminate films used as a gate dielectric on a transistor body.
Alternately, solid or liquid precursors can be used in an
appropriately designed reaction chamber. ALD formation of other
materials is disclosed in co-pending, commonly assigned U.S. patent
application: entitled "Atomic Layer Deposition and Conversion,"
attorney docket no. 303.802US1, Ser. No. 10/137,058, and "Methods,
Systems, and Apparatus for Atomic-Layer Deposition of Aluminum
Oxides in Integrated Circuits," attorney docket no. 1303.048US1,
Ser. No. 10/137,168.
[0062] FIG. 2A shows an embodiment of an atomic layer deposition
system for processing layers of HfO.sub.2 and nanolaminates of
HfO.sub.2/ZrO.sub.2 according to the teachings of the present
invention. The elements depicted are those elements necessary for
discussion of the present invention such that those skilled in the
art may practice the present invention without undue
experimentation. A further discussion of the ALD reaction chamber
can be found in co-pending, commonly assigned U.S. patent
application: entitled "Methods, Systems, and Apparatus for Uniform
Chemical-Vapor Depositions," attorney docket no. 303.717US1, Ser.
No. 09/797,324, incorporated herein by reference.
[0063] In FIG. 2A, a substrate 210 is located inside a reaction
chamber 220 of ALD system 200. Also located within the reaction
chamber 220 is a heating element 230 which is thermally coupled to
substrate 210 to control the substrate temperature. A
gas-distribution fixture 240 introduces precursor gases to the
substrate 210. Each precursor gas originates from individual gas
sources 251-254 whose flow is controlled by mass-flow controllers
256-259, respectively. The gas sources 251-254 provide a precursor
gas either by storing the precursor as a gas or by providing a
location and apparatus for evaporating a solid or liquid material
to form the selected precursor gas.
[0064] Also included in the ALD system are purging gas sources 261,
262, each of which is coupled to mass-flow controllers 266, 267,
respectively. The gas sources 251-254 and the purging gas sources
261-262 are coupled by their associated mass-flow controllers to a
common gas line or conduit 270 which is coupled to the
gas-distribution fixture 240 inside the reaction chamber 220. Gas
conduit 270 is also coupled to vacuum pump, or exhaust pump, 281 by
mass-flow controller 286 to remove excess precursor gases, purging
gases, and by-product gases at the end of a purging sequence from
the gas conduit.
[0065] Vacuum pump, or exhaust pump, 282 is coupled by mass-flow
controller 287 to remove excess precursor gases, purging gases, and
by-product gases at the end of a purging sequence from the reaction
chamber 220. For convenience, control displays, mounting apparatus,
temperature sensing devices, substrate maneuvering apparatus, and
necessary electrical connections as are known to those skilled in
the art are not shown in FIG. 2A.
[0066] FIG. 2B shows an embodiment of a gas-distribution fixture of
an atomic layer deposition chamber for processing layers of
HfO.sub.2 and nanolaminates of HfO.sub.2/ZrO.sub.2, according to
the teachings of the present invention. Gas-distribution fixture
240 includes a gas-distribution member 242, and a gas inlet 244.
Gas inlet 244 couples the gas-distribution member 242 to the gas
conduit 270 of FIG. 2A. Gas-distribution member 242 includes
gas-distribution holes, or orifices, 246 and gas-distribution
channels 248. In the exemplary embodiment, holes 246 are
substantially circular with a common diameter in the range of 15-20
microns, gas-distribution channels 248 have a common width in the
range of 20-45 microns. The surface 249 of the gas distribution
member having gas-distribution holes 246 is substantially planar
and parallel to the substrate 210 of FIG. 2A. However, other
embodiments use other surface forms as well as shapes and sizes of
holes and channels. The distribution and size of holes may also
affect deposition thickness and thus might be used to assist
thickness control. Holes 246 are coupled through gas-distribution
channels 248 to gas inlet 244. Though the ALD system 200 is well
suited for practicing the present invention, other ALD systems
commercially available can be used.
[0067] The use, construction and fundamental operation of reaction
chambers for deposition of films are understood by those of
ordinary skill in the art of semiconductor fabrication. The present
invention man be practiced on a variety of such reaction chambers
without undue experimentation. Furthermore, one of ordinary skill
in the art will comprehend the necessary detection, measurement,
and control techniques in the art of semiconductor fabrication upon
reading the disclosure.
[0068] FIG. 3 illustrates a flow diagram of elements for an
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2, according to the teachings of the present
invention. This embodiment of a method for forming a
HfO.sub.2/ZrO.sub.2 nanolaminate includes forming a layer of
hafnium oxide on a substrate in a reaction chamber by atomic layer
deposition using a HfI.sub.4 precursor, at block 305, and forming a
layer of zirconium oxide on the layer of hafnium oxide to form a
HfO.sub.2/ZrO.sub.2 composite, at block 310. By strictly
controlling the processing of the HfO.sub.2 layer and the ZrO.sub.2
layer, the HfO.sub.2/ZrO.sub.2 composite formed is a
HfO.sub.2/ZrO.sub.2 nanolaminate. In one embodiment, the
HfO.sub.2/ZrO.sub.2 nanolaminate is composed of one HfO.sub.2 layer
and one layer ZrO.sub.2 layer. In another embodiment, the
HfO.sub.2/ZrO.sub.2 nanolaminate includes multiple layers of the
HfO.sub.2/ZrO.sub.2 composite, where the initial layer disposed on
a substrate is a HfO.sub.2 layer. After this initial HfO.sub.2
layer, there are alternating layers of HfO.sub.2 and ZrO.sub.2,
with the terminating layer being a ZrO.sub.2 layer in one
embodiment and HfO.sub.2 layer in another embodiment.
[0069] Forming the HfO.sub.2 layer on a substrate by atomic layer
deposition involves using a deposition sequence including pulsing
the HfI.sub.4 precursor into the reaction chamber, followed by
pulsing a purging gas, pulsing a first oxygen containing precursor,
and pulsing the purging gas. In one embodiment, the first oxygen
precursor is water vapor. Each precursor is pulsed for a short time
ranging from 0.5 seconds to two or three seconds. A purging gas
such as nitrogen is pulsed for a longer period such as five to
fifteen seconds to insure that all excess precursor gases and
by-products are removed from the reaction chamber. Pulsing times
are selected to enable the controlled growth of the HfO.sub.2 layer
on a one to two monolayer basis. For a fixed ALD sequence or cycle,
including fixed pulsing times and substrate temperatures, the
HfO.sub.2 layer growth rate is at a relatively fixed rate, where a
desired thickness of the HfO.sub.2 layer is obtained by performing
the ALD sequence for a predetermined number of cycles.
[0070] FIG. 4 illustrates a flow diagram of elements for another
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2 by atomic layer deposition, according to the
teachings of the present invention. In this embodiment, a method
for forming a dielectric film includes forming a layer of HfO.sub.2
on a substrate in a reaction chamber by atomic layer deposition
using a HfI.sub.4 precursor, and forming a layer of ZrO.sub.2 on
the HfO.sub.2 layer by atomic layer deposition to form a
HfO.sub.2/ZrO.sub.2 composite. Using the ALD process provides for
the formation of the HfO.sub.2/ZrO.sub.2 composite as a
nanolaminate. An embodiment of this method can be implemented with
the atomic layer deposition system of FIGS. 2A, B.
[0071] At block 405, a substrate is prepared. The substrate used
for forming a transistor is typically a silicon or silicon
containing material. In other embodiments, germanium, gallium
arsenide, silicon-on-sapphire substrates, or other suitable
substrates may be used. This preparation process includes cleaning
of the substrate 210 and forming layers and regions of the
substrate, such as drains and sources of a metal oxide
semiconductor (MOS) transistor, prior to forming a gate dielectric.
The sequencing of the formation of the regions of the transistor
being processed follows typical sequencing that is generally
performed in the fabrication of a MOS transistor as is well known
to those skilled in the art. Included in the processing prior to
forming a gate dielectric is the masking of substrate regions to be
protected during the gate dielectric formation, as is typically
performed in MOS fabrication. In this embodiment, the unmasked
region includes a body region of a transistor, however one skilled
in the art will recognize that other semiconductor device
structures may utilize this process. Additionally, the substrate
210 in its ready for processing form is conveyed into a position in
reaction chamber 220 for ALD processing.
[0072] At block 410, a precursor containing hafnium is pulsed into
reaction chamber 220. In particular, HfI.sub.4 is used as a source
material. The HfI.sub.4 is pulsed into reaction chamber 220 through
the gas-distribution fixture 240 onto substrate 210. The flow of
the HfI.sub.4 is controlled by mass-flow controller 256 from gas
source 251. In one embodiment, the substrate temperature is
maintained between about 225.degree. C. and about 500.degree. C. In
another embodiment, the substrate temperature is maintained between
about 250.degree. C. and about 325.degree. C. The lower temperature
allows for forming a dielectric film suited for use as a gate
dielectric, since an amorphous layer tends to more readily form at
lower processing temperatures. The HfI.sub.4 reacts with the
surface of the substrate 210 in the desired region defined by the
unmasked areas of the substrate 210.
[0073] At block 415, a first purging gas is pulsed into the
reaction chamber 220. In particular, pure nitrogen with a purity
greater than 99.99% is used as a purging gas for HfI.sub.4. The
nitrogen flow is controlled by mass-flow controller 266 from the
purging gas source 261 into the gas conduit 270. Using the pure
nitrogen purge avoids overlap of the precursor pulses and possible
gas phase reactions. A nitrogen gas can also be used as a carrier
gas for the precursors. Following the purge, a first oxygen
containing precursor is pulsed into the reaction chamber 220, at
block 420. For the hafnium sequence using HfI.sub.4 as the
precursor, water vapor is selected as the precursor acting as an
oxidizing reactant to form a HfO.sub.2 on the substrate 210.
Alternately, a vapor solution of H.sub.2O--H.sub.2O.sub.2 can be
used as the oxygen containing precursor. The water vapor is pulsed
into the reaction chamber 220 through gas conduit 270 from gas
source 252 by mass-flow controller 257. The water vapor
aggressively reacts at the surface of substrate 210.
[0074] Following the pulsing of oxidizing reactant water vapor, the
first purging gas is injected into the reaction chamber 220, at
block 425. In the HfI.sub.4/water vapor sequence, pure nitrogen gas
is used to purge the reaction chamber after pulsing each precursor
gas. Excess precursor gas, and reaction by-products are removed
from the system by the purge gas in conjunction with the exhausting
of the reaction chamber 220 using vacuum pump 282 through mass-flow
controller 287, and exhausting of the gas conduit 270 by the vacuum
pump 281 through mass-flow controller 286.
[0075] During the HfI.sub.4/water vapor sequence, the substrate is
held between about 250.degree. C. and about 325.degree. C. by the
heating element 230. In other embodiments the substrate is held
between about 225.degree. C. and 500.degree. C. The HfI.sub.4 pulse
time ranges from about 1.0 sec to about 2.0 sec. After the
HfI.sub.4 pulse, the hafnium sequence continues with a purge pulse
followed by a water vapor pulse followed by a purge pulse. In one
embodiment, performing a purge pulse followed by a water vapor
pulse followed by a purge pulse takes about 2 seconds. In another
embodiment, each pulse in the hafnium sequence has a 2 second pulse
period. In another embodiment, the pulse periods for the precursors
are 2 seconds, while the purge gas pulse period ranges from five
second to twenty seconds.
[0076] At block 430, a determination is made as to whether a
desired thickness of the HfO.sub.2 layer has been formed. The
thickness of a HfO.sub.2 film after one cycle is determined by a
fixed growth rate for the pulsing periods and precursors used in
the hafnium sequence, set at a value such as N nm/cycle. For a
desired HfO.sub.2 film thickness, t, in an application such as
forming a gate dielectric of a MOS transistor, the ALD process
should be repeated for t/N cycles. The desired thickness should be
attained after t/N cycles. If less than t/N cycles have been
completed, the process starts over at block 410 with the pulsing of
the precursor containing hafnium, which in the embodiment discussed
above is a HfI.sub.4 gas. If t/N cycles have completed, no further
ALD processing of HfO.sub.2 is required and the HfO.sub.2 layer is
ready to be formed as a composite with a ZrO.sub.2 layer.
[0077] At block 435, a precursor containing zirconium is pulsed
into the reaction chamber 220. In one embodiment, ZrI.sub.4 is used
as the zirconium containing precursor. In another embodiment,
ZrCl.sub.4 is used as the zirconium containing precursor. The
ZrI.sub.4 is evaporated from a containment area held at about
250.degree. C. in gas source 253. It is pulsed to the surface of
the substrate 210 through gas-distribution fixture 240 from gas
source 253 by mass-flow controller 258. The ZrI.sub.4 is introduced
onto the HfO.sub.2 layer that was formed during the HfI.sub.4/water
vapor sequence.
[0078] At block 440, a second purging gas is introduced into the
system. For a ZrI.sub.4 precursor, nitrogen gas is used as a
purging and carrier gas. The nitrogen flow is controlled by
mass-flow controller 267 from the purging gas source 262 into the
gas conduit 270 and subsequently into the reaction chamber 220.
Following the nitrogen purge, at block 445, a second oxygen
containing precursor is pulsed into the reaction chamber 220. For
the zirconium sequence using ZrI.sub.4 as the precursor, a vapor
solution of H.sub.2O--H.sub.2O.sub.2 is selected as the precursor
acting as an oxidizing reactant to interact with the zirconium
deposited on the HfO.sub.2 layer on the substrate 210. The
H.sub.2O--H.sub.2O.sub.2 vapor solution is pulsed into the reaction
chamber 220 through gas conduit 270 from gas source 254, held at
about room temperature, by mass-flow controller 259. The
H.sub.2O--H.sub.2O.sub.2 vapor solution aggressively reacts at the
surface of substrate 210 to form a ZrO.sub.2 layer.
[0079] Following the pulsing of the H.sub.2O--H.sub.2O.sub.2 vapor
solution acting as an oxidizing reactant, the nitrogen purging gas
is injected into the reaction chamber 200, at block 450. In the
ZrI.sub.4/H.sub.2O--H.sub.2O.sub.2 vapor solution sequence,
nitrogen gas is used to purge the reaction chamber after pulsing
each precursor gas. In another embodiment, argon gas is used as the
purging gas. Excess precursor gas, and reaction by-products are
removed from the system by the purge gas in conjunction with the
exhausting of the reaction chamber 220 using vacuum pump 282
through mass-flow controller 287, and exhausting of the gas conduit
270 by the vacuum pump 281 through mass-flow controller 286.
[0080] During the ZrI.sub.4/H.sub.2O--H.sub.2O.sub.2 vapor solution
sequence, the substrate is held between about 250.degree. C. and
about 325.degree. C. by the heating element 230. In other
embodiments, the substrate is held between about 275.degree. C. and
about 500.degree. C. In one embodiment, the process pressure is
maintained at about 250 Pa during the zirconium sequence. Pulse
times for the ZrI.sub.4 and the H.sub.2O--H.sub.2O.sub.2 vapor
solution were about 2 sec for both precursors, with purging pulse
times of about 2 secs.
[0081] At 455, similar to the HfO.sub.2 layer formation, a
determination is made as to whether the ZrO.sub.2 layer has the
desired thickness by determining if a desired number of zirconium
cycles have been performed. If the number of zirconium cycles
performed is less than the number needed to form the desired
thickness, the zirconium containing precursor is pulsed into the
reaction chamber, at block 435, and the process continues. If the
desired number of zirconium cycles has been performed, this
completes not only the ZrI.sub.4/H.sub.2O--H.sub.2O.sub.2 vapor
solution sequence, but it also completes a hafnium
sequence/zirconium sequence cycle forming a HfO.sub.2/ZrO.sub.2
nanolaminate.
[0082] Upon completing the formation of the HfO.sub.2/ZrO.sub.2
nanolaminate, the nanolaminate can be annealed. The annealing can
be performed at a temperature between about 300.degree. C. and
about 800.degree. C. in an inert or nitrogen atmosphere.
[0083] At block 460, after forming the HfO.sub.2/ZrO.sub.2
nanolaminate, processing the device containing the
HfO.sub.2/ZrO.sub.2 nanolaminate is completed. In one embodiment,
completing the device includes completing the formation of a
transistor. Alternately, completing the process includes completing
the construction of a memory device having a array with access
transistors formed with gate dielectrics containing
HfO.sub.2/ZrO.sub.2 nanolaminates. Further, in another embodiment,
completing the process includes the formation of an electronic
system including an information handling device that uses
electronic devices with transistors formed with gate dielectrics
containing HfO.sub.2/ZrO.sub.2 nanolaminates. Typically,
information handling devices such as computers include many memory
devices, having many access transistors.
[0084] In one embodiment, a HfO.sub.2/ZrO.sub.2 nanolaminate
includes one HfO.sub.2 layer and one HfO.sub.2/ZrO.sub.2 layer. The
completed HfO.sub.2/ZrO.sub.2 nanolaminate has a thickness in which
the thickness of the HfO.sub.2 layer is about one-half the
thickness of the completed HfO.sub.2/ZrO.sub.2 nanolaminate. In
another embodiment, a completed HfO.sub.2/ZrO.sub.2 nanolaminate
includes multiple alternating layers of HfO.sub.2 and ZrO.sub.2,
which requires that at block 455, once a given ZrO.sub.2 layer has
been formed with a desired thickness, a hafnium sequence is then
started at block 410. This process, proceeding from completing the
zirconium sequence at block 455 to starting the hafnium sequence at
block 410, continues until the desired number of alternating layers
of HfO.sub.2 and ZrO.sub.2 have been formed. The
HfO.sub.2/ZrO.sub.2 nanolaminate formation begins with forming a
HfO.sub.2 layer, but may end with forming ZrO.sub.2 layer or a
HfO.sub.2 layer. ALD provides for the engineering of a
HfO.sub.2/ZrO.sub.2 nanolaminate. For example, nanolaminates can be
formed with n number of HfO.sub.2/ZrO.sub.2 composite layers where
the HfO.sub.2 layer is formed with x number of hafnium cycles and y
number of zirconium cycles. Alternately, nanolaminates can be
formed with n number of HfO.sub.2/ZrO.sub.2 composite layers where
the first composite layer has a HfO.sub.2 layer formed with x.sub.1
number of hafnium cycles and y.sub.1 number of zirconium cycles, a
second composite layer has a HfO.sub.2 layer formed with x.sub.2
number of hafnium cycles and y.sub.2 number of zirconium cycles,
extended to the n.sup.th composite layer having a HfO.sub.2 layer
formed with x.sub.n number of hafnium cycles and y.sub.n number of
zirconium cycles. Such tailoring of the HfO.sub.2/ZrO.sub.2
nanolaminate provides for forming dielectric films with a designed
physical thickness, t, and equivalent oxide thickness,
t.sub.eq.
[0085] In the hafnium sequence and in the zirconium sequence,
pulsing each precursor into the reaction chamber is controlled for
a predetermined period, the predetermined period being individually
controlled for each precursor pulsed into the reaction chamber.
Additionally, the substrate is maintained at a selected temperature
for forming each layer, where the selected temperature set
independently for forming each layer.
[0086] In a recent article by O. Sneh et al., Thin Solid Films,
vol. 402, pp. 248-261 (2002), atomic layer deposition of thin films
was discussed. The article noted that the growth rate for HfO.sub.2
is, typically, about 0.8 .ANG./cycle. Similarly, in a recent
article by K. Kukli et al., Journal of the Electrochemical Society,
vol. 148, no. 12, pp. F227-F232 (2001), dealing with ZrO.sub.2
formed by ALD using ZrI.sub.4, it was noted that at about a growth
temperature of about 300.degree. C., ZrO.sub.2 growth rate was
about 0.075 nm/cycle. Thus, in the embodiments for forming
HfO.sub.2/ZrO.sub.2 nanolaminates using ALD for all composite
layers, each material layer can be grown at about 0.75-0.80
.ANG./cycle.
[0087] FIG. 5 illustrates a flow diagram of elements for an
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2 using atomic layer deposition and thermal
evaporation/plasma oxidation, according to the teachings of the
present invention. In one embodiment, a nanolaminate of
HfO.sub.2/ZrO.sub.2 is formed by a method that includes forming a
layer of hafnium oxide on a substrate in a reaction chamber by
atomic layer deposition using a HfI.sub.4 precursor, at block 505,
forming a layer of zirconium on the layer of hafnium oxide by
thermal evaporation, at block 510, and oxidizing the zirconium
layer using a krypton(Kr)/oxygen(O.sub.2) mixed plasma to form a
HfO.sub.2/ZrO.sub.2 composite, at block 515. The
HfO.sub.2/ZrO.sub.2 composite is a nanolaminate, whose thickness
can be controlled by precisely controlling the ALD formation of
HfO.sub.2, and thermal deposition of zirconium. In one embodiment,
the thermal evaporation of zirconium is performed using electron
beam evaporation.
[0088] FIG. 6 shows an embodiment of an electron beam evaporation
process for forming a layer of zirconium on a layer of HfO.sub.2 to
process a nanolaminate of HfO.sub.2/ZrO.sub.2, according to the
teachings of the present invention. In the embodiment of FIG. 6, a
substrate 610 is located inside a deposition chamber 660. The
substrate in this embodiment is masked by a first masking structure
670 and a second masking structure 671. In this embodiment, the
unmasked region 633 includes a body region of a transistor on which
a layer of HfO.sub.2 is formed. However one skilled in the art will
recognize that other semiconductor device structures may utilize
this process. Also located within the deposition chamber 660 is an
electron gun 663 and a target 661. The electron gun 663 provides an
electron beam 664 directed at target 661 containing a source
material for forming ZrO.sub.2 on the unmasked region HfO.sub.2
layer 633 of the substrate 610. The electron gun 663 includes a
rate monitor for controlling the rate of evaporation of the
material in the target 661 at which the electron beam 664 is
directed. For convenience, control displays and necessary
electrical connections as are known to those skilled in the art are
not shown in FIG. 6.
[0089] During the evaporation process, the electron gun 663
generates an electron beam 664 that hits target 661. In one
embodiment, target 661 contains a zirconium metal source, which is
evaporated due to the impact of the electron beam 664. The
evaporated material 668 is then distributed throughout the chamber
660. A layer of zirconium is grown forming a film 640 on the
surface of the HfO.sub.2 layer 633 on substrate 610, which is
maintained at a temperature between 150.degree. C. and 200.degree.
C. The growth rate can vary with a typical rate of 0.1 .ANG./s.
After depositing a zirconium layer on the HfO.sub.2 layer 633, the
zirconium layer is oxidized.
[0090] The evaporation chamber 660 can be included as part of an
overall processing system including ALD system 200 of FIG. 2. To
avoid contamination of the surface of the HfO.sub.2 layer 633,
evaporation chamber 660 can be connected to ALD system 200 using
sealable connections to maintain the substrate, which is substrate
210 in FIG. 2 and substrate 610 of FIG. 6, in an appropriate
environment between ALD processing of the HfO.sub.2 layer and Zr
evaporation. Other means as are known to those skilled in the art
can be employed for maintaining an appropriate environment between
different processing procedures.
[0091] FIGS. 7A-7C show a low temperature oxidation process that is
used in one embodiment to form a layer of ZrO.sub.2 on a layer of
HfO.sub.2. FIG. 7A shows an embodiment of a zirconium layer 720
deposited on a HfO.sub.2 layer 710, according to the teachings of
the present invention. The HfO.sub.2 layer 710 is formed on
substrate 700 using an ALD process, as previously discussed, having
an substrate interface 730. The Zr layer 720 is deposited on the
HfO.sub.2 layer 710 by electron beam evaporation, as discussed
above, forming an interface 740 with the HfO.sub.2 layer 710 and
having an outer surface 750. The combined film with the Zr layer
720 deposited on the HfO.sub.2 layer 710 has a total thickness 752.
The layers 710, 720 are deposited over a body region of a
transistor, however the layers may be deposited on any surface
within the scope of the invention.
[0092] FIG. 7B shows an embodiment of a partially oxidized
zirconium layer 770 deposited on a HfO.sub.2 layer 710, according
to the teachings of the present invention. In FIG. 7B, the layer
720 is in the process of being oxidized. In one embodiment, the
oxidation process includes a krypton/oxygen mixed plasma oxidation
process. The mixed plasma process generates atomic oxygen or oxygen
radicals in contrast to molecular oxygen or O.sub.2 used in
conventional thermal oxidation. The atomic oxygen is introduced to
the layer from all exposed directions as indicated by arrows 760,
creating an oxide portion 770. The atomic oxygen continues to react
with the layer and creates an oxidation interface 742. As the
reaction progresses, atomic oxygen diffuses through the oxide
portion 770 and reacts at the oxidation interface 742 until the
layer is completely converted to an oxide of the deposited material
layer.
[0093] FIG. 7C shows an embodiment of a ZrO.sub.2 substantially
completely oxidized and formed on a layer of HfO.sub.2 to form a
nanolaminate of HfO.sub.2/ZrO.sub.2, according to the teachings of
the present invention. FIG. 7C shows the resulting oxide layer 770
which spans a physical thickness 772 from the outer surface 750 to
the interface 740. The overall thickness 752 of the
HfO.sub.2/ZrO.sub.2 composite in FIG. 7C has increased from that of
the Zr layer deposited on the HfO.sub.2 layer in FIG. 7A, due to
the oxidation of the zirconium.
[0094] In an embodiment, the processing variables for the mixed
plasma oxidation include a low ion bombardment energy of less than
7 eV, a high plasma density above 10.sup.12/cm.sup.3 and a low
electron temperature below 1.3 eV. In another embodiment, the
substrate temperature is approximately 400.degree. C. In another
embodiment, a mixed gas of 3% oxygen with the balance being krypton
at a pressure of 1 Torr is used. In one embodiment, a microwave
power density of 5 W/cm.sup.2 is used. The oxidation process
provides a growth rate of 1.5 nm/min.
[0095] The low temperature mixed plasma oxidation process described
above allows the deposited layer to be oxidized at a low
temperature. The mixed plasma process in one embodiment is
performed at approximately 400.degree. C. in contrast to prior
thermal oxidation processes that are performed at approximately
1000.degree. C.
[0096] FIG. 8 illustrates a flow diagram of elements for an
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2 using atomic layer deposition and chemical
vapor deposition (CVD), according to the teachings of the present
invention. This embodiment of the method includes forming a layer
of hafnium oxide on a substrate in a reaction chamber by atomic
layer deposition using a HfI.sub.4 precursor, at block 805, and
forming a layer of zirconium oxide on the layer of hafnium oxide by
chemical vapor deposition to form a HfO.sub.2/ZrO.sub.2 composite,
at block 810. The HfO.sub.2 layer is formed by ALD as discussed in
the embodiments above. In one embodiment, the ZrO.sub.2 layer is
formed by rapid thermal CVD at about 500.degree. C. Subsequently, a
nitrogen anneal is performed between about 700.degree. C. and about
800.degree. C. for about 30 sec. A rapid thermal CVD system, as is
known to those skilled in the art, is used to form the ZrO.sub.2
layer.
[0097] FIG. 9 illustrates a flow diagram of elements for an
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2 using atomic layer deposition and pulsed-laser
deposition, according to the teachings of the present invention.
This embodiment of the method includes forming a layer of hafnium
oxide on a substrate in a reaction chamber by atomic layer
deposition using a HfI.sub.4 precursor, at block 905, and forming a
layer of zirconium oxide on the layer of hafnium oxide by
pulsed-laser deposition to form a HfO.sub.2/ZrO.sub.2 composite, at
block 910. The HfO.sub.2 layer is formed by ALD as discussed in the
embodiments above. A pulsed-laser deposition system is similar to
the electron beam evaporation system 660 of FIG. 6 with the
electron gun 663 replaced by a laser and focusing optics, though
the laser and focusing optics need not be located in the
evaporation reaction chamber. A beam from the laser is focused on a
target, which causes an ablation of material from the target. The
material removed from the target deposits on an unmasked HfO.sub.2
layer located on a substrate. Controlling the focusing of the beam
from the laser on the source target provides for precision growth
rate of the ZrO.sub.2 layer.
[0098] In one embodiment, a substrate temperature is maintained
between about 200.degree. C. to about 800.degree. C. during
pulsed-laser deposition. A beam from a laser source such as a
excimer laser is focused on a rotating zirconium target source in a
deposition chamber with an O.sub.2 pressure of about 0.2 Torr to
form a ZrO.sub.2 layer on a HfO.sub.2 layer. Other laser sources
and configurations can be used as is known by those skilled in the
art.
[0099] FIG. 10 illustrates a flow diagram of elements for an
embodiment of a method to process a nanolaminate of
HfO.sub.2/ZrO.sub.2 using atomic layer deposition and jet-vapor
deposition, according to the teachings of the present invention.
This embodiment of the method includes forming a layer of hafnium
oxide on a substrate in a reaction chamber by atomic layer
deposition using a HfI.sub.4 precursor, at block 1005, and forming
a layer of zirconium oxide on the layer of hafnium oxide by
jet-vapor deposition to form a HfO.sub.2/ZrO.sub.2 composite, at
block 1010. The HfO.sub.2 layer is formed by ALD as discussed in
the embodiments above. The ZrO.sub.2 layer can be formed using
jet-vapor deposition techniques as is known to those skilled in the
art.
[0100] In one embodiment, the jet-vapor deposition zirconium and
oxygen vapors are directed to the HfO.sub.2 layer out of source
nozzles by supersonic Ar jets. Using jet-vapor deposition in a low
pressure atmosphere allows for forming the ZrO.sub.2 layer at at
room temperature. In one embodiment, annealing is performed
subsequent to forming the ZrO.sub.2 layer at a about 800.degree. C.
In one embodiment, the annealing is performed using a nitrogen
rapid thermal annealing (RTA). The annealing can be performed after
each ZrO.sub.2 layer is formed in the composite of alternating
layers of the HfO.sub.2/ZrO.sub.2 nanolaminate and/or at the
completion of the HfO.sub.2/ZrO.sub.2 nanolaminate.
[0101] In each of the various embodiments for forming ZrO.sub.2
layers, the HfO.sub.2/ZrO.sub.2 nanolaminates can be annealed in a
temperature range from between 300.degree. C. to 800.degree. C.
Typically the annealing is for a short time and in performed in a
nitrogen atmosphere or in some other inert atmosphere.
[0102] Bulk layers of HfO.sub.2 and bulk layers of ZrO.sub.2 both
have a dielectric constant of about 25. Consequently, a material
film composed of bulk layers of HfO.sub.2 and ZrO.sub.2 will also
have a dielectric constant of about 25. However, thin layers of a
material, typically, have dielectric constants somewhat less than
their bulk counterparts. The reduced value of the dielectric
constants for ultra thin material films is due in part to the
formation of an interfacial layer between the material film and the
substrate. Some materials formed on silicon substrates form a
SiO.sub.2 interfacial layer, while other materials form an silicide
interfacial layer. The material silicide in many cases will have a
dielectric greater than SiO.sub.2, but less than the bulk material
dielectric constant. ZrO.sub.2 formed on silicon substrates may
result in an interfacial region where silicon diffuses through a
layer of ZrO.sub.2 to form a poly-silicon/ZrO.sub.2/silicon
interfacial region, as reported by C. H. Lee et al., IEDM 2000,
27-30 (2000). Further, nanolaminates of ZrO.sub.2/HfO.sub.2 were
reported to have SiO.sub.2 interfacial layer when formed by ALD
using ZrCl.sub.4 and HfCl.sub.4 precursors. See H. Zhang et al.,
Journal of the Electrochemical Society, vol. 148, no. 4, pp.
F63-F66 (2001). To eliminate the SiO.sub.2 interfacial layer, Zhang
et al. grew ZrO.sub.2/HfO.sub.2 nanolaminates on nitrated Si
substrates producing dielectric constants ranging from 9 to 14 with
low leakage currents ranging from 2.2.times.10.sup.-6 to
1.2.times.10.sup.-8 .ANG./cm.sup.3 at 1 MV/cm.
[0103] In the various embodiments according to the teachings of the
present invention, HfO.sub.2/ZrO.sub.2 nanolaminates are formed by
ALD of HfO.sub.2 on substrates using a HfI.sub.4 precursor.
Subsequently, a layer of ZrO.sub.2 is formed on the HfO.sub.2 layer
by various deposition techniques. These HfO.sub.2/ZrO.sub.2
nanolaminates form a stable interface with a silicon substrate.
Using ALD, the size and effect of interfacial layer between the
silicon substrate and the first HfO.sub.2 layer will depend on the
reactivity of the HfO.sub.2 in forming an abrupt transition from
silicon surface to HfO.sub.2 layer. Consequently, dielectric films
containing HfO.sub.2/ZrO.sub.2 nanolaminates can have dielectric
constants ranging from 9 or 10 to 25. Additionally, forming the
HfO.sub.2 layer at relatively low temperatures provides a means for
enabling the formation of HfO.sub.2/ZrO.sub.2 nanolaminates that
are amorphous.
[0104] Another factor setting a lower limit for the scaling of a
dielectric layer is the number of monolayers of the dielectric
structure necessary to develop a full band gap such that good
insulation is maintained between an underlying silicon layer and an
overlying conductive layer on the dielectric layer or film. This
requirement is necessary to avoid possible short circuit effects
between the underlying silicon layer and the overlying conductive
layer used. In one embodiment, for several HfO.sub.2 monolayers and
several ZrO.sub.2 monolayers forming a nanolaminate, an expected
lower limit for the physical thickness of a dielectric layer grown
by forming HfO.sub.2/ZrO.sub.2 nanolaminates is anticipated to be
in about the 2-4 nm range. Consequently, typical dielectric layers
or films can be grown by forming HfO.sub.2/ZrO.sub.2 nanolaminates
having physical thickness in the range of 4 to 10 nm. HfO.sub.2
used as the initial layer is expected to provide excellent overall
results with respect to reliability, current leakage, and
ultra-thin t.sub.eq. Further, using ALD for processing all layers
of a HfO.sub.2/ZrO.sub.2 nanolaminate, the transitions between such
oxide layers can be engineered to be abrupt or graded. Thus, the
number of layers used, the thickness of each layer, and the nature
of the interface between each layer can be engineered to provide
the desired electrical characteristics.
[0105] With HfO.sub.2 layers formed by ALD and ZrO.sub.2 layers
formed according to one of the various embodiments described
herein, HfO.sub.2/ZrO.sub.2 nanolaminates can have a wide range of
thicknesses and dielectric constants. The physical thicknesses can
range from about 2 nm to about 10 nm with typical thickness ranging
from about 4 nm to about 10 nm. Such layers have an effective
dielectric constant ranging from 9 or 10 to 25. The expected
t.sub.eq ranges for various effective dielectric constants are
shown in the following: TABLE-US-00002 Physical Thickness Physical
Thickness Physical Thickness t = 0.5 nm (5 .ANG.) t = 1.0 nm (10
.ANG.) t = 5.0 nm (50 .ANG.) .kappa. t.sub.eq (.ANG.) t.sub.eq
(.ANG.) t.sub.eq (.ANG.) 9 2.17 4.33 21.67 17 1.15 2.29 11.47 21
.93 1.86 9.29 25 .78 1.56 7.8
[0106] As mentioned, the lower limit on the scaling of a layer
containing HfO.sub.2/ZrO.sub.2 nanolaminates depends on the
monolayers of the film necessary to develop a full band gap such
that good insulation is maintained between an underlying silicon
layer and an overlying conductive layer to the HfO.sub.2/ZrO.sub.2
nanolaminate film. From above, it is apparent that a film
containing HfO.sub.2/ZrO.sub.2 nanolaminates can be attained with a
t.sub.eq ranging from 3 .ANG. to 12 .ANG.. Further, a dielectric
film with completely formed band structures and monolayer
formations can provide a t.sub.eq significantly less than 2 or 3
.ANG..
[0107] The novel process described above provides significant
advantages by performing atomic layer deposition of
HfO.sub.2/ZrO.sub.2 in a hafnium sequence using HfI.sub.4
precursors followed by the formation of a ZrO.sub.2 layer on the
HfO.sub.2 layer. Further, by independently controlling the various
parameters for each sequence a gate dielectric with a selected
dielectric constant can be formed. Additionally, the novel process
can be implemented to form transistors, memory devices, and
information handling devices. With careful preparation and
engineering of the HfO.sub.2/ZrO.sub.2 nanolaminates limiting the
size of interfacial regions, a teq down to 2.5 .ANG. or lower is
anticipated.
[0108] A transistor 100 as depicted in FIG. 1 can be formed by
forming a source/drain region 120 and another source/drain region
130 in a silicon based substrate 110 where the two source/drain
regions 120, 130 are separated by a body region 132. The body
region 132 separated by the source/drain 120 and the source/drain
130 defines a channel having a channel length 134. A dielectric
film is formed on the substrate 110 by forming a layer of hafnium
oxide on substrate 110 in a reaction chamber by atomic layer
deposition using a HfI.sub.4 precursor and forming a layer of
zirconium oxide on the layer of hafnium oxide to form a
HfO.sub.2/ZrO.sub.2 composite. The resulting HfO.sub.2/ZrO.sub.2
composite is a nanolaminate. These HfO.sub.2/ZrO.sub.2
nanolaminates can be formed using any of the various embodiments
previously discussed. These HfO.sub.2/ZrO.sub.2 nanolaminates are
contained in a dielectric film defining the gate dielectric
140.
[0109] A gate is formed over the gate dielectric 140. Typically,
forming the gate includes forming a polysilicon layer, though a
metal gate can be formed in an alternative process. Forming the
substrate, source/region regions, and the gate is performed using
standard processes known to those skilled in the art. Additionally,
the sequencing of the various elements of the process for forming a
transistor is conducted with standard fabrication processes, also
as known to those skilled in the art.
[0110] Embodiments of the method of forming HfO.sub.2/ZrO.sub.2
nanolaminates as a gate dielectric can be applied to other
transistor structures having dielectric layers. For example, FIG.
11 shows an embodiment of a configuration of a transistor capable
of being fabricated, according to the teachings of the present
invention. The transistor 1100 includes a silicon based substrate
1110 with two source/drain regions 1120, 1130 separated by a body
region 1132. The body region 1132 between the two source/drain
regions 1120, 1130 defines a channel region having a channel length
1134. Located above the body region 1132 is a stack 1155 including
a gate dielectric 1140, a floating gate 1152, a floating gate
dielectric 1142, and control gate 1150. The gate dielectric 1140
containing HfO.sub.2/ZrO.sub.2 nanolaminates is formed according to
the teachings of the present invention as described above with the
remaining elements of the transistor 1100 formed using processes
known to those skilled in the art. Alternately, both the gate
dielectric 1140 and the floating gate dielectric 1142 can be formed
containing HfO.sub.2/ZrO.sub.2 nanolaminates, in accordance with
the present invention as described above.
[0111] Transistors created by the methods described above may be
implemented into memory devices and electronic systems including
information handling devices. Information handling devices having a
dielectric layer containing HfO.sub.2/ZrO.sub.2 nanolaminates can
be constructed using various embodiments of the methods described
above. Such information devices can include wireless systems,
telecommunication systems, and computers. An embodiment of a
computer having a dielectric layer containing HfO.sub.2/ZrO.sub.2
nanolaminates is shown in FIGS. 12-14 and described below. While
specific types of memory devices and computing devices are shown
below, it will be recognized by one skilled in the art that several
types of memory devices and electronic systems including
information handling devices utilize the invention.
[0112] FIG. 12 shows an embodiment of a personal computer 1200
incorporating devices, according to the teachings of the present
invention. Personal computer 1200 includes a monitor 1201, keyboard
input 1202 and a central processing unit 1204.
[0113] FIG. 13 illustrates a schematic view of an embodiment of a
central processing unit 1204 incorporating devices, according to
the teachings of the present invention. The central processing unit
1204 typically includes microprocessor 1306, memory bus circuit
1308 having a plurality of memory slots 1312(a-n), and other
peripheral circuitry 1310. Peripheral circuitry 1310 permits
various peripheral devices 1324 to interface processor-memory bus
1320 over input/output (I/O) bus 1322. The personal computer 1200
shown in FIGS. 12 and 13 also includes at least one transistor
having a gate dielectric containing HfO.sub.2/ZrO.sub.2
nanolaminates in an embodiment according to the teachings of the
present invention.
[0114] Microprocessor 1306 produces control and address signals to
control the exchange of data between memory bus circuit 1308 and
microprocessor 1306 and between memory bus circuit 1308 and
peripheral circuitry 1310. This exchange of data is accomplished
over high speed memory bus 1320 and over high speed I/O bus
1322.
[0115] Coupled to memory bus 1320 are a plurality of memory slots
1312(a-n) which receive memory devices well known to those skilled
in the art. For example, single in-line memory modules (SIMMs) and
dual in-line memory modules (DIMMs) may be used in the
implementation of the present invention.
[0116] These memory devices can be produced in a variety of designs
which provide different methods of reading from and writing to the
dynamic memory cells of memory slots 1312. One such method is the
page mode operation. Page mode operations in a DRAM are defined by
the method of accessing a row of a memory cell arrays and randomly
accessing different columns of the array. Data stored at the row
and column intersection can be read and output while that column is
accessed. Page mode DRAMs require access steps which limit the
communication speed of memory circuit 1308.
[0117] An alternate type of device is the extended data output
(EDO) memory which allows data stored at a memory array address to
be available as output after the addressed column has been closed.
This memory can increase some communication speeds by allowing
shorter access signals without reducing the time in which memory
output data is available on memory bus 1320. Other alternative
types of devices include SDRAM, DDR SDRAM, SLDRAM and Direct RDRAM
as well as others such as SRAM or Flash memories.
[0118] FIG. 14 illustrates a schematic view of an embodiment of a
DRAM memory device 1400 according to the teachings of the present
invention. DRAM device 1400 is compatible with memory slots
1312(a-n). The description of DRAM 1400 has been simplified for
purposes of illustrating a DRAM memory device and is not intended
to be a complete description of all the features of a DRAM. Those
skilled in the art will recognize that a wide variety of memory
devices may be used in the implementation of the present invention.
The example of a DRAM memory device shown in FIG. 14 includes at
least one transistor having a gate dielectric containing
HfO.sub.2/ZrO.sub.2 nanolaminates in an embodiment according to the
teachings of the present invention.
[0119] Control, address and data information provided over memory
bus 1320 is further represented by individual inputs to DRAM 1400,
as shown in FIG. 14. These individual representations are
illustrated by data lines 1402, address lines 1404 and various
discrete lines directed to control logic 1406.
[0120] As is well known in the art, DRAM 1400 includes memory array
1410 which in turn comprises rows and columns of addressable memory
cells. Each memory cell in a row is coupled to a common word line.
The word line is coupled to gates of individual transistors, where
at least one transistor has a gate coupled to a gate dielectric
containing HfO.sub.2/ZrO.sub.2 nanolaminates in accordance with the
method and structure previously described above. Additionally, each
memory cell in a column is coupled to a common bit line. Each cell
in memory array 1410 includes a storage capacitor and an access
transistor as is conventional in the art.
[0121] DRAM 1400 interfaces with, for example, microprocessor 1306
through address lines 1404 and data lines 1402. Alternatively, DRAM
1400 may interface with a DRAM controller, a micro-controller, a
chip set or other electronic system. Microprocessor 1306 also
provides a number of control signals to DRAM 1400, including but
not limited to, row and column address strobe signals RAS and CAS,
write enable signal WE, an output enable signal OE and other
conventional control signals.
[0122] Row address buffer 1412 and row decoder 1414 receive and
decode row addresses from row address signals provided on address
lines 1404 by microprocessor 1306. Each unique row address
corresponds to a row of cells in memory array 1410. Row decoder
1414 includes a word line driver, an address decoder tree, and
circuitry which translates a given row address received from row
address buffers 1412 and selectively activates the appropriate word
line of memory array 1410 via the word line drivers.
[0123] Column address buffer 1416 and column decoder 1418 receive
and decode column address signals provided on address lines 1404.
Column decoder 1418 also determines when a column is defective and
the address of a replacement column. Column decoder 1418 is coupled
to sense amplifiers 1420. Sense amplifiers 1420 are coupled to
complementary pairs of bit lines of memory array 1410.
[0124] Sense amplifiers 1420 are coupled to data-in buffers 1422
and data-out buffers 1424. Data-in buffers 1422 and data-out
buffers 1424 are coupled to data lines 1402. During a write
operation, data lines 1402 provide data to data-in buffers 1422.
Sense amplifier 1420 receives data from data-in buffers 1422 and
stores the data in memory array 1410 as a charge on a capacitor of
a cell at an address specified on address lines 1404.
[0125] During a read operation, DRAM 1400 transfers data to
microprocessor 1306 from memory array 1410. Complementary bit lines
for the accessed cell are equilibrated during a precharge operation
to a reference voltage provided by an equilibration circuit and a
reference voltage supply. The charge stored in the accessed cell is
then shared with the associated bit lines. A sense amplifier of
sense amplifiers 1420 detects and amplifies a difference in voltage
between the complementary bit lines. The sense amplifier passes the
amplified voltage to data-out buffers 1424.
[0126] Control logic 1406 is used to control the many available
functions of DRAM 1400. In addition, various control circuits and
signals not detailed herein initiate and synchronize DRAM 1400
operation as known to those skilled in the art. As stated above,
the description of DRAM 1400 has been simplified for purposes of
illustrating the present invention and is not intended to be a
complete description of all the features of a DRAM. Those skilled
in the art will recognize that a wide variety of memory devices,
including but not limited to, SDRAMs, SLDRAMs, RDRAMs and other
DRAMs and SRAMs, VRAMs and EEPROMs, may be used in the
implementation of the present invention. The DRAM implementation
described herein is illustrative only and not intended to be
exclusive or limiting.
CONCLUSION
[0127] A gate dielectric containing HfO.sub.2/ZrO.sub.2
nanolaminates and a method of fabricating such a gate produces a
reliable gate dielectric having an equivalent oxide thickness
thinner than attainable using SiO.sub.2. Gate dielectrics
containing HfO.sub.2/ZrO.sub.2 nanolaminates formed using the
methods described herein are thermodynamically stable such that the
gate dielectrics formed will have minimal reactions with a silicon
substrate or other structures during processing.
[0128] Transistors, higher level ICs or devices, and systems are
constructed utilizing the novel process for forming a gate
dielectric having an ultra thin equivalent oxide thickness,
t.sub.eq. Gate dielectric layers or films containing
HfO.sub.2/ZrO.sub.2 nanolaminates are formed having a high
dielectric constant (.kappa.), where the gate dielectrics are
capable of a t.sub.eq thinner than 10 .ANG., thinner than the
expected limit for SiO.sub.2 gate dielectrics. At the same time,
the physical thickness of the HfO.sub.2/ZrO.sub.2 nanolaminates is
much larger than the SiO.sub.2 thickness associated with the
t.sub.eq limit of SiO.sub.2. Forming the larger thickness provides
advantages in processing the gate dielectric. Further,
HfO.sub.2/ZrO.sub.2 nanolaminates processed in relatively low
temperatures can provide amorphous dielectric films having
relatively low leakage current for use as dielectric layers in
electronic devices and systems.
[0129] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement which is calculated to achieve the
same purpose may be substituted for the specific embodiment shown.
This application is intended to cover any adaptations or variations
of the present invention. It is to be understood that the above
description is intended to be illustrative, and not restrictive.
Combinations of the above embodiments, and other embodiments will
be apparent to those of skill in the art upon reviewing the above
description. The scope of the invention includes any other
applications in which the above structures and fabrication methods
are used. The scope of the invention should be determined with
reference to the appended claims, along with the full scope of
equivalents to which such claims are entitled.
* * * * *