U.S. patent application number 11/158456 was filed with the patent office on 2006-11-02 for internal clock generator.
Invention is credited to Geun Il Lee.
Application Number | 20060244503 11/158456 |
Document ID | / |
Family ID | 37233873 |
Filed Date | 2006-11-02 |
United States Patent
Application |
20060244503 |
Kind Code |
A1 |
Lee; Geun Il |
November 2, 2006 |
Internal clock generator
Abstract
An internal clock generator that modulates a high-frequency
clock signal to a low-frequency signal to transmit the
low-frequency signal if a transmission line for transmitting the
high-frequency clock signal is long, and then restores the
transmitted low-frequency signal to the high-frequency signal. The
internal clock generator includes a first signal generation unit
for receiving a first signal having a first frequency and
generating a second signal having a second frequency that is lower
than the first frequency, and a second signal generation unit for
receiving the second signal and generating a third signal having a
frequency equal to the first frequency. Here, the third signal is
used as a signal for controlling an operating time point of an
internal circuit of a synchronous memory device.
Inventors: |
Lee; Geun Il; (Kyoungki-do,
KR) |
Correspondence
Address: |
LADAS & PARRY LLP
224 SOUTH MICHIGAN AVENUE
SUITE 1600
CHICAGO
IL
60604
US
|
Family ID: |
37233873 |
Appl. No.: |
11/158456 |
Filed: |
June 22, 2005 |
Current U.S.
Class: |
327/291 |
Current CPC
Class: |
G06F 1/04 20130101 |
Class at
Publication: |
327/291 |
International
Class: |
G06F 1/04 20060101
G06F001/04 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 27, 2005 |
KR |
10-2005-0034974 |
Claims
1. An internal clock generator comprising: a first signal
generation unit for receiving a first signal having a first
frequency and generating a second signal having a second frequency
that is lower than the first frequency; and a second signal
generation unit for receiving the second signal and generating a
third signal having a frequency equal to the first frequency.
2. The internal clock generator as claimed in claim 1, wherein the
third signal is used as a signal for controlling an operating time
point of an internal circuit of a synchronous memory device.
3. An internal clock generator comprising: a frequency modulation
unit for receiving a first clock signal having a first frequency
and outputting second and third clock signal having a second
frequency; and a clock generation unit for receiving the second and
third clock signals and outputting a fourth clock signal having the
first frequency.
4. The internal clock generator as claimed in claim 3, wherein if
the first frequency is fo, the second frequency becomes fo/2.
5. The internal clock generator as claimed in claim 4, wherein a
rising edge of the second clock signal is in synchronization with a
rising edge of the first clock signal, and a rising edge of the
third clock signal is in synchronization with a falling edge of the
first clock signal.
6. The internal clock generator as claimed in claim 5, wherein a
high-level period of the second and third clock signals is equal to
a period of the first clock signal.
7. The internal clock generator as claimed in claim 3, wherein the
first frequency is the same as a frequency of an external clock
applied to a synchronous memory device.
8. The internal clock generator as claimed in claim 7, wherein the
fourth clock signal is applied to an internal circuit of the
synchronous memory device and controls an operating time point of
the internal circuit.
9. The internal clock generator as claimed in claim 8, wherein a
transmission distance of the second and third clock signals that
reach the clock generation unit is longer than a transmission
distance of the fourth clock signal that reaches the internal
circuit.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the invention
[0002] The present invention relates to an internal clock generator
used in a high-speed semiconductor device.
[0003] 2. Description of the Prior Art
[0004] Generally, a synchronous semiconductor device controls an
internal operation of the semiconductor device using an internal
clock that is synchronized with an external clock. A representative
synchronous semiconductor device may be a synchronous memory device
(hereinafter referred to as a memory device) such as an SDRAM, DDR,
SDRAM, etc.
[0005] Recently, with the development of technology, the operating
frequency of a memory device is greatly being heightened and the
size of the memory device is gradually increasing as well.
Typically, the fact that the operating frequency of the memory
device is increasing means that the frequency of the internal clock
is also being heightened. Here, as a moving distance (i.e.,
transmission distance) of the internal clock is increasing, an RC
loading of a transmission line is also increasing. However, in the
case in which the loading of the transmission line is increasing, a
problem may occur in transmitting a high-frequency signal.
[0006] Hereinafter, the conventional method of transmitting an
internal clock will be explained with reference to the accompanying
drawings.
[0007] FIG. 1 is a block diagram of a general memory device that
uses the internal clock.
[0008] Referring to FIG. 1, a clock buffer 101 receives an external
clock signal of an SSTL level or a TTL level. A clock generator 102
receives an output signal of the clock buffer 101, and generates an
internal clock ICLK.
[0009] The internal clock ICLK is applied to a column control unit
11, a row control unit 12, a command control unit 13, a data
control unit 14, etc., in the memory device, and controls the
operating timing of the memory device. Here, the column control
device 11 is a circuit for controlling a column operation of the
memory device, and the row control unit 12 is a circuit for
controlling a row operation of the memory device. Also, the command
control unit 13 is a circuit for controlling a command such as an
active, read, write, precharge, etc., and the data control unit 14
is an input/output (I/O) unit of the memory device.
[0010] FIG. 2 is a view illustrating an example of a conventional
clock generator 102 used in the memory device of FIG. 1.
[0011] As illustrated in FIG. 2, a clock generator causes no
trouble in the case in which a period of an input signal IN is
longer than a delay time of a delay unit 21.
[0012] However, if the period of the input signal IN is shorter
than the delay time of the delay unit 21, the memory device may
malfunction. Specifically, if the input signal IN is a
high-frequency signal over 500 MHz, it is difficult to apply such a
clock generator to a high-speed memory device.
[0013] Additionally, in the case in which a signal transmission
line is long, this may cause a problem in that the loading of the
transmission line becomes extremely great and thus the
high-frequency signal is not properly transferred.
SUMMARY OF THE INVENTION
[0014] Accordingly, the present invention has been made to solve
the above-mentioned problems occurring in the prior art, and an
object of the present invention is to provide an internal clock
generator that modulates a high-frequency clock signal to a
low-frequency signal to transmit the low-frequency signal if a
transmission line for transmitting the high-frequency clock signal
is long, and then restores the transmitted low-frequency signal to
the high-frequency signal.
[0015] In a first embodiment of the present invention, there is
provided an internal clock generator comprising a first signal
generation unit for receiving a first signal having a first
frequency and generating a second signal having a second frequency
that is lower than the first frequency, and a second signal
generation unit for receiving the second signal and generating a
third signal having a frequency equal to the first frequency.
[0016] Here, the third signal is used as a signal for controlling
an operating time point of an internal circuit of a synchronous
memory device.
[0017] In a second embodiment of the present invention, there is
provided an internal clock generator comprising a frequency
modulation unit for receiving a first clock signal having a first
frequency and outputting second and third clock signal having a
second frequency, and a clock generation unit for receiving the
second and third clock signals and outputting a fourth clock signal
having the first frequency.
[0018] Here, if the first frequency is fo, the second frequency
becomes fo/2.
[0019] Additionally, a rising edge of the second clock signal is in
synchronization with a rising edge of the first clock signal, and a
rising edge of the third clock signal is in synchronization with a
falling edge of the first clock signal.
[0020] It is preferable that a high-level period of the second and
third clock signals is equal to a period of the first clock
signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The above and other objects, features and advantages of the
present invention will be more apparent from the following detailed
description taken in conjunction with the accompanying drawings, in
which:
[0022] FIG. 1 is a block diagram of a general memory device that
uses the internal clock;
[0023] FIG. 2 is an exemplary circuit diagram of a conventional
clock generator 102 used in the memory device of FIG. 1;
[0024] FIG. 3 is a block diagram of an internal clock generator
according to an embodiment of the present invention;
[0025] FIG. 4 is an exemplary circuit diagram of a frequency
modulator as illustrated in FIG. 3;
[0026] FIG. 5 is an exemplary circuit diagram of a clock generator
as illustrated in FIG. 3; and
[0027] FIG. 6 is a waveform diagram illustrating clock signals IN,
Up_clk, Down_clk and ICLK that appear in the circuits of FIGS. 3 to
5.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0028] Hereinafter, preferred embodiments of the present invention
will be described with reference to the accompanying drawings. In
the following description and drawings, the same reference numerals
are used to designate the same or similar components, and so
repetition of the description on the same or similar components
will be omitted.
[0029] FIG. 3 is a block diagram of an internal clock generator
according to an embodiment of the present invention.
[0030] In FIG. 3, the construction and operation of a clock buffer
301 that receives an external clock signal CLK are the same as
those of the conventional clock buffer. For example, the clock
buffer 301 is the same as the clock buffer 101 explained with
reference to FIG. 1. Also, the period of a clock signal IN output
from the clock buffer 301 is the same as that of the external clock
signal CLK (See FIG. 6).
[0031] A frequency modulation unit 302 modulates the frequency of
the clock signal IN output from the clock buffer 301. In an
embodiment of the present invention, the frequency of output
signals Up_clk and Down_clk of the frequency modulation unit 302 is
a 1/2 of the frequency of the clock signal IN. That is, the
frequency modulation unit 302 of FIG. 3 performs the same function
as a frequency divider. Here, the clock signal Up_clk rises in
synchronization with a rising edge of the clock signal IN, and
falls in synchronization with a rising edge of the next clock
signal IN (See FIG. 6). Additionally, the clock signal Down_clk
rises in synchronization with a falling edge of the clock signal
IN, and falls in synchronization with a falling edge of the next
clock signal IN (See FIG. 6).
[0032] Clock generation units 35 to 38 receive in common the output
signals Up_clk and Down_clk of the frequency modulation unit 302,
and output an internal clock signal ICLK. The clock generation
units 35 to 38 correspond to a column control unit 31, a row
control unit 32, a command decoder 33 and a data control unit 34
etc. in a one-to-one manner because there are differences in
distance from frequency unit(differences in operating time points)
among the column control unit 31, row control unit 32, command
decoder 33 and data control unit 34 etc.
[0033] The clock generation units 35 to 38 that have received the
clock signals Up_clk and Down_clk combine the clock signals and
generate the internal clock signal ICLK having the same frequency
as the clock signal IN.
[0034] The frequency modulation unit and the clock generation units
as described above are constituent elements of the internal clock
generator newly proposed in one embodiment of the present
invention.
[0035] FIG. 4 is an exemplary circuit diagram of the frequency
modulation unit as illustrated in FIG. 3. In FIG. 3, a method of
increasing twice the period of the input clock signal IN using
flip-flops is illustrated. Here, a power-up signal pwrup is a
signal for sensing an input of an external power supply to the
memory device and initializing internal circuits of the memory
device when the external power is supplied to the memory device.
Specifically, the power-up signal sets an initial level of the
flip-flops.
[0036] In FIG. 4, the flip-flop 41 receives the clock signal IN and
outputs the clock signal Up_clk having the period that is twice the
period of the clock signal IN, and the the flip-flop 42 receives
the clock signal IN and outputs the clock signal Down_clk having
the period that is twice the period of the clock signal IN. As
described above, the clock signal Up_clk rises in synchronization
with the rising edge of the clock signal IN and falls in
synchronization with the rising edge of the next clock signal, and
the clock signal Down_clk rises in synchronization with the falling
edge of the clock signal IN and falls in synchronization with the
falling edge of the next clock signal IN. For reference, the
flip-flop 42 receives an inversed signal of the clock signal
IN.
[0037] The frequency modulation unit of FIG. 4 is exemplary, and it
is apparent to those skilled in the art that diverse circuits for
dividing the frequency by 2 can be used in place of the frequency
modulation unit.
[0038] FIG. 5 is an exemplary circuit diagram of the clock
generator as illustrated in FIG. 3.
[0039] The clock generator of FIG. 5 includes a NAND gate 51 for
receiving the clock signals Up_clk and Down_clk, an inverter 52 for
receiving an output signal of the NAND gate 51, a NOR gate 53 for
receiving the clock signals Up_clk and Down_clk, a NAND gate 54 for
receiving an output signal of the inverter 52 and an output signal
of the NOR gate 53, and an inverter 55 for receiving an output
signal of the NAND gate 54. The inverter 55 outputs the internal
clock signal ICLK.
[0040] FIG. 6 is a waveform diagram illustrating clock signals IN,
Up_clk, Down_clk and ICLK that appear in the circuits of FIGS. 3 to
5.
[0041] As can be seen in FIG. 6, the period of the clock signals
Up_clk and Down_clk is twice the period of the clock signal IN, and
the period of the internal clock signal ICLK is equal to the period
of the clock signal IN.
[0042] Hereinafter, the operation of the internal clock generator
according to the present invention that is advantageous in
high-frequency operation will be explained in detail with reference
to FIGS. 3 to 6.
[0043] The clock buffer 301 receives the external clock signal CLK
of the SSTL level or the TTL level, and output the clock signal IN.
Here, the low level of the clock signal IN corresponds to a ground
voltage, and the high level thereof corresponds to a driving
voltage VCC. That is, the clock signal IN is a clock signal fully
swinging between the ground voltage and the driving voltage VCC.
Here, the driving voltage VCC is for driving the clock buffer
301.
[0044] The frequency modulation unit 302 generates and transmits
the clock signals Up_clk and Down_clk having the period that is
twice the period of the clock signal IN to the clock generation
units 35 to 38. In the case of doubling the period of the
high-frequency clock signal IN as in the internal clock generator
according to the present invention, a signal distortion is greatly
reduced in comparison to the conventional clock generator.
Particularly, if the loading of the transmission line is great, the
signal distortion can properly be reduced by transmitting the
low-frequency signal using the frequency modulation unit.
[0045] The clock generation units 35 to 38 receive the output
signals of the frequency modulation unit 302, generate and provide
the internal clock signal ICLK having the same frequency as the
operating frequency of the memory device to the column control unit
31, the row control unit 32, etc.
[0046] In the present invention, the clock signals Up_clk and
Down_clk having the lower frequency than the clock signal IN are
generated and transferred to the clock generation units, and then
the internal clock signal ICLK is generated. Here, it is preferable
to make the transmission distance of the clock signals Up_clk and
Down_clk, which reach the clock generation units, longer than the
distance of the internal clock signal ICLK which reaches the column
control units 31, etc. By doing so, the signal distortion which may
occur during the transmission of the high-frequency signal can be
prevented. As described above, the present invention can prevent
the signal distortion occurring when the high-frequency signal is
transmitted for a long distance through the transmission of the
low-frequency signal instead of the high-frequency signal.
Particularly, it may be possible that the clock signal transmission
is performed using the same circuit as the conventional circuit if
the internal transmission line is short, while the clock signal
transmission is performed using the circuit proposed according to
the present invention if the internal transmission line is
long.
[0047] As described above, according to the present invention which
is applicable to an ultrahigh-speed memory device, a stable
internal clock signal can be generated by transmitting a
low-frequency clock signal through a transmission line of a great
loading and then generating an internal clock signal having the
same frequency as an operating frequency using the transmitted
low-frequency signal.
[0048] The present invention is not limited to this, but in the
case in which the loading of the transmission line is extremely
great, the clock signal having a frequency that is four times or
more lower than the original clock signal may be generated and
transmitted, and then the transmitted lower-frequency clock signal
may be restored to the original clock signal.
[0049] In the case in which the internal clock generator according
to the present invention is used, a stable internal clock can be
generated even if the operating frequency is greatly high.
[0050] Although preferred embodiments of the present invention have
been described for illustrative purposes, those skilled in the art
will appreciate that various modifications, additions and
substitutions are possible, without departing from the scope and
spirit of the invention as disclosed in the accompanying
claims.
* * * * *