U.S. patent application number 11/108186 was filed with the patent office on 2006-10-19 for reference circuit that provides a temperature dependent voltage.
Invention is credited to Russell Houghton, Helmut Seitz, Ernst Stahl.
Application Number | 20060232326 11/108186 |
Document ID | / |
Family ID | 37107922 |
Filed Date | 2006-10-19 |
United States Patent
Application |
20060232326 |
Kind Code |
A1 |
Seitz; Helmut ; et
al. |
October 19, 2006 |
Reference circuit that provides a temperature dependent voltage
Abstract
A reference circuit that includes a first circuit configured to
provide a temperature dependent current, a second circuit
configured to provide a first current, and a third circuit. The
third circuit is configured to provide a temperature dependent
voltage based on the first current and the temperature dependent
current. The temperature dependent voltage has a voltage versus
temperature slope established by the third circuit and a voltage
level established by the first current.
Inventors: |
Seitz; Helmut; (Essex
Junction, VT) ; Houghton; Russell; (Essex Junction,
VT) ; Stahl; Ernst; (Essex Junction, VT) |
Correspondence
Address: |
DICKE, BILLIG & CZAJA, P.L.L.C.
FIFTH STREET TOWERS
100 SOUTH FIFTH STREET, SUITE 2250
MINNEAPOLIS
MN
55402
US
|
Family ID: |
37107922 |
Appl. No.: |
11/108186 |
Filed: |
April 18, 2005 |
Current U.S.
Class: |
327/539 ;
327/541 |
Current CPC
Class: |
G11C 11/4074 20130101;
G11C 5/143 20130101; G11C 11/4076 20130101; G11C 5/147 20130101;
G05F 3/30 20130101 |
Class at
Publication: |
327/539 ;
327/541 |
International
Class: |
G05F 1/10 20060101
G05F001/10 |
Claims
1. A reference circuit comprising: a first circuit configured to
provide a temperature dependent current; a second circuit
configured to provide a first current; and a third circuit
configured to provide a temperature dependent voltage based on the
first current and the temperature dependent current, wherein the
temperature dependent voltage has a voltage versus temperature
slope established by the third circuit and a voltage level
established by the first current.
2. The reference circuit of claim 1, wherein the second circuit
provides a second current that comprises the first current and the
temperature dependent current and the third circuit is configured
to provide a third current that mirrors the second current.
3. The reference circuit of claim 1, wherein the third circuit
includes a resistive element configured to receive a current that
mirrors the first current and the temperature dependent current and
to establish the voltage versus temperature slope of the
temperature dependent voltage.
4. The reference circuit of claim 1, wherein the first circuit
comprises: a first resistive element; and a diode coupled to the
first resistive element, wherein the diode has a diode voltage that
is dependent on temperature and a constant voltage is applied
across the first resistive element and the diode to provide the
temperature dependent current.
5. The reference circuit of claim 4, wherein the second circuit
includes a second resistive element coupled across the first
resistive element and the diode and configured to provide the first
current.
6. The reference circuit of claim 1, wherein the first circuit
comprises: a bandgap reference circuit; and a current mirror
coupled to the bandgap reference to provide the temperature
dependent current.
7. An electronic system comprising: a random access memory that
includes a reference circuit configured to provide a temperature
dependent reference voltage, wherein the reference circuit
comprises: a temperature dependent current source configured to
provide a temperature dependent current; a constant current source
configured to provide a constant current; and a circuit configured
to mirror the constant current and the temperature dependent
current and provide the temperature dependent reference voltage
based on the mirrored constant current and temperature dependent
current, wherein the circuit is configured to provide a voltage
level of the temperature dependent reference voltage based on the
constant current and to establish a voltage versus temperature
slope of the temperature dependent reference voltage.
8. The electronic system of claim 7, wherein the random access
memory includes a regulator configured to receive the temperature
dependent reference voltage and provide a temperature dependent
output voltage based on the temperature dependent reference
voltage.
9. The electronic system of claim 8, wherein the random access
memory includes a temperature dependent delay chain configured to
receive the temperature dependent output voltage and provide a
substantially constant delay versus temperature.
10. The electronic system of claim 7, wherein the circuit
comprises: a differential amplifier configured to receive a first
constant voltage; and a first transistor configured to be
controlled by the differential amplifier to provide a second
constant voltage and to provide a first current comprising the
temperature dependent current and the constant current.
11. The electronic system of claim 10, wherein the circuit
comprises: a second transistor configured to be controlled by the
differential amplifier and to provide a second current that mirrors
the first current; and a resistive element configured to receive
the second current to provide the temperature dependent reference
voltage and the voltage versus temperature slope of the temperature
dependent reference voltage.
12. A reference circuit comprising: a temperature dependent current
source configured to provide a temperature dependent current; a
constant current source configured to provide a constant current; a
differential amplifier configured to receive a first constant
voltage and provide an output voltage; a first transistor
configured to receive the output voltage to provide a second
constant voltage and to provide a first current comprising the
temperature dependent current and the constant current; a second
transistor configured to receive the output voltage to provide a
second current that mirrors the first current; and a first
resistive element configured to receive the second current to
provide a temperature dependent voltage and a voltage versus
temperature slope of the temperature dependent voltage, wherein a
voltage level of the temperature dependent voltage is based on the
constant current.
13. The reference circuit of claim 12, wherein the constant current
source comprises a resistive element configured to receive the
second constant voltage to provide the constant current.
14. The reference circuit of claim 12, wherein the temperature
dependent current source comprises: a resistive element; and a
diode coupled to the resistive element.
15. The reference circuit of claim 12, wherein the temperature
dependent current source comprises: a bandgap reference circuit;
and a current mirror coupled to the bandgap reference.
16. A random access memory comprising: means for providing a
temperature dependent current; means for providing a current to
establish a voltage level of a temperature dependent voltage; means
for mirroring the current and the temperature dependent current to
provide the temperature dependent voltage; and means for
establishing a voltage versus temperature slope of the temperature
dependent voltage.
17. The random access memory of claim 16, wherein the means for
providing a temperature dependent current comprises: means for
applying a constant voltage across a resistor and a diode.
18. The random access memory of claim 16, wherein the means for
providing a temperature dependent current comprises: means for
mirroring a bandgap reference temperature dependent current.
19. The random access memory of claim 16, comprising: means for
regulating a temperature dependent output voltage based on the
temperature dependent voltage.
20. A method for providing a temperature dependent voltage
comprising: providing a temperature dependent current; providing a
current; mirroring the current and the temperature dependent
current to provide the temperature dependent voltage; establishing
a voltage versus temperature slope of the temperature dependent
voltage; and establishing a voltage level of the temperature
dependent voltage.
21. The method of claim 20, wherein providing a temperature
dependent current comprises: applying a constant voltage across a
resistor and a diode.
22. The method of claim 20, wherein providing a temperature
dependent current comprises: mirroring a bandgap reference
temperature dependent current.
23. The method of claim 20, wherein providing a current comprises:
applying a constant voltage across a resistor.
24. The method of claim 20, comprising: regulating a temperature
dependent output voltage based on the temperature dependent
voltage.
25. A method for providing a temperature dependent output voltage
in a random access memory, comprising: receiving a temperature
dependent current; receiving a constant current; combining the
temperature dependent current and the constant current; mirroring
the combined current; receiving the mirrored current at a resistor
to provide a voltage level of a temperature dependent reference
voltage based on the constant current and to establish a voltage
versus temperature slope of the temperature dependent reference
voltage.
26. The method of claim 25, comprising: receiving the temperature
dependent reference voltage; and regulating a temperature dependent
output voltage based on the temperature dependent reference
voltage.
27. The method of claim 25, comprising: receiving a first constant
voltage at a differential amplifier; and controlling a first
transistor via the differential amplifier to provide a second
constant voltage and the combined current.
28. The method of claim 27, wherein mirroring the combined current
comprises controlling a second transistor via the differential
amplifier to provide a second current that mirrors the combined
current.
29. A method for providing a temperature dependent voltage
comprising: receiving a temperature dependent current; receiving a
constant current; receiving a first constant voltage at a
differential amplifier to provide an output voltage; receiving the
output voltage at a first transistor to provide a second constant
voltage and a first current comprising the temperature dependent
current and the constant current; receiving the output voltage at a
second transistor to provide a second current that mirrors the
first current; and receiving the second current at a first
resistive element to provide a temperature dependent voltage and a
voltage versus temperature slope of the temperature dependent
voltage and to establish a voltage level of the temperature
dependent voltage based on the constant current.
30. The method of claim 29, comprising: receiving the second
constant voltage at a second resistive element to provide the
constant current.
31. The method of claim 29, comprising: receiving the second
constant voltage across a third resistive element and a diode
coupled to the third resistive element to provide the temperature
dependent current.
32. The method of claim 29, comprising: providing the temperature
dependent current via a current mirror coupled to a bandgap
reference.
Description
BACKGROUND
[0001] Memory speed and memory capacity continue to increase to
meet the demands of system applications. Some of these system
applications include mobile electronic systems that have limited
space and limited power resources. In mobile applications, such as
cellular telephones and personal digital assistants (PDAs), memory
cell density and power consumption are issues for future
generations.
[0002] To address these issues, the industry is developing random
access memories (RAMs) for mobile applications. One type of RAM,
referred to as CellularRAM, is a high performance and low power
memory designed to meet the growing memory density and bandwidth
demands of future designs. CellularRAM is a pseudo static RAM
(PSRAM) that offers a lower cost per bit ratio than current
solutions. Also, CellularRAM offers static RAM (SRAM) pin and
function compatibility, external refresh-free operation, and a low
power design. CellularRAM devices are drop-in replacements for most
asynchronous low power SRAMs currently used in mobile applications,
such as cellular telephones.
[0003] Typically, a PSRAM is based on a dynamic RAM (DRAM) that
provides significant advantages in density and speed over
traditional SRAM. The DRAM can include one transistor and one
capacitor memory cells that are arranged in one or more arrays of
memory cells, which are arranged in memory banks. To read and write
memory cells, each DRAM includes one or more row decoders, one or
more column decoders, and sense amplifiers. The sense amplifiers
can be differential sense amplifiers, wherein each sense amplifier
receives one bit line at each of two differential inputs.
[0004] To read or write memory cells, the DRAM receives a row
address, a column address, and control signals, such as row address
select (RAS) and column address select (CAS) signals. A row decoder
receives the row address to select a row of memory cells and the
row address is latched into the row decoder via the RAS signal. A
column decoder receives the column address to select one or more
columns of memory cells and the column address is latched into the
column decoder via the CAS signal. Each memory cell at the
intersection of a selected row and a selected column provides a
data bit to a sense amplifier.
[0005] At each sense amplifier that receives data, one of the bit
lines receives the data bit from a selected memory cell and the
other bit line is used as a reference. To read the data bit, the
sense amplifier amplifies the difference between the data bit value
and the reference value and provides a sensed output value to an
output driver. To write a data bit into a selected memory cell,
input drivers overdrive the sense amplifier. One input driver
overdrives a data bit value onto the bit line that is connected to
the selected memory cell and another input driver overdrives the
inverse of the data bit value onto the reference bit line.
[0006] Typically, a PSRAM receives SRAM control signals that do not
include DRAM control signals, such as RAS and CAS signals. As a
result, the PSRAM internally provides the DRAM control signals to
read data from and write data into the DRAM memory. The DRAM
control signals include timing constraints that must be met to
operate the DRAM. These timing constraints include timing
parameters such as the minimum amount of time that the RAS signal
is active (tRAS), the minimum amount of time that the RAS signal is
inactive, referred to as RAS precharge time (tRP), the minimum
amount of time for a RAS cycle (tRC), and the minimum amount of
time to recover from a write operation, referred to as write
recovery time (tWR).
[0007] The PSRAM includes delay chains to provide the DRAM control
signals and meet the timing constraints of the DRAM control
signals. Typically, the speeds of the delay chains are temperature
dependent, such that the timing of the DRAM control signals will
vary with temperature. As the timing of the DRAM control signals
change with temperature, the PSRAM may become unreliable or stop
working altogether.
[0008] For these and other reasons there is a need for the present
invention.
SUMMARY
[0009] One aspect of the present invention provides a reference
circuit that includes a first circuit configured to provide a
temperature dependent current, a second circuit configured to
provide a first current, and a third circuit. The third circuit is
configured to provide a temperature dependent voltage based on the
first current and the temperature dependent current. The
temperature dependent voltage has a voltage versus temperature
slope established by the third circuit and a voltage level
established by the first current.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a block diagram illustrating one embodiment of an
electronic system according to the present invention.
[0011] FIG. 2 is a block diagram illustrating one embodiment of an
electronic system according to the present invention including a
controller and a RAM.
[0012] FIG. 3 is a diagram illustrating one embodiment of a memory
cell in an array of memory cells.
[0013] FIG. 4 is a diagram illustrating one embodiment of a
temperature dependent reference circuit.
[0014] FIG. 5 is a diagram illustrating one embodiment of a
regulator circuit.
[0015] FIG. 6 is a diagram illustrating one embodiment of a
temperature dependent reference circuit including a band gap
reference circuit and a current mirror circuit.
DETAILED DESCRIPTION
[0016] In the following Detailed Description, reference is made to
the accompanying drawings, which form a part hereof, and in which
is shown by way of illustration specific embodiments in which the
invention may be practiced. In this regard, directional
terminology, such as "top," "bottom," "front," "back," "leading,"
"trailing," etc., is used with reference to the orientation of the
Figure(s) being described. Because components of embodiments of the
present invention can be positioned in a number of different
orientations, the directional terminology is used for purposes of
illustration and is in no way limiting. It is to be understood that
other embodiments may be utilized and structural or logical changes
may be made without departing from the scope of the present
invention. The following detailed description, therefore, is not to
be taken in a limiting sense, and the scope of the present
invention is defined by the appended claims.
[0017] FIG. 1 is a block diagram illustrating one embodiment of an
electronic system 20 according to the present invention. The
electronic system 20 includes a temperature dependent reference
circuit 22. Electronic system 20 can be any suitable electronic
system, such as an integrated circuit chip, multiple integrated
circuit chips, or a computer system including a controller and
memory.
[0018] Temperature dependent reference circuit 22 provides a
temperature dependent reference voltage VREF at 24. Temperature
dependent reference circuit 22 includes circuitry that provides a
temperature dependent current, a constant current, and the
temperature dependent reference voltage VREF at 24 based on the
constant current and the temperature dependent current. The
temperature dependent reference voltage VREF at 24 has a voltage
versus temperature slope that is established via one part of the
temperature dependent reference circuit 22 and a voltage level that
is established via another part of the temperature dependent
reference circuit 22. The voltage versus temperature slope and the
voltage level of the temperature dependent reference voltage VREF
at 24 are individually established parameters of the temperature
dependent reference voltage VREF at 24. In one embodiment, as the
temperature increases, the temperature dependent reference voltage
VREF at 24 increases and as the temperature decreases, the
temperature dependent reference voltage VREF at 24 decreases.
[0019] Electronic system 20 includes circuitry that receives the
temperature dependent reference voltage VREF at 24 and uses the
temperature dependent reference voltage VREF at 24 for any suitable
purpose in electronic system 20. In one embodiment, electronic
system 20 includes a delay chain, wherein the speed of the delay
chain varies with temperature due to device characteristics. As the
temperature increases, the speed of the delay chain decreases and
as the temperature decreases, the speed of the delay chain
increases. The speed of the delay chain is also dependent on the
delay chain supply voltage. As the supply voltage increases, the
speed of the delay chain increases and as the supply voltage
decreases, the speed of the delay chain decreases. To keep the
speed of the delay chain constant, electronic circuit 20 provides a
temperature dependent output voltage as a supply voltage to the
delay chain. The temperature dependent output voltage is based on
the temperature dependent reference voltage VREF at 24. As the
temperature increases, the temperature dependent reference voltage
VREF at 24 and the temperature dependent output voltage increase to
increase the speed of the delay chain at higher temperatures. As
the temperature decreases, the temperature dependent reference
voltage VREF at 24 and the temperature dependent output voltage
decrease to decrease the speed of the delay chain at lower
temperatures. The speed of the delay chain can be made constant
over temperature, i.e., independent of temperature, using the
temperature dependent reference voltage VREF at 24 to provide a
temperature dependent output voltage as the delay chain supply
voltage.
[0020] FIG. 2 is a block diagram illustrating one embodiment of an
electronic system 40 according to the present invention. Electronic
system 40 includes a controller 42 and a RAM 44. Controller 42 is
electrically coupled to RAM 44 via memory communications path 46
and data communications path 48. Controller 42 provides row and
column addresses and control signals to RAM 44 via memory
communications path 46. Controller 42 provides data to RAM 44 and
receives data from RAM 44 via data communications path 48. In one
embodiment, RAM 44 is a PSRAM. In other embodiments, RAM 44 can be
any suitable RAM.
[0021] RAM 44 includes an array of memory cells 50, a row address
latch and decoder 52, a column address latch and decoder 54, a
sense amplifier circuit 56, a RAM I/O circuit 58, an address
register 60, a control circuit 62, and a temperature dependent
voltage source 64. Conductive word lines 66, referred to as row
select lines, extend in the x-direction across the array of memory
cells 50. Conductive bit lines 68, referred to as bit lines, extend
in the y-direction across the array of memory cells 50. A memory
cell 70 is located at each cross point of a word line 66 and a bit
line 68.
[0022] Each word line 66 is electrically coupled to row address
latch and decoder 52 and each bit line 68 is electrically coupled
to one of the sense amplifiers in sense amplifier circuit 56. The
sense amplifier circuit 56 is electrically coupled to column
address latch and decoder 54 via conductive column select lines 72.
Also, sense amplifier circuit 56 is electrically coupled to row
address latch and decoder 52 via communications path 74 and to RAM
I/O circuit 58 via I/O communications path 76. Data is transferred
between RAM I/O circuit 58 and controller 42 via data
communications path 48.
[0023] Controller 42 is electrically coupled to address register 60
and control circuit 62 via memory communications path 46. Address
register 60 is electrically coupled to row address latch and
decoder 52 and column address latch and decoder 54 via row and
column address lines 78. Control circuit 62 is electrically coupled
to row address latch and decoder 52 and column address latch and
decoder 54 via control communications path 80. Also, control
circuit 62 is electrically coupled to temperature dependent voltage
source 64 via voltage source path 82.
[0024] Temperature dependent voltage source 64 includes a
temperature dependent reference circuit 84 and a regulator circuit
86. Temperature dependent reference circuit 84 is electrically
coupled to regulator circuit 86 via reference voltage path 88.
Control circuit 62 includes a delay block 90 that is electrically
coupled to regulator circuit 86 via voltage source path 82.
[0025] Address register 60 receives row and column addresses from
controller 42 via memory communications path 46. Address register
60 supplies a row address to row address latch and decoder 52 via
row and column address lines 78, and control circuit 62 supplies a
RAS signal to row address latch and decoder 52 via control
communications path 80 to latch the supplied row address into row
address latch and decoder 52. Address register 60 supplies a column
address to column address latch and decoder 54 via row and column
address lines 78, and control circuit 62 supplies a CAS signal to
column address latch and decoder 54 via control communications path
80 to latch the supplied column address into column address latch
and decoder 54.
[0026] Controller 42 and I/O circuit 58 communicate data between
controller 42 and RAM 44 via data communications path 48. I/O
circuit 58 includes a suitable number of transmitter and receiver
pairs and controller 42 includes a suitable number of transmitter
and receiver pairs. Each transmitter and receiver pair in I/O
circuit 58 corresponds to a transmitter and receiver pair in
controller 42. Data communications path 48 includes one or more
signal lines and each transmitter and receiver pair in I/O circuit
58 is electrically coupled to the corresponding transmitter and
receiver pair in controller 42 via one of the signal lines in data
communications path 48.
[0027] Sense amplifier circuit 56 includes sense amplifiers,
equalization and precharge circuits, and switches. The sense
amplifiers are differential input sense amplifiers and each sense
amplifier receives one bit line 68 at each of the two differential
inputs. One of the bit lines 68 receives a data bit from a selected
memory cell 70 and the other bit line 68 is used as a reference.
The equalization and precharge circuits equalize the voltage on bit
lines 68 connected to the same sense amplifier prior to a read or
write operation. To read a data bit, a sense amplifier amplifies
the difference between the data bit value and the reference value
and provides a sensed output value to I/O circuit 58 via I/O
communications path 76. One of the transmitter and receiver pairs
in I/O circuit 58 receives the sensed output value and provides the
sensed output value to the corresponding transmitter and receiver
pair in controller 42 via data communications path 48. To write a
data bit, one of the transmitter and receiver pairs in controller
42 provides a data bit to the corresponding transmitter and
receiver pair in I/O circuit 58 in RAM 44 via data communications
path 48. I/O circuit 58 provides the data bit to a sense amplifier
in sense amplifier circuit 56 via I/O communications path 76. I/O
circuit 58 overdrives the sense amplifier to overdrive the data bit
value onto the bit line 68 that is connected to one of the memory
cells 70 and to overdrive the inverse of the data bit value onto
the reference bit line 68. The sense amplifier writes the received
data bit value into the selected memory cell 70.
[0028] Row address latch and decoder 52 receives row addresses and
RAS signals and latches the row addresses into row address latch
and decoder 52. Row address latch and decoder 52 decodes each of
the row addresses to select a row of memory cells 70. In addition,
row address latch and decoder 52 provides sense amplifier
activation signals and equalization and precharge signals to sense
amplifier circuit 56 via communications path 74.
[0029] Column address latch and decoder 54 activates column select
lines 72 to connect sense amplifiers in sense amplifier circuit 56
to transmitter and receiver pairs in I/O circuit 58. Column address
latch and decoder 54 receives a column address and latches the
column address into column address latch and decoder 54. Column
address latch and decoder 54 decodes the column address to select
addressed column select lines 72. In addition, column address latch
and decoder 54 receives column select line activation signals from
control circuit 62 via control communications path 80. The column
select line activation signals indicate which of the addressed
column select lines 72 are to be activated by column address latch
and decoder 54. Column address latch and decoder 54 activates
column select lines 72 that are addressed by the column address and
selected for activation by the column select line activation
signals. Activated column select lines 72 are provided to sense
amplifier circuit 56 to connect sense amplifiers in sense amplifier
circuit 56 to transmitter and receiver pairs in I/O circuit 58.
[0030] Controller 42 provides addresses and control signals to
control circuit 62 via memory communications path 46. Control
circuit 62 receives the addresses and control signals from
controller 42 and provides internal control signals to read data
from or write data into the array of memory cells 50. Control
circuit 62 provides RAS signals to row address latch and decoder 52
and CAS signals to column address latch and decoder 54. Also,
control circuit 62 provides internal control signals to column
address latch and decoder 52 to selectively activate column select
lines 72.
[0031] In one embodiment, RAM 44 is a PSRAM and controller 42
provides SRAM control signals to control circuit 62. The SRAM
control signals do not include DRAM control signals, such as RAS
and CAS signals, and control circuit 62 provides the DRAM control
signals in response to the SRAM control signals. The DRAM control
signals include timing constraints to read data from or write data
into the array of memory cells 50. These timing constraints include
timing parameters such as the minimum amount of time that the RAS
signal is active (tRAS), the minimum amount of time that the RAS
signal is inactive, referred to as RAS precharge time (tRP), the
minimum amount of time for a RAS cycle (tRC), and the minimum
amount of time to recover from a write operation, referred to as
write recovery time (tWR).
[0032] Delay block 90 includes delay chains that are used to
provide internal control signals and to meet the timing constraints
of the internal control signals. The speed of each of the delay
chains in delay block 90 varies with temperature due to device
characteristics. As the temperature increases, the speed of each of
the delay chains decreases and as the temperature decreases, the
speed of each of the delay chains increases. Also, the speed of
each of the delay chains is dependent on the supply voltage
provided to delay block 90. As the supply voltage increases, the
speed of each of the delay chains increases and as the supply
voltage decreases, the speed of each of the delay chains decreases.
To provide constant delay times over temperature, the supply
voltage provided to delay block 90 increases at higher temperatures
and decreases at lower temperatures.
[0033] Temperature dependent voltage source 64 provides a
temperature dependent output voltage VOUT to delay block 90 via
voltage source path 82. The temperature dependent output voltage
VOUT is used as the supply voltage for the delay chains in delay
block 90. As the temperature increases, the temperature dependent
output voltage VOUT increases and as the temperature decreases, the
temperature dependent output voltage VOUT decreases.
[0034] Temperature dependent reference circuit 84 is similar to
temperature dependent reference circuit 22 (shown in FIG. 1).
Temperature dependent reference circuit 84 provides a temperature
dependent reference voltage VREF to regulator circuit 86 via
reference voltage path 88. Temperature dependent reference circuit
84 includes circuitry that provides a temperature dependent
current, a constant current, and the temperature dependent
reference voltage VREF based on the constant current and the
temperature dependent current. The temperature dependent reference
voltage VREF has a voltage versus temperature slope that is
established via one part of the temperature dependent reference
circuit 84 and a voltage level that is established via another part
of the temperature dependent reference circuit 84. The voltage
versus temperature slope and the voltage level of the temperature
dependent reference voltage VREF are individually established
parameters of the temperature dependent reference voltage VREF. As
the temperature increases, the temperature dependent reference
voltage VREF increases and as the temperature decreases, the
temperature dependent reference voltage VREF decreases.
[0035] Regulator circuit 86 receives the temperature dependent
reference voltage VREF via reference voltage path 88 and provides
the temperature dependent output voltage VOUT to delay block 90 via
voltage source path 82. The temperature dependent output voltage
VOUT is based on the temperature dependent reference voltage VREF.
As the temperature increases, the temperature dependent reference
voltage VREF and the temperature dependent output voltage VOUT
increase. As the temperature decreases, the temperature dependent
reference voltage VREF and the temperature dependent output voltage
VOUT decrease. The speed of the delay chains in delay block 90 can
be made constant over temperature, i.e., independent of
temperature, using the temperature dependent reference voltage VREF
to provide a temperature dependent output voltage VOUT as the
supply voltage for delay block 90.
[0036] During a read operation, control circuit 62 receives read
control signals and address register 60 receives the row address of
a selected memory cell or cells 70. The row address is supplied
from address register 60 to row address latch and decoder 52 and
latched into row address latch and decoder 52 by control circuit 62
that provides a RAS signal. Row address latch and decoder 52
decodes the row address and activates the selected word line 66. As
the selected word line 66 is activated, the value stored in each
memory cell 70 coupled to the selected word line 66 is passed to
the respective bit line 68. The bit value stored at a memory cell
70 is detected by a sense amplifier that is electrically coupled to
the respective bit line 68.
[0037] Next, control circuit 62 and address register 60 receive the
column address of the selected memory cell or cells 70. The column
address is supplied from address register 60 to column address
latch and decoder 54 and latched into column address latch and
decoder 54 by control circuit 62 that provides a CAS signal. The
column address latch and decoder 54 decodes the column address to
select column select lines 72. Control circuit 62 provides internal
control signals to column address latch and decoder 54 to
selectively activate column select lines 72 and connect selected
sense amplifiers to transmitter and receiver pairs in I/O circuit
58. Sensed output values are provided to transmitter and receiver
pairs in I/O circuit 58 and to the corresponding transmitter and
receiver pairs in controller 42 via data communications path
48.
[0038] During a write operation, data to be stored in the array of
memory cells 50 is supplied from transmitter and receiver pairs in
controller 42 to transmitter and receiver pairs in I/O circuit 58
via data communications path 48. Control circuit 62 receives write
control signals and address register 60 receives the row address of
a selected memory cell or cells 70. The row address is supplied
from address register 60 to row address latch and decoder 52 and
latched into row address latch and decoder 52 by control circuit 62
that provides a RAS signal. The row address latch and decoder 52
decodes the row address and activates the selected word line 66. As
the selected word line 66 is activated, the value stored in each
memory cell 70 coupled to the selected word line 66 is passed to
the respective bit line 68 and the sense amplifier that is
electrically coupled to the respective bit line 68.
[0039] Next, control circuit 62 and address register 60 receive the
column address of the selected memory cell or cells 70. Address
register 60 supplies the column address to column address latch and
decoder 54 and the column address is latched into column address
latch and decoder 54 by control circuit 62 via a CAS signal. Column
address latch and decoder 54 receives column select line activation
signals from control circuit 62 and activates selected column
select lines 72 to connect sense amplifiers in sense amplifier
circuit 56 to transmitter and receiver pairs in I/O circuit 58. I/O
circuit 58 passes data from controller 42 to the sense amplifiers
and overdrives the sense amplifiers to write data to the selected
memory cell or cells 70 via bit lines 68.
[0040] FIG. 3 is a diagram illustrating one embodiment of a memory
cell 70 in the array of memory cells 50. Memory cell 70 includes a
transistor 92 and a capacitor 94. The gate of transistor 92 is
electrically coupled to word line 66. One side of the drain-source
path of transistor 92 is electrically coupled to bit line 68 and
the other side of the drain-source path is electrically coupled to
one side of capacitor 94. The other side of capacitor 94 is
electrically coupled to a reference 96, such as one-half the supply
voltage. Capacitor 94 is charged and discharged to represent a
logic 0 or a logic 1.
[0041] During a read operation, word line 66 is activated to turn
on transistor 92 and the value stored on capacitor 94 is read by a
sense amplifier via bit line 68. During a write operation, word
line 66 is activated to turn on transistor 92 to access capacitor
94. The sense amplifier connected to bit line 68 is overdriven to
write a data value on capacitor 94 via bit line 68 and transistor
92.
[0042] A read operation on memory cell 70 is a destructive read
operation. After each read operation, capacitor 94 is recharged or
discharged to the data value that was just read. In addition, even
without read operations, the charge on capacitor 94 discharges over
time. To retain a stored value, memory cell 70 is refreshed
periodically by reading and/or writing memory cell 70. All memory
cells 70 in the array of memory cells 50 are periodically refreshed
to maintain their values.
[0043] FIG. 4 is a diagram illustrating one embodiment of a
temperature dependent reference circuit 100. Temperature dependent
reference circuit 100 is similar to temperature dependent reference
circuit 22 (shown in FIG. 1) and temperature dependent reference
circuit 84 (shown in FIG. 2). Temperature dependent reference
circuit 100 provides a temperature dependent reference voltage VREF
at 102. As the temperature increases, the temperature dependent
reference voltage VREF at 102 increases, and as the temperature
decreases, the temperature dependent reference voltage VREF at 102
decreases.
[0044] Temperature dependent reference circuit 100 includes a
differential amplifier 104, a first p-channel metal oxide
semiconductor (PMOS) transistor 106, a capacitor 108, a first
resistor 110, a diode 112, a second resistor 114, a second PMOS
transistor 116, and a third resistor 118. The negative input of
differential amplifier 104 receives input voltage VIN at 120 and
the output of differential amplifier 104 is electrically coupled at
122 to one side of capacitor 108, the gate of first PMOS transistor
106, and the gate of second PMOS transistor 116. The other side of
capacitor 108 is electrically coupled to a reference, such as
ground, at 124.
[0045] One side of the drain-source path of first PMOS transistor
106 is electrically coupled at 126 to first resistor 110, second
resistor 114, and the positive input of differential amplifier 104.
The other side of second resistor 114 is electrically coupled at
128 to a reference, such as ground, and the other side of first
resistor 110 is electrically coupled at 130 to the anode of diode
112. The cathode of diode 112 is electrically coupled to a
reference, such as ground, at 132.
[0046] The other side of the drain-source path of first PMOS
transistor 106 is electrically coupled to a power supply voltage
VDD at 134. One side of second PMOS transistor 116 is electrically
coupled to the power supply voltage VDD at 134. The other side of
the drain-source path of second PMOS transistor 116 is electrically
coupled at 102 to third resistor 118 and the other side of third
resistor 118 is electrically coupled to a reference, such as
ground, at 136.
[0047] Differential amplifier 104 receives input voltage VIN at 120
and provides an output voltage at 122 that turns on first PMOS
transistor 106 and second PMOS transistor 116. The input voltage
VIN is a substantially constant voltage. Current I1 passes through
first PMOS transistor 106 and is divided into a substantially
constant current ICC that passes through second resistor 114 and a
temperature dependent current ITD that passes through the series
combination of first resistor 110 and diode 112. The voltage at the
drain of first PMOS transistor 106 and at the positive input of
differential amplifier 104 is regulated to substantially the value
of the constant input voltage VIN by differential amplifier 104.
Capacitor 108 stabilizes the feedback loop from the output of
differential amplifier 104 to the gate of first PMOS transistor 106
and back to the positive input of differential amplifier 104.
[0048] The current I1 is equal to the sum of the constant current
ICC and the temperature dependent current ITD. Second resistor 114
is part of a constant-current source that provides constant current
ICC. The constant current ICC is equal to the value of the input
voltage VIN divided by the resistance value R2 of second resistor
114. First resistor 110 and diode 112 are part of a temperature
dependent current source that provides temperature dependent
current ITD. The temperature dependent current ITD is equal to the
value of the input voltage VIN minus the temperature dependent
voltage VBE across diode 112, divided by the resistance value R1 of
first resistor 110. As the temperature increases, the voltage VBE
across diode 112 decreases and the temperature dependent current
ITD increases. As the temperature decreases, the voltage VBE across
diode 112 increases and the temperature dependent current ITD
decreases.
[0049] The current I1 through first PMOS transistor 106 is mirrored
as current I2 through second PMOS transistor 116. Current I2 is
substantially equal to current I1 and current I2 passes through
second PMOS transistor 116 and third resistor 118 to provide the
temperature dependent output voltage VREF at 102. With the
reference at 136 at ground, the current I2 times the resistance
value R3 of third resistor 118 equals the temperature dependent
output voltage VREF at 102.
[0050] In operation, as the temperature increases, the voltage VBE
across diode 112 decreases and the temperature dependent current
ITD increases. This increases current I1 and current 12, which
increases the temperature dependent output voltage VREF at 102. As
the temperature decreases, the voltage VBE across diode 112
increases and the temperature dependent current ITD decreases. This
decreases current I1 and current I2, which decreases temperature
dependent output voltage VREF at 102.
[0051] The temperature dependent output voltage VREF at 102 is
determined as follows in Equation I: VREF = ( VIN R .times. .times.
2 + VIN - VBE R .times. .times. 1 ) * R .times. .times. 3 Equation
.times. .times. I ##EQU1##
[0052] Equation I can be rearranged into Equation II: VREF = ( ( R
.times. .times. 1 + R .times. .times. 2 R .times. .times. 1 * R
.times. .times. 2 ) * R .times. .times. 3 * VIN ) - ( R .times.
.times. 3 R .times. .times. 1 * VBE ) Equation .times. .times. II
##EQU2##
[0053] In Equation II, temperature dependent reference voltage VREF
includes a temperature independent part and a temperature dependent
part. The temperature independent part comes before the minus sign
and is based on the resistance values R1, R2, and R3 and the input
voltage VIN. The temperature dependent part follows the minus sign
and is based on the resistance values R3 and R1 and the temperature
dependent voltage VBE across diode 112. The temperature dependent
voltage VBE across diode 112 is determined roughly as follows in
Equation III: VBE=0.662-0.0025(T-25) Equation III
[0054] where T is the temperature in degrees Celsius (C.).
[0055] From Equation III, the temperature dependent voltage VBE
across diode 112 changes at a rate of 2.5 millivolts (mV) per
degrees C. In Equation II, the temperature dependent voltage VBE is
multiplied by resistance value R3 of third resistor 118 and divided
by the resistance value R1 of first resistor 110. The voltage
versus temperature slope of the temperature dependent reference
voltage VREF is established by setting the resistance values R1 and
R3.
[0056] For example, to change the temperature dependent reference
voltage VREF 150 mV over a 140 degree C. temperature range of -30
degrees C. to 110 degrees C., the temperature dependent part of
temperature dependent reference voltage VREF is as follows in
Equation IV: 2.5 .times. mV .degree.C * R .times. .times. 3 R
.times. .times. 1 = 150 .times. mV 140 .times. .degree.C = 1.071
.times. mV .degree.C Equation .times. .times. IV ##EQU3##
[0057] Setting the resistance value R1 of first resistor 110 equal
to 1 mega Ohm (MOhm) and solving for the resistance value R3 of
third resistor 118, results in a resistance value R3 of 0.429
MOhms. If the resistance value R1 of first resistor 110 is
constant, the voltage versus temperature slope of the temperature
dependent reference voltage VREF is established by setting the
resistance value R3 of third resistor 118.
[0058] To further the example, input voltage VIN is set to 1.2
volts and Equation III is combined with Equation II. Substituting
in a resistance value of 1 MOhm for resistance value R1 and a
resistance value of 0.429 MOhms for resistance value R3, results in
Equation V. VREF = 0.514 * ( 1 + R .times. .times. 2 R .times.
.times. 2 ) - 0.311 + ( .001071 * T ) Equation .times. .times. V
##EQU4##
[0059] Setting the temperature dependent reference voltage VREF to
0.9 volts and the temperature to 30 degrees C. and solving for the
resistance value R2 of second resistor 114, results in a resistance
value R2 of 0.773 MOhms. At a given temperature, the voltage level
of the temperature dependent reference voltage VREF is established
by setting the resistance value R2 of second resistor 114.
Substituting the resistance value R2 of 0.773 MOhms back into
Equation V results in Equation VI. VREF=0.868+(0.001071*T) Equation
VI
[0060] The temperature dependent reference voltage VREF in Equation
VI is equal to 0.9 volts at 30 degrees C. and has a voltage versus
temperature slope of 150 mV over 140 degrees C., between -30
degrees C. and 110 degrees C.
[0061] Second resistor 114 and third resistor 118 are variable
resistors configured to establish the voltage level and the voltage
versus temperature slope of the temperature dependent reference
voltage VREF. With the resistance value R1 constant, the resistance
value R3 of third resistor 118 establishes the slope of the
temperature dependent reference voltage VREF, which also changes
the voltage level of the temperature dependent reference voltage
VREF. The resistance value R2 of second resistor 114 is then
configured to establish the voltage level of the temperature
dependent reference voltage VREF. The voltage versus temperature
slope and the voltage level of the temperature dependent reference
voltage VREF are established independently via third resistor 118
and second resistor 114.
[0062] In one embodiment, second resistor 114 includes multiple
resistors connected in series and each of the multiple resistors
can be selected or shorted to provide resistance value R2. In one
embodiment, third resistor 118 includes multiple resistors
connected in series and each of the multiple resistors can be
selected or shorted to provide resistance value R3. In one
embodiment, second resistor 114 is a digitally variable resistor.
In one embodiment, third resistor 118 is a digitally variable
resistor. In other embodiments, first resistor 110 can be a
variable resistor.
[0063] FIG. 5 is a diagram illustrating one embodiment of a
regulator circuit 200. Regulator circuit 200 is similar to
regulator circuit 86 (shown in FIG. 2). Regulator circuit 200
receives the temperature dependent reference voltage VREF at 202
and provides the temperature dependent output voltage VOUT at 204.
The temperature dependent output voltage VOUT at 204 is based on
the temperature dependent reference voltage VREF at 202. As the
temperature increases, the temperature dependent reference voltage
VREF at 202 increases and the temperature dependent output voltage
VOUT at 204 increases. As the temperature decreases, the
temperature dependent reference voltage VREF at 202 decreases and
the temperature dependent output voltage VOUT at 204 decreases.
[0064] Regulator circuit 200 includes an input circuit 206 and an
output circuit 208. Input circuit 206 is a differential amplifier
including a first n-channel metal oxide semiconductor (NMOS)
transistor 210, a second NMOS transistor 212, a third NMOS
transistor 214, a first PMOS transistor 216, and a second PMOS
transistor 218. The first NMOS transistor 210 and the second NMOS
transistor 212 are input transistors and the third NMOS transistor
214 provides a current source for the differential amplifier. The
first PMOS transistor 216 and the second PMOS transistor 218 are
arranged as a current mirror.
[0065] The gate of the first NMOS transistor 210 receives the
temperature dependent reference voltage VREF at 202 and one side of
the drain-source path of first NMOS transistor 210 is electrically
coupled at 220 to one side of the drain-source path of second NMOS
transistor 212 and to one side of the drain-source path of third
NMOS transistor 214. The other side of the drain-source path of
third NMOS transistor 214 is electrically coupled to a reference,
such as ground, at 222. The gate of third NMOS transistor 214
receives a current source voltage VC1 at 224 that turns on third
NMOS transistor 214 to provide a current source for the
differential amplifier.
[0066] The other side of the drain-source path of first NMOS
transistor 210 is electrically coupled at 226 to one side of the
drain-source path of first PMOS transistor 216 and to the gates of
first PMOS transistor 216 and second PMOS transistor 218. The other
side of the drain-source path of first PMOS transistor 216 is
electrically coupled to a power supply voltage VPP at 228. One side
of the drain-source path of second PMOS transistor 218 is
electrically coupled to a power supply voltage VPP at 228. The
other side of the drain-source path of second PMOS transistor 218
is electrically coupled at 230 to the other side of the
drain-source path of second NMOS transistor 212 and to output
circuit 208. The gate of the second NMOS transistor 212 is
electrically coupled at 232 to output circuit 208.
[0067] Output circuit 208 includes a third PMOS transistor 234, a
fourth PMOS transistor 236, a fourth NMOS transistor 238, a fifth
NMOS transistor 240, a first resistor 242, and a second resistor
244. The gate of the third PMOS transistor 234 is electrically
coupled at 230 to the drain-source path of second PMOS transistor
218 and the drain-source path of second NMOS transistor 212. One
side of the drain-source path of the third PMOS transistor 234 is
electrically coupled at 246 to one side of the drain source path of
fourth NMOS transistor 238 and the gate of fourth PMOS transistor
236. The other side of the drain-source path of fourth NMOS
transistor 238 is electrically coupled to a reference, such as
ground, at 248. The gate of fourth NMOS transistor 238 receives a
current source voltage VC2 at 250 that turns on fourth NMOS
transistor 238 to provide a current source. The other side of the
drain-source path of third PMOS transistor 234 is electrically
coupled to the power supply voltage VPP at 228. One side of the
drain source path of fourth PMOS transistor 236 is electrically
coupled to the power supply voltage VPP at 228.
[0068] The other side of the drain-source path of the fourth PMOS
transistor 236 is electrically coupled at 204 to one side of first
resistor 242. The other side of first resistor 242 is electrically
coupled at 232 to the gate of second NMOS transistor 212 and one
side of second resistor 244. The other side of second resistor 244
is electrically coupled at 252 to one side of the drain-source path
of fifth NMOS transistor 240. The other side of the drain-source
path of fifth NMOS transistor 240 is electrically coupled to a
reference, such as ground, at 254. The gate of fifth NMOS
transistor 240 receives a current source voltage VC3 at 256 that
turns on fifth NMOS transistor 240 to provide a current source. In
one embodiment, current source voltages VC1, VC2, and VC3 are
provided by the same voltage supply and are the same voltage
value.
[0069] First NMOS transistor 210 receives the temperature dependent
reference voltage VREF at 202 and is biased to pass a first current
from first PMOS transistor 216 to third NMOS transistor 214 and the
reference at 222. The current mirror's second PMOS transistor 218
is biased to pass a second current that mirrors the first current.
The output circuit 208 responds to the voltage at 230 to provide
the temperature dependent output voltage VOUT and stabilize the
voltage at the gate of second NMOS transistor 212 to substantially
the voltage value of the temperature dependent reference voltage
VREF.
[0070] If second NMOS transistor 212 is biased to pass less current
than first NMOS transistor 210, the voltage at 230 increases and
third PMOS transistor 234 is biased to pass less current. Fourth
NMOS transistor 238 pulls the voltage at 246 lower, which biases
fourth PMOS transistor 236 to pass more current. Current that
passes through fourth PMOS transistor 236 flows through first and
second resistors 242 and 244 and fifth NMOS transistor 240 to the
reference at 254. A larger current through fourth PMOS transistor
236 raises the temperature dependent output voltage VOUT and the
gate voltage of second NMOS transistor 212, between the first and
second resistors 242 and 244. This biases second NMOS transistor
212 to pass more current and lower the voltage at 230. The lower
voltage at 230 biases third PMOS transistor 234 to pass more
current, which raises the voltage at 246 and biases fourth PMOS
transistor 236 to pass less current. The regulator circuit 200
stabilizes with the gate voltage of second NMOS transistor 212
substantially equal to the temperature dependent reference voltage
VREF at 202.
[0071] If second NMOS transistor 212 is biased to pass more current
than first NMOS transistor 210, the voltage at 230 decreases and
third PMOS transistor 234 is biased to pass more current. The
voltage at 246 increases and fourth PMOS transistor 236 is biased
to pass less current. The smaller current through fourth PMOS
transistor 236 lowers the temperature dependent output voltage VOUT
and the gate voltage of second NMOS transistor 212. Second NMOS
transistor 212 is biased to pass less current, which raises the
voltage at 230. The higher voltage at 230 biases third PMOS
transistor 234 to pass less current, which lowers the voltage at
246 and fourth PMOS transistor 236 is biased to pass more current.
The regulator circuit 200 stabilizes with the gate voltage of
second NMOS transistor 212 substantially equal to the temperature
dependent reference voltage VREF at 202.
[0072] In one embodiment, the resistance value of first resistor
242 is equal to the resistance value of second resistor 244 and the
temperature dependent output voltage VOUT is substantially twice
the temperature dependent reference voltage VREF. In one
embodiment, temperature dependent reference circuit 100 of FIG. 4
receives a power supply voltage VDD of 1.8 volts that is boosted to
provide a power supply voltage VPP of 2.9 volts to regulator
circuit 200. In one embodiment, temperature dependent reference
circuit 100 provides a temperature dependent reference voltage VREF
that ranges from 0.85-1.00 volt and regulator circuit 200 provides
a temperature dependent output voltage VOUT that ranges from
1.7-2.0 volts.
[0073] FIG. 6 is a diagram illustrating one embodiment of a
temperature dependent reference circuit 300. Temperature dependent
reference circuit 300 is similar to temperature dependent reference
circuit 22 (shown in FIG. 1) and temperature dependent reference
circuit 84 (shown in FIG. 2). Temperature dependent reference
circuit 300 provides a temperature dependent reference voltage VREF
at 302. As the temperature increases, the temperature dependent
reference voltage VREF at 302 increases, and as the temperature
decreases, the temperature dependent reference voltage VREF at 302
decreases.
[0074] Temperature dependent reference circuit 300 includes a
bandgap reference circuit 304, a current mirror circuit 306, a
differential amplifier 308, a first PMOS transistor 310, a
capacitor 312, a first resistor 314, a second PMOS transistor 316,
and a second resistor 318. Bandgap reference circuit 304 provides a
constant, temperature independent input voltage VIN at 320 to the
negative input of differential amplifier 308. The output of
differential amplifier 308 is electrically coupled at 322 to one
side of capacitor 312, the gate of first PMOS transistor 310, and
the gate of second PMOS transistor 316. The other side of capacitor
312 is electrically coupled to a reference, such as ground, at
324.
[0075] One side of the drain-source path of first PMOS transistor
310 is electrically coupled at 326 to current mirror circuit 306,
first resistor 314, and the positive input of differential
amplifier 308. The other side of first resistor 314 is electrically
coupled at 328 to a reference, such as ground. The other side of
the drain-source path of first PMOS transistor 310 is electrically
coupled to a power supply voltage VDD at 330. One side of second
PMOS transistor 316 is electrically coupled to the power supply
voltage VDD at 330. The other side of the drain-source path of
second PMOS transistor 316 is electrically coupled at 302 to second
resistor 318 and the other side of second resistor 318 is
electrically coupled to a reference, such as ground, at 332.
[0076] Bandgap reference circuit 304 includes a first bandgap
circuit PMOS transistor 334, a second bandgap circuit PMOS
transistor 336, a first bandgap circuit NMOS transistor 338, a
second bandgap circuit NMOS transistor 340, a first diode 342, a
second diode 344, and a first bandgap circuit resistor 346. Bandgap
reference circuit 304 also includes a third bandgap circuit PMOS
transistor 348, a third diode 350, and a second bandgap circuit
resistor 352.
[0077] First bandgap circuit PMOS transistor 334 and second bandgap
circuit PMOS transistor 336 are arranged as a current mirror. The
gate of first bandgap circuit PMOS transistor 334 is electrically
coupled at 354 to the gate and one side of the drain-source path of
second bandgap circuit PMOS transistor 336 and to one side of the
drain-source path of second bandgap circuit NMOS transistor 340.
The other side of the drain-source path of second bandgap circuit
PMOS transistor 336 is electrically coupled to power supply voltage
VDD at 356. One side of the drain-source path of first bandgap
circuit PMOS transistor 334 is electrically coupled to the power
supply voltage VDD at 356. The other side of the drain-source path
of first bandgap circuit PMOS transistor 334 is electrically
coupled at 358 to the gate and one side of the drain-source path of
first bandgap circuit NMOS transistor 338 and to the gate of second
bandgap circuit NMOS transistor 340.
[0078] The other side of the drain-source path of first bandgap
circuit NMOS transistor 338 is electrically coupled at 360 to the
anode of first diode 342. The other side of the drain-source path
of second bandgap circuit NMOS transistor 340 is electrically
coupled at 362 to one side of first bandgap circuit resistor 346.
The other side of first bandgap circuit resistor 346 is
electrically coupled at 364 to the anode of second diode 344. The
cathode of first diode 342 is electrically coupled at 366 to the
cathode of second diode 344 and to a reference such as ground.
[0079] Third bandgap circuit PMOS transistor 348 is arranged in the
current mirror including first bandgap circuit PMOS transistor 334
and second bandgap circuit PMOS transistor 336. The gate of third
bandgap circuit PMOS transistor 348 is electrically coupled at 354
to the gates of first bandgap circuit PMOS transistor 334 and
second bandgap circuit PMOS transistor 336. Also, one side of the
drain-source path of third bandgap circuit PMOS transistor 348 is
electrically coupled to the power supply voltage VDD at 356. The
other side of the drain-source path of third bandgap circuit PMOS
transistor 348 is electrically coupled at 320 to one side of second
bandgap circuit resistor 352 and the negative input of differential
amplifier 308. The other side of second bandgap circuit resistor
352 is electrically coupled at 368 to the anode of third diode 350
and the cathode of third diode 350 is electrically coupled to a
reference such as ground, at 370.
[0080] The current mirror circuit 306 includes a mirror circuit
PMOS transistor 372, a first mirror circuit NMOS transistor 374,
and a second mirror circuit NMOS transistor 376. Mirror circuit
PMOS transistor 372 is arranged in the current mirror including
first bandgap circuit PMOS transistor 334 and second bandgap
circuit PMOS transistor 336. The gate of mirror circuit PMOS
transistor 372 is electrically coupled at 354 to the gates of first
bandgap circuit PMOS transistor 334 and second bandgap circuit PMOS
transistor 336. Also, one side of the drain-source path of mirror
circuit PMOS transistor 372 is electrically coupled to the power
supply voltage VDD at 356.
[0081] The other side of the drain-source path of mirror circuit
PMOS transistor 372 is electrically coupled at 378 to the gate and
one side of the drain-source path of first mirror circuit NMOS
transistor 374 and to the gate of second mirror circuit NMOS
transistor 376. The other side of the drain-source path of first
mirror circuit NMOS transistor 374 is electrically coupled to a
reference, such as ground, at 380. One side of the drain-source
path of second mirror circuit NMOS transistor 376 is electrically
coupled to a reference, such as ground, at 382 and the other side
of the drain-source path of second mirror circuit NMOS transistor
376 is electrically coupled at 326 to first PMOS transistor 310,
first resistor 314, and the positive input of differential
amplifier 308.
[0082] In bandgap reference circuit 304, second bandgap circuit
PMOS transistor 336 is biased to pass a bandgap reference current
IBGR from the power supply voltage VDD to second bandgap circuit
NMOS transistor 340. The bandgap reference current IBGR flows
through second bandgap circuit NMOS transistor 340 and first
bandgap circuit resistor 346 and second diode 344 to the reference
at 366. First bandgap circuit PMOS transistor 334 is biased to pass
a mirror current that is substantially equal in value to the
bandgap reference current IBGR. The mirror current flows from the
power supply voltage VDD and through first bandgap circuit PMOS
transistor 334 and first bandgap circuit NMOS transistor 338 and
first diode 342 to the reference at 366.
[0083] The bandgap reference current IBGR is a temperature
dependent current that increases as the temperature increases and
decreases as the temperature decreases. The bandgap reference
current IBGR changes as a function of V=kT/q, where k is
Boltzmann's constant, T is temperature, and q is the charge of an
electron. As the temperature increases, the voltage across second
diode 344 decreases, which increases the bandgap reference current
IBGR. As the temperature decreases, the voltage across second diode
344 increases, which decreases the bandgap reference current
IBGR.
[0084] Third bandgap circuit PMOS transistor 348 is biased to pass
a mirror current that is substantially equal in value to the
bandgap reference current IBGR. The mirror current flows from the
power supply voltage VDD and through third bandgap circuit PMOS
transistor 348 and second bandgap circuit resistor 352 and third
diode 350. The first diode 342, second diode 344, and third diode
350 are thermally matched to have substantially the same voltage
versus temperature slopes and the input voltage VIN at 320 is
substantially constant over temperature. As the temperature
increases, a decrease in the voltage across third diode 350 is
offset by the increase in the bandgap reference current IBGR and
increase in the voltage across second bandgap circuit resistor 352.
As the temperature decreases, an increase in the voltage across
third diode 350 is offset by a decrease in the bandgap reference
current IBGR and decrease in the voltage across second bandgap
circuit resistor 352. Bandgap reference circuit 304 provides a
constant, temperature independent input voltage VIN at 320 to the
negative input of differential amplifier 308.
[0085] Current mirror circuit 306 provides a temperature dependent
current ITD via second mirror circuit NMOS transistor 376. Mirror
circuit PMOS transistor 372 is biased to pass a mirror current that
is substantially equal in value to the bandgap reference current
IBGR. The mirror current flows from the power supply voltage VDD
and through mirror circuit PMOS transistor 372 and first mirror
circuit NMOS transistor 374 to the reference at 380. The current
through first mirror circuit NMOS transistor 374 is mirrored
through second mirror circuit NMOS transistor 376. The temperature
dependent current ITD is directly related to the bandgap reference
current IBGR and increases as the temperature increases and
decreases as the temperature decreases.
[0086] Differential amplifier 308 receives input voltage VIN at 320
and provides an output voltage at 322 that turns on first PMOS
transistor 310 and second PMOS transistor 316. Current I1 passes
through first PMOS transistor 310 and is divided into a
substantially constant current ICC that passes through first
resistor 314 and temperature dependent current ITD. The voltage at
the drain of first PMOS transistor 310 and at the positive input of
differential amplifier 308 is regulated to substantially the value
of the constant input voltage VIN by differential amplifier 308.
Capacitor 312 stabilizes the feedback loop from the output of
differential amplifier 308 to the gate of first PMOS transistor 310
and back to the positive input of differential amplifier 308.
[0087] The current I1 is equal to the sum of the constant current
ICC and the temperature dependent current ITD. First resistor 314
is part of a constant current source that provides constant current
ICC. The constant current ICC is equal to the value of the input
voltage VIN divided by the resistance value of first resistor 314.
Bandgap reference circuit 304 and current mirror circuit 306 are
part of a temperature dependent current source that provides
temperature dependent current ITD. As the temperature increases,
the temperature dependent current ITD increases and, as the
temperature decreases, the temperature dependent current ITD
decreases.
[0088] The current I1 through first PMOS transistor 310 is mirrored
as current I2 through second PMOS transistor 316. Current I2 is
substantially equal to current I1 and current I2 passes through
second PMOS transistor 316 and second resistor 318 to provide the
temperature dependent output voltage VREF at 302. With the
reference at 332 at ground, the current I2 times the resistance
value of second resistor 318 equals the temperature dependent
output voltage VREF at 302.
[0089] In operation, as the temperature increases, the temperature
dependent current ITD increases. This increases the currents I1 and
I2 and the temperature dependent output voltage VREF at 302. As the
temperature decreases, the temperature dependent current ITD
decreases. This decreases the currents I1 and I2 and the
temperature dependent output voltage VREF at 302. The voltage
versus temperature slope of the temperature dependent reference
voltage VREF is established by setting the resistance value of
second resistor 318. The voltage level of the temperature dependent
reference voltage VREF is established by setting the resistance
value of first resistor 314.
[0090] First resistor 314 and second resistor 318 are variable
resistors configured to establish the voltage level and the voltage
versus temperature slope of the temperature dependent reference
voltage VREF. The resistance value of second resistor 318
establishes the slope of the temperature dependent reference
voltage VREF, which also changes the voltage level of the
temperature dependent reference voltage VREF. The resistance value
of first resistor 314 is then configured to establish the voltage
level of the temperature dependent reference voltage VREF. The
voltage versus temperature slope and the voltage level of the
temperature dependent reference voltage VREF are established
independently via second resistor 318 and first resistor 314.
[0091] In one embodiment, first resistor 314 includes multiple
resistors connected in series and each of the multiple resistors
can be selected or shorted to provide a resistance value. In one
embodiment, second resistor 318 includes multiple resistors
connected in series and each of the multiple resistors can be
selected or shorted to provide a resistance value. In one
embodiment, first resistor 314 is a digitally variable resistor. In
one embodiment, second resistor 318 is a digitally variable
resistor.
[0092] The slope and voltage level of the temperature dependent
reference voltage VREF can be established to accommodate circuit
needs. In one embodiment, the slope and voltage level of the
temperature dependent reference voltage VREF is established to
provide a regulated, temperature dependent output voltage VOUT that
is used as a supply voltage for delay chains in a RAM. The speed of
the delay chains can be made constant over temperature, i.e.,
temperature independent, via the temperature dependent output
voltage VOUT to help ensure that the RAM functions reliably over
temperature. The voltage level of the temperature dependent
reference voltage VREF can be established independently to conserve
power, while the slope of the temperature dependent reference
voltage VREF can be established to provide temperature independent
delay chains.
[0093] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that a variety of alternate and/or equivalent
implementations may be substituted for the specific embodiments
shown and described without departing from the scope of the present
invention. This application is intended to cover any adaptations or
variations of the specific embodiments discussed herein. Therefore,
it is intended that this invention be limited only by the claims
and the equivalents thereof.
* * * * *