U.S. patent application number 11/099834 was filed with the patent office on 2006-10-12 for alternative methodology for defect simulation and system.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Chung-Min Fu, Jui-Jung Yan, Ricky Yang.
Application Number | 20060230371 11/099834 |
Document ID | / |
Family ID | 37064035 |
Filed Date | 2006-10-12 |
United States Patent
Application |
20060230371 |
Kind Code |
A1 |
Yan; Jui-Jung ; et
al. |
October 12, 2006 |
Alternative methodology for defect simulation and system
Abstract
A system for defect simulation is provided. A defect layout
generator generates a defect layout comprising a given number of
spot defects of a given size. A processor first compares the defect
layout and a provided circuit layout comprising a plurality of
conductive regions. The processor further determines whether the
spot defects are located on the conductive regions, and determines
whether short-circuits and/or open circuits are caused by the spot
defects in the conductive regions.
Inventors: |
Yan; Jui-Jung; (Hsin-Chu
city, TW) ; Fu; Chung-Min; (Chungli City, TW)
; Yang; Ricky; (Hsinchu City, TW) |
Correspondence
Address: |
THOMAS, KAYDEN, HORSTEMEYER & RISLEY, LLP
100 GALLERIA PARKWAY, NW
STE 1750
ATLANTA
GA
30339-5948
US
|
Assignee: |
Taiwan Semiconductor Manufacturing
Co., Ltd.
|
Family ID: |
37064035 |
Appl. No.: |
11/099834 |
Filed: |
April 6, 2005 |
Current U.S.
Class: |
716/112 |
Current CPC
Class: |
G06F 30/398
20200101 |
Class at
Publication: |
716/005 |
International
Class: |
G06F 17/50 20060101
G06F017/50; G06F 9/45 20060101 G06F009/45 |
Claims
1. A method for defect simulation, comprising: providing a defect
layout comprising a given number of spot defects of one or more
given sizes; providing a circuit layout comprising a plurality of
conductive regions; comparing the defect layout and the circuit
layout; and determining whether at least one spot defect is located
on the conductive regions.
2. The method of claim 1, further comprising: providing a defect
layout database, wherein said defect layout is selected from said
defect layout database.
3. The method of claim 2, wherein the circuit layout comes from a
design layout database, and wherein said defect layout database and
said design layout database have the same format.
4. The method of claim 1, further comprising repeating the steps
with a different defect layout.
5. The method of claim 1, wherein the locations of the spot defects
are determined randomly or by a given rule.
6. The method of claim 1, wherein the number of the spot defects is
user-defined.
7. The method of claim 1, wherein the one or more sizes of the spot
defect are user-defined.
8. The method of claim 1, further determining whether at least one
spot defect causes a short-circuit between conductive regions.
9. The method of claim 1, further determining whether at least one
spot defect causes an open-circuit in the conductive region.
10. The method of claim 1, further estimating susceptibility of the
circuit layout to the defects of the defect layout.
11. The method of claim 1, further estimating a manufacturing yield
of the circuit layout.
12. A system for defect simulation, comprising: a defect layout
generator generating a defect layout comprising a given number of
spot defects of one or more given sizes; and a processor comparing
the defect layout and a provided circuit layout comprising a
plurality of conductive regions, and determining whether at least
one spot defect locates on the conductive region.
13. The system of claim 12, further comprising a defect layout
database including a plurality of defect layouts.
14. The system of claim 13, wherein the circuit layout is provided
from a design layout database, and wherein said defect layout
database and said design layout database have the same format.
15. The system of claim 12, wherein the defect layout generator
determines the locations of the spot defects randomly or by a given
rule.
16. The system of claim 12, wherein the number of the spot defects
is user-defined.
17. The system of claim 12, wherein the one or more sizes of the
spot defects are user-defined.
18. The system of claim 12, wherein the processor further
determines whether at least one spot defect causes a short-circuit
between conductive regions.
19. The system of claim 12, wherein the processor further
determines whether at least one spot defect causes an open-circuit
in the conductive region.
20. The system of claim 12, wherein the processor further estimates
susceptibility of the circuit layout to the defects of the defect
layout.
21. The system of claim 12, wherein the processor further estimates
a manufacturing yield of the circuit layout.
Description
BACKGROUND
[0001] The invention relates to the layout design and manufacture
process of integrated circuits, and more particularly to a
simulation methodology of defects interaction with layout
design.
[0002] Defects may be randomly introduced during IC fabrication
process. Some of these defects may cause electrical circuitry
failures (open or short faults in general), and similar electrical
failures are collectively referred to as certain failure
mechanisms. For example, spot defects are caused by particles such
as dust and other contaminants in materials and equipment. Open or
short failures are considered from two types of mechanisms: "extra
material" defects causing shorts between different conductive
regions; and "missing material" defects causing open circuits.
These defects may be randomly occurring particles of foreign
matters, of varying sizes, during the manufacturing process. These
defects can fatally cause an integrated circuit failure.
[0003] Conventionally, susceptibility of an integrated circuit to
defects is estimated using complicated numerical methods, such as a
computer-aided mathematical analysis of the integrated circuit mask
layout. Typically, such an analysis requires complicated numerical
methods and large amounts of computing and resources.
[0004] For example, the determination of the susceptibility of an
integrated circuit to defects may be obtained by a computer
analysis of the integrated circuit mask layout. It is common for
such an analysis to require lots of computer time and a large
amount of computer memory. A substantial cost must be incurred to
estimate these properties and other properties of an integrated
circuit.
[0005] A method commonly used to reduce the time to extract
properties is to exploit the hierarchy of the integrated circuit
design. In its simplest form the interactions between sub-cells,
i.e., discrete areas of the design, are ignored. The technique
consists of the analysis of each sub-cell within the design to
estimate the property of the sub-cell. This property is then
multiplied by the numbers of repeats of the sub-cell within the
chip design. The technique is limited by the nature of the design
hierarchy. Integrated circuits that are largely made up of multiple
copies of a single or a few cells can be analyzed.
[0006] The simplified approach of hierarchical extraction of whole
chip ignores interactions between cells. This might always lead to
certain degree of inaccuracy. The level of inaccuracy is not easily
predicted so that the results are less confident. In more complex
embodiments interactions between cells are included. This ensures
that the results are accurate, but at a cost. The implementation is
considerable more difficult. The analysis takes longer since the
interaction region, which can be large, must also be processed.
SUMMARY
[0007] An alternative methodology of defect simulation and systems
are provided. In embodiments of a defect simulation system
comprising a defect layout generator and processor, wherein the
defect layout generator generates defect layouts with the same
layout database format. The processor first compares the defect
layouts and a provided circuit layout comprising a plurality of
electrical conducting regions. The processor further judges whether
the conductive regions are impacted by the spot defects, and
determines whether circuitry short and/or open failures are caused
by the spot defects in the conductive regions.
[0008] Also disclosed are methods of defect simulation. In an
embodiment of such a method, a defect layout database comprising a
given numbers of spot defects and given sizes is provided. A
circuit layout to be analyzed is provided, wherein the circuit
layout comprises a plurality of electrical conducting regions. The
defect layout and the circuit layout are then processed to judge
whether the conductive regions are impacted by the spot
defects.
[0009] Various methods may take the different forms of program
coding embodied in a tangible media or tool. When the program
coding is loaded into and executed by a computing machine, the
machine becomes an apparatus for practicing the invention.
DESCRIPTION OF THE DRAWINGS
[0010] The invention can be more fully understood by reading the
subsequent detailed description and examples with references and
the accompanying drawings, wherein:
[0011] FIG. 1 is a schematic diagram showing an embodiment of a
defect simulation system implemented with a circuit design
system;
[0012] FIG. 2 is a flowchart of an embodiment of a method of defect
simulation; and
[0013] FIGS. 3A-3C illustrate comparison of circuit and defect
layouts during the defect simulation.
DETAILED DESCRIPTION
[0014] In the following detailed description, reference is made to
the accompanying drawings which form a part hereof, and in which is
shown by way of illustration of specific embodiments. These
embodiments are described in sufficient details to enable those
skilled in the art to practice the disclosure, and it is to be
understood that other embodiments may be utilized and structural,
logical and electrical changes may be made without departing from
the spirit and scope of the disclosure. The following detailed
description is, therefore, not to be taken in a limiting sense. The
leading digit(s) of reference numbers appearing in the Figures
corresponds to the Figure number, with the exception that the same
reference number is used throughout to refer to an identical
component, which appears in multiple Figures.
[0015] FIG. 1 is a schematic diagram showing an embodiment of a
defect simulation system 100 implemented with a circuit layout
source 150. As shown in FIG. 1, defect simulation system 100
comprises an interface 101, defect layout generator 103, defect
layout database 105, and a processor 107. The circuit layout source
150 provides a circuit layout to defect simulation system 100. The
defect simulation system 100 is connected to circuit layout source
150 via the interface 101. The defect simulation system 100
provides output 13 via the interface 101. The defect layout
generator 103 receives a plurality of random numbers from a random
number generator 104, and determines the positions of a plurality
of spot defects according to the received random numbers. The
defect layout generator 103 then generates a defect layout
comprising a given number of spot defects of a given size arranged
according to the positions determined by the random numbers. The
defect layout generated by the defect layout generator 103 is
stored in the defect layout database 105, and is analyzed by the
processor 107. The processor 107 receives a circuit layout input
according to a user instruction, and compares the received circuit
layout and the defect layout. The processor 107 determines whether
the position of the spot defects and the conductive regions overlap
and/or comes into contact, and determines whether short-circuit
and/or open circuits are caused by the spot defect in the
conductive region.
[0016] The processing algorithm implemented in defect simulation
system 100 is detailed in the flowchart of FIG. 2. A defect
database is generated in step S21. In step S211, data specifying
the number and size of defects is received. In step S213, a
plurality of random numbers are generated. The random numbers may
be integers generated by a pseudo-random number generator according
to mathematical formula. The number of the random numbers is
determined according to given number and size of defects. In step
S214, coordinates corresponding to a plurality of spot defects are
determined according to the random numbers generated in step S213.
A defect layout comprising the spot defects is then generated
according to the coordinates based on preset coordinate axis and
coordinate center. In step S215, a defect layout comprising spot
defects of the given size and number is generated, wherein the spot
defects are arranged according to the determined positions. In step
S23, a circuit layout is provided, which may be retrieved from a
circuit layout database or provided by a user. The circuit layout
comprises a plurality of conductive regions 31, as shown in FIG.
3A. In step S25, the retrieved circuit layout and the defect layout
are compared. In step S27, it is judged whether the conductive
regions are impacted by the spot defects. For example, simple
Boolean operations are sufficient, instead of conventional
complicated numerical methods. In step S28, it is determined
whether short-circuits and/or open circuits are caused by the spot
defects in the conductive region. Referring to FIG. 3B, the
conductive region 31a is intercepted by spot defect 33a. This
interception induces an open circuit in the conductive region 31a.
Referring to FIG. 3C, the conductive regions 31b and 31c are
bridged by spot defect 33b. Thus short-circuit is caused by the
bridged conductive regions.
[0017] In case necessary, instead of using an experimentally
optimum defect layout, the above process may be repeated several
times for different defect layouts. The results thereof may be
taken into consideration in combination to make an engineering
decision more accurate.
[0018] The described system and method may be applied to extra
material of a given size and other defect types, such as missing
material, pinhole, inter-level dielectric defects and defective
contacts and vias.
[0019] Results obtained from the described defect simulation may be
further used for various applications.
[0020] For example, the defect simulation may be used for
estimating sensitivity or susceptibility of a circuit layout to the
defects during the manufacturing process. The susceptibility of the
integrated circuit to the defects can be used to estimate the
manufacturing yield of the devices, or for further engineering
study. It could also be used to estimate the cost or the volume
required for the production of a given number of good circuit dies
in planning phase.
[0021] The technique of characterizing layout may be extended to
the characterization of particular design environments used for
automated integrated circuit design, in particular, to compare the
manufacturability and other characteristics of different design
environment.
[0022] The present invention is capable of analyzing large
commercial integrated circuits (1,000,000 transistors) in a
reasonable time with standard computer resources. Additionally, the
practical applications of the invention are not limited by the
design hierarchy, the size of the device or the design environment
used to produce the design. The preferred embodiment of the present
invention can be used even by those of ordinary skill. The
significant increase in execution speed and lower memory
requirements permitted by the present invention make possible the
practical application of more rigorous techniques. Such techniques
are not generally considered practical because of the time and/or
computer memory requirements.
[0023] Various embodiments, or certain aspects or portions thereof,
may take the different forms of program coding (i.e., instructions)
embodied in tangible media or tools, when the program code is
loaded into and executed by a computing machine, such as a
computer, the machine becomes an apparatus for practicing the
invention. Some embodiments may also be embodied in the form of
program code transmitted over some transmission medium, such as
electrical wiring or cabling, through fiber optics, or via any
other form of transmission, wherein, when the program code is
received and loaded into and executed by a machine, such as a
computer, the machine becomes an apparatus for practicing
embodiments of the invention. When implemented on a general-purpose
processor, the program coding combines with the processor to
provide a unique apparatus that operates analogously to specific
logic circuits.
[0024] While the invention has been described by way of example and
in terms of preferred embodiment, it is to be understood that the
invention is not limited thereto. Those who are skilled in this
technology can still make various alterations and modifications
without departing from the scopes and spirits of this invention.
Therefore, the scope of the present invention shall be defined and
protected by the following claims and their equivalents.
* * * * *