U.S. patent application number 11/103917 was filed with the patent office on 2006-10-12 for method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Yen Chuang, Huang-Yi Huang.
Application Number | 20060226014 11/103917 |
Document ID | / |
Family ID | 37077197 |
Filed Date | 2006-10-12 |
United States Patent
Application |
20060226014 |
Kind Code |
A1 |
Chuang; Yen ; et
al. |
October 12, 2006 |
Method and process for improved uniformity of electrochemical
plating films produced in semiconductor device processing
Abstract
A method and device for ECP copper deposition into openings and
over a surface of a semiconductor substrate provides a final
deposited film with a uniform height across the substrate. The
substrate is submerged in an ECP electrolyte solution with
accelerants formed on a dielectric surface and in and over
damascene openings formed in the dielectric surface, and copper is
deposited onto the surface and into the damascene openings. A
deplating process that uses a reverse polarity of power conditions
used in the ECP process is then used for a brief time to remove
some of the deposited copper and an excess portion of the
accelerant. The copper is preferentially removed from portions
where the initial deposition produced localized thick portions and
the deplating process is followed by a further ECP process that
yields a copper film with a uniform top surface.
Inventors: |
Chuang; Yen; (Taipei City,
TW) ; Huang; Huang-Yi; (Hsin-Chu City, TW) |
Correspondence
Address: |
Howard Chen;Preston Gates & Ellis LLP
Suite 1700
55 Second Street
San Francisco
CA
94105
US
|
Assignee: |
Taiwan Semiconductor Manufacturing
Co., Ltd.
|
Family ID: |
37077197 |
Appl. No.: |
11/103917 |
Filed: |
April 11, 2005 |
Current U.S.
Class: |
205/87 ;
205/291 |
Current CPC
Class: |
C25D 5/02 20130101; C25D
5/10 20130101; C25D 3/38 20130101 |
Class at
Publication: |
205/087 ;
205/291 |
International
Class: |
C25D 3/38 20060101
C25D003/38 |
Claims
1. An electrochemical plating (ECP) method comprising: providing a
substrate with a surface; providing accelerants on the surface;
depositing copper on the surface by ECP in which the substrate is
submerged in an ECP electrolyte solution; deplating whereby some
copper and an excess portion of the accelerants are removed; and
further depositing copper over the surface by ECP in which the
substrate is submerged in the ECP electrolyte solution and the
copper includes an upper surface that is essentially uniform in
elevation with respect to the surface.
2. The method as in claim 1, wherein the accelerants are a
component of the ECP electrolyte solution and the providing
accelerants and the depositing copper take place substantially
simultaneously.
3. The method as in claim 1, wherein the deplating takes place for
a time of about 5 seconds.
4. The method of claim 1, wherein the providing a substrate
includes the substrate including openings extending downwardly from
the surface, the depositing copper includes depositing copper in
the openings and the deplating is initiated about when the openings
become filled with copper.
5. The method of claim 1, wherein the providing a substrate
includes openings extending downwardly from the surface, and
wherein the excess portion of the accelerants lies above the
openings.
6. The method as in claim 5, wherein the deplating removes more
copper from over the openings than from other areas of the
substrate surface.
7. The method as in claim 1, wherein the depositing, the deplating,
and the further depositing take place in-situ and wherein the
deplating uses a reverse polarity of power used in the depositing
and the further depositing.
8. The method as in claim 1, wherein the depositing forms a
non-uniform copper layer and the deplating results in a
substantially uniform copper layer.
9. An electrochemical plating (ECP) method comprising: providing a
substrate in an ECP electrolyte solution; and plating copper on a
surface using an ECP operation that includes a sequence of a
forward polarity first plating step followed by an in-situ reverse
polarity deplating step followed by an in-situ forward polarity
second plating step, the forward polarity steps having a forward
power and the reverse polarity step having a reverse power.
10. The method as in claim 9, wherein the reverse polarity
deplating step takes place for a time within a range of 3 to 12
seconds.
11. The method as in claim 9, wherein the ECP electrolyte solution
includes accelerants therein and the reverse polarity deplating
step removes an excess portion of the accelerants from the
surface.
12. An electrochemical plating (ECP) method comprising: providing a
semiconductor substrate with a dielectric layer having an upper
surface and openings extending downwardly from the upper surface;
depositing copper at least in the openings using an ECP operation;
when the openings are substantially filled, performing a deplating
operation that removes some of the copper; and further depositing
copper at least over the openings and over the upper surface.
13. The method as in claim 12, wherein the depositing copper at
least in the openings using an ECP operation includes submerging
the substrate in an ECP electrolyte solution that further includes
an accelerant, and wherein the deplating process removes excess
portions of the accelerant.
14. The method as in claim 13, wherein the accelerant accumulates
around the openings during the depositing copper and the deplating
produces a substantially uniform concentration of accelerant across
the substrate.
15. The method as in claim 12, wherein the deplating process takes
place for about 5 seconds.
16. The method as in claim 12, wherein the openings include extend
to a conductive bottom and the openings comprise at least one of
trenches and vias.
17. The method as in claim 12, wherein the deplating process is
performed in-situ with the depositing and the further depositing,
and the deplating process includes a reverse polarity of a power
applied in the depositing and in the further depositing.
18. The method as in claim 12, wherein the further depositing
copper produces copper filling the openings and over the upper
surface such that the copper has a top surface of substantially
uniform height.
19. The method as in claim 12, wherein the depositing copper
includes depositing copper over the upper surface.
20. The method as in claim 12, wherein the deplating preferentially
removes the copper from over the openings.
Description
BACKGROUND
[0001] The present invention relates generally to the
electrochemical plating of film and more particularly to the
electrochemical plating of copper-based metal layers during the
fabrication of semiconductor devices.
[0002] In the fabrication of integrated circuit (IC) semiconductor
devices, substrate surface planarity is of critical importance.
This is especially so as the scale of integration increases and the
device features are reduced in size (e.g., sub-micron sized
geometries). ICs typically include metal layers that are used to
interconnect individual device features thereof. Individual metal
layers are typically isolated from each other by one or more
insulating, dielectric material layers. Conductive interconnection
features (e.g., trenches, vias, contacts, etc.) may be formed
through the dielectric layers to provide the electrical access
between successive conductive metal layers.
[0003] Copper and copper alloys are becoming a metal of choice in
ICs as the metal layers and the interconnection structures that
provide the electrical access between successive metal layers.
Copper metal is used because its material properties feature lower
resistance and improved electromigration performance compared to
traditional metal materials such as aluminum and aluminum alloys.
Copper and copper alloy layers (films) may be deposited by various
methods such as physical vapor deposition (PVD), chemical vapor
deposition (CVD) and electrochemical plating (ECP). ECP for copper
is preferred as a low cost and effective deposition method. A
typical ECP process for copper involves the deposition of the metal
conductive layer on the semiconductor substrate surface by
contacting the wafer with an electrolyte solution and applying an
electrochemical potential between electrodes of opposing
polarities. During this process, copper ions plate out of the
electrolyte solution and deposit onto the semiconductor substrate
surface.
[0004] Copper is typically difficult to pattern and etch.
Accordingly, copper features are typically formed using a damascene
or dual damascene processes. In damascene processes, features such
as vias and/or trenches, are defined within the dielectric material
and subsequently filled with copper. The copper is deposited both
into the opening in the dielectric feature and onto the surrounding
field on top of the dielectric layer. The copper deposited onto the
field may be subsequently removed to leave the copper filled
feature formed within the dielectric or reduced, left on to become
subsequently patterned and etched to become the next metal line
layer of the IC device.
[0005] The copper or copper alloy film deposited on the field (top
of the dielectric) may be removed or planarized by using such
methods as chemical mechanical polishing (CMP), plasma etching and
or wet etching. Copper film removal and planarization difficulties
are dependant upon the thickness uniformity of the copper layer.
The ECP processes may not produce copper metal layers of uniform
thickness on top of the dielectric layer, particularly at and near
the field locations above the copper-filled via and/or trench
features within the dielectric layer. At these field locations,
above the copper-filled vias and/or trenches, the deposited copper
layer thickness is usually greater than the rest of the field due
to an accelerated rate of copper deposition (ECP activity) at that
particular field region. This accelerated deposition rate is
attributed to excess electrochemical activity resulting from the
copper deposition of the underlying via and/or trench features.
[0006] FIG. 1 illustrates the phenomena of non-uniform thickness
deposition during the conventional ECP processing of areas over
underlying via/trench type structures and areas with no underlying
structures. FIG. 1A is a cross-section of a portion of an IC
semiconductor device 100 during fabrication. The dielectric
substrate 102 is shown with several damascene via/trench structures
104 having been fabricated into the dielectric substrate 102. These
via/trench structures 104 have been fabricated so that subsequent
ECP processing will deposit a copper based metal film both over the
dielectric and into the structures 104, filling them to completion
with continued deposition to obtain a desired thickness of the
copper based film onto the surrounding field on top of the
dielectric substrate 102. The positions of the black dots 106 of
the figure represent the relative concentration and distribution of
the active accelerant component of the ECP chemicals that are used
for the deposition process. It is noted that the distribution of
the ECP accelerant 106 is fairly evenly distributed across the
multi-dimensioned open surface of the dielectric 102 at the start
of the actual ECP deposition, both across the top of the field and
within the open damascene via/trench structures 104.
[0007] FIG. 1B illustrates how the previously even distribution of
the ECP accelerant 106 changes as the via/trench structures 104 are
filled during the ECP process. As the via/trench structures 104 are
filled, the ECP accelerants 106 that were located within these open
structures migrate upwards. The resultant migration of the ECP
accelerants 106 produces a non-uniform distribution of the ECP
accelerants 106 across the changing top surface of the open
dielectric substrate 102. It is this excess and uneven distribution
of the ECP accelerant 106 during the ECP deposition processing that
causes the non-uniform final thickness of a deposited copper-based
film 108. FIG. 1C illustrates the final non-uniformity of the
copper-based film 108. The final copper metal film 108 is shown on
top of the dielectric substrate 102. The thickness of the copper
film 108 over the dielectric substrate 102 areas without any
underlying via/trench structures 104 is generally consistent and
uniform. However, the thickness of the copper film portion 110
located above the underlying, filled via/trench structures 104 is
significantly thicker than the surrounding field areas without any
underlying via/trench structures. This increased copper thickness
region 110 corresponds to the locations of higher concentration,
excess ECP accelerants 106 that were shown in FIG. 1B.
[0008] In addition to the previously discussed micro non-uniformity
issue related to structures within the dielectric layers, a macro
copper layer uniformity problem may occur across the entire wafer
substrate by which the IC devices are built upon. Various
dispersion and non-uniformity issues of the ECP chemicals (e.g.,
accelerants) affected by various mechanical and equipment related
factors may cause the wafers to experience a thickness variation
from wafer edge to wafer center. In typical ECP processing of
semiconductor wafers, the wafer center tends to experience a higher
rate of copper metal deposition than the wafer edge, thus often
producing wafers with the copper metal layers thicker at the center
versus the edge. The graph of FIG. 2 illustrates the typical
relationship of final plating thickness, shown as the y-axis of the
graph, as a function of the process wafer location, shown as the
x-axis of the graph. The graph shows the typical relationship with
wafer center locations having an overall thicker final film
thickness at locations at the wafer edge.
[0009] Typical IC fabrication flows commonly address the micro
uniformity issue of the copper layer thickness non-uniformity on
top of the field (dielectric) above the regions with light versus
dense underlying via/trench features by simply depositing a thick
copper film and then relying upon a long and carefully controlled
metal planarization/etching process to obtain a flat final copper
metal layer. This method of deposition and planarization/etching
undesirably adds processing time, wastes copper and is dependant
upon tight controls of the planarization/etching processes. Such
waste and strict control requirements increase the ICs' fabrication
costs and cycle times, as well as the decrease of IC production
throughput rates. The macro non-uniformity issue of the copper
layer thickness across the wafer areas (center versus edge) may be
minimized with careful optimization and control of machine process
parameters such as wafer revolution speed during the ECP process.
The varying of process parameters during the ECP deposition may
undesirably induce film composition variations within the final
copper metal film. In addition, the varying values of the process
parameters may be more difficult to monitor and control. Despite
the implementation of such optimizations to the machine/process
parameters, the desired level of the copper layer thickness,
uniformity, planarity and composition may still not be
obtained.
[0010] What is desired is an improved method by which the copper
metal layer deposited during the ECP processing is planar as
formed, i.e., it includes uniform thickness both over the various
topography and fields of the individual IC devices, as well as
throughout the semiconductor wafer that includes many IC
devices.
SUMMARY
[0011] In view of the foregoing, this disclosure provides an
improved method and process for the ECP deposition of copper metal
layers upon a semiconductor substrate surface such that the final
deposited film is planar across the semiconductor wafer.
[0012] According to one aspect, accelerants are deposited onto the
top surface of a dielectric substrate having one or more damascene
structures, and the dielectric substrate submerged in an
electrolyte. Copper is then deposited onto the top surface of the
dielectric substrate and filling the one or more damascene
structures and coating a portion of the dielectric substrate. The
copper is then deplated for a predetermined period of time to
remove an excess portion of the accelerant and a portion of the
copper to yield a uniform top surface of the copper.
[0013] The construction and method of operation of the invention,
however, together with additional objects and advantages thereof
will be best understood from the following description of specific
embodiments when read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIGS. 1A through 1C are cross-sectional views of a
conventional IC device during conventional ECP deposition
processing.
[0015] FIG. 2 is a graph showing the relationship between final
plating thickness and the plating location within the processed
wafer for the conventional ECP deposition process.
[0016] FIGS. 3A through 3D are cross-sectional views of an IC
device during ECP deposition processing using the ideal method and
process in accordance with one embodiment of the present
invention.
[0017] FIG. 4 is a flow chart summarizing the ECP method and
processing steps as described in accordance with an embodiment of
the present invention.
DESCRIPTION
[0018] The present disclosure provides a detailed description of an
improved method and process for the ECP deposition of copper metal
layers upon a semiconductor substrate surface such that the final
deposited film is planar and uniform both at the micro uniformity
scale, across the various topography and fields of the individual
IC devices, as well the macro uniformity scale, across the
semiconductor wafer of many IC devices. The improved method and
process implements a deplating step, in-situ within the ECP
processing, such that excess chemical accelerant components of the
ECP chemistry are removed leaving a uniform, even distribution of
the components to provide a uniform, planar final deposited copper
metal film layer.
[0019] FIG. 3 illustrates an exemplary method and process of the
present invention. FIG. 3A is a cross-section of a portion of an IC
semiconductor device 300 during fabrication. The dielectric
substrate 302 is shown with several damascene via/trench structures
304 having been fabricated into the dielectric substrate 302. These
via/trench structures 304 have been fabricated so that subsequent
ECP processing will deposit a copper based metal film both into the
structures 304, filling them to completion with continued
deposition to obtain a desired thickness of the copper based film
onto the surrounding field on top of the dielectric substrate 302.
The positions of the black dots 306 of the figure represent the
relative concentration and distribution of the active accelerant
component of the ECP chemicals that are used for the deposition
process. The accelerants are advantageously included as a component
of the ECP electrolyte solution. Accelerants commonly used in the
ECP of copper include bis(3-sulfopropyl)disulfide,
mercapto-propane-sulfonic acid and thiourea. It is noted that the
distribution of the ECP accelerant 306 is fairly evenly distributed
across the multi-dimensioned open surface of the dielectric 302 at
the start of the actual ECP deposition, both across the top of the
field and within the open damascene via/trench structures 304.
[0020] FIG. 3B illustrates how the previously even distribution of
the ECP accelerant 306 changes as the via/trench structures 304 are
filled during the ECP process. As the via/trench structures 304 are
filled, the accelerants 306 that were located within these open
structures migrate upwards. The resultant migration of the ECP
accelerants produces a non-uniform distribution of the accelerants
306 across the changing top surface of the open dielectric
substrate 302. It is this excess of accelerants over the via/trench
structures 304 and the uneven distribution of ECP accelerant 306
during the ECP deposition processing that would cause the
non-uniform final thickness of the deposited copper-based film 308
using conventional methods. The method and process of the present
invention provides for the ECP deposition to halt at or near the
point at which the damascene via/trench structures 304 are filled
and before the bulk deposition of the copper film onto the
remaining field areas of the open dielectric substrate 302 begins.
A thin copper metal film 308 may be depositing on the remaining
field of the open dielectric substrate 302 (shown in FIG. 3B)
during the ECP deposition step that fills the via/trench structures
304 in various exemplary embodiments.
[0021] The deplating process is now performed onto the partially
ECP deposited copper metal film 308. The deplating process of the
present disclosure is performed in-situ, utilizing the same
equipment and hardware of the ECP process. A reverse polarity of
the power applied in the ECP process, is applied to the same ECP
electrodes thereby causing the ECP's electrolysis process to
operate in reverse for a pre-determined short period of time.
During the deplating process, the copper metal film 308 which is
already deposited onto the wafer's dielectric substrate 302 is
removed until the deplating process is stopped. The copper film 308
is preferentially removed from portions where the initial
deposition produced localized thick portions of the copper film
308. The reversed chemical electrolysis also removes the
non-uniformly distributed excess chemical accelerants 306 off of
the deposited copper metal film substrate 308. The accelerants are
preferably removed from regions of high concentration such as over
via/trench structures 304. The remaining accelerants 306 are
distributed fairly evenly and uniformly across the open surface of
the exposed copper metal film 308, both over the top of the field
areas without underlying damascene via/trench structures 304 and
field areas with underlying damascene via/trench structures. It is
noted that the disclosed deplating process and equipment
configurations and parameters are changed and controlled by the ECP
process tools as a process recipe step. The disclosed deplating
process is fairly short in time, e.g. 3 to 12 seconds and typically
approximately 5 seconds, much shorter than that of the combined
total ECP copper metal film deposition times. Other deplating times
may be used in other exemplary embodiments.
[0022] FIG. 3C illustrates a cross-sectional view after completion
of the deplating step. The deplated copper metal film 308, both
over the top of the field areas without underlying damascene
via/trench structures 304 and field areas over underlying damascene
via/trench structures, is now a little thinner than prior to the
deplating process. The remaining ECP accelerants 306 are now
distributed fairly evenly and uniformly across the entirety of the
open surface of the exposed, deplated copper metal film 308.
[0023] The method of the present invention further provides for the
completion of the ECP copper metal film deposition to obtain the
final copper thickness required by the IC devices. The ECP
equipment and hardware is once again changed via a similar process
recipe step as created for the deplating process. The previously
reversed polarity of the power to the ECP electrodes is now changed
back to the original power configuration so that the ECP copper
deposition onto the production wafers resumes. The ECP copper
deposition then continues to obtain the required final thickness of
the copper metal film which may vary according to device
requirements. The second ECP step may be used to plate about
3000-7000 A of copper in one embodiment, but other thicknesses may
be used in other exemplary embodiments. FIG. 3D shows the
cross-sectional view of the IC device after completion of the ECP
final deposition process step with a planar final copper metal film
308 of uniform thickness. It is the even, uniformly distributed
accelerants 306 left on the surface of the partially deposited
copper metal film 308 after the deplating process step shown as
FIG. 3C that enables the subsequent ECP copper metal film
deposition to provide a final film with a uniform thickness. The
final planar, uniform thickness exists both over the top of the
field areas without underlying damascene via/trench structures 304
and field areas with underlying damascene via/trench structures,
i.e., the same height with respect to the substrate 302. It is also
noted that the removal of the non-even distribution of accelerants
306 allows for a subsequent copper metal film deposition of a
uniform thickness resolving both the previously described micro and
macro uniformity issues experienced from plated films processed via
the conventional ECP processes without the disclosed method and
process.
[0024] FIG. 4 is a flow chart summarizing the process sequence of
an exemplary method of the present invention. The first process
step 402 of the present method is the ECP deposition of the copper
metal film that stops about when the open damascene via/trench
structures of the dielectric substrate layer are filled. Once the
damascene structures are filled, the ECP deposition process is
stopped. The next process step is the deplating process step 404.
The deplating process step 404 is then performed for a
pre-determined deplating time. The deplating process time may have
been previously determined through process and device
characterization studies to determine the required and optimum
performance of the combined ECP deposition and deplating steps.
After the completion of the deplating step 404, the second ECP
deposition step 406 is performed. The completed second ECP
deposition step 406 provides the final copper metal film of a
planar layer with uniform thickness over all areas of the
dielectric field, both above underlying damascene via/trench
structures and over areas without any underlying damascene
via/trench structures. These three sequential steps 402, 404 and
406, may be considered as a single ECP process method comprising a
deposition step and an in-situ deplating step, followed by another
deposition step.
[0025] The method and process of using a deplating process step
between ECP deposition steps greatly improves the planarity and
thickness uniformity of plated copper metal films deposited upon
the semiconductor substrate surface. This improvement of planarity
and thickness uniformity can be obtained on substrates with various
levels of topography and underlying structures. Such planarity and
uniformity improvements resolve both micro and macro uniformity
issues experienced using conventional ECP processes. Implementation
of the method and process of the present invention may eliminate
the requirement to define and maintain special varying process,
tool parameters which could lead to inconsistent and
difficult-to-control ECP film compositions. The method and process
of the present invention may also eliminate the requirements for
special, separate planarization/etch processing upon an overly
thick deposited ECP film just to obtain film planarity.
[0026] The method and process of the present invention may be
easily implemented within existing ECP fabrication tools and tool
configurations of existing and future IC fabrication facilities and
operations. Various, commercially available tools may be used. The
disclosed method and process may be defined as a single new ECP
process recipe within the ECP fabrication tools as a recipe
comprised of at least 3 individual sequential steps: deposition,
deplating and deposition. It is noted that for further
planarization optimizations and future process and devices
technologies, the disclosed method and process may be incorporated
into embodiments where multiple deposition, deplating process
steps, combinations and sequences may be required.
[0027] The implementation of the disclosed method and structure
will improve IC device quality, yields and production throughput
rates. Such improvements will translate into significant cost
improvements for a given production facility to maintain highly
competitive cost and output advantages over other manufacturers of
similar product devices and technologies. As result, advanced
device generations and performance levels may be more easily
achieved and attained.
[0028] The present disclosure provides several examples to
illustrate the flexibility of how the disclosed method and
deplating process may be used and implemented. The above disclosure
provides different embodiments or examples for implementing
different features of the disclosure. Specific examples of
components and processes are described and are intended to be
exemplary and not intended to limit the disclosure from that
described in the claims.
[0029] Although the invention is illustrated and described herein
as embodied in a design and method for, it is nevertheless not
intended to be limited to the details shown, since various
modifications and structural changes may be made therein without
departing from the spirit of the invention and within the scope and
range of equivalents of the claims. Accordingly, it is appropriate
that the appended claims be construed broadly and in a manner
consistent with the scope of the disclosure, as set forth in the
following claims.
* * * * *