U.S. patent application number 11/422592 was filed with the patent office on 2006-09-28 for non-volatile memory device and method of fabricating the same.
This patent application is currently assigned to SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to Seong-Soon CHO, Jung-Dal CHOI, Chang-Hyun LEE, Jong-Woo PARK.
Application Number | 20060216891 11/422592 |
Document ID | / |
Family ID | 19711443 |
Filed Date | 2006-09-28 |
United States Patent
Application |
20060216891 |
Kind Code |
A1 |
CHOI; Jung-Dal ; et
al. |
September 28, 2006 |
NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
Abstract
A non-volatile memory device includes a tunnel oxide layer, a
charge storage layer, a blocking insulating layer, and a gate
electrode that are sequentially stacked, as well as an impurity
diffusion layer in an active region at both sides of the gate
electrode. The gate electrode crosses active regions between device
isolation layers formed in a predetermined area of a semiconductor
substrate, and an edge of the charge storage layer is extended to
have a protruding part that protrudes from the gate electrode. In
order to form a charge storage layer having a protruding part, a
stack insulating layer including first to third insulating layers
is formed in an active region between the device isolation layers
formed in the substrate. A plurality of gate electrodes crossing
the active region are formed on the stack insulating layer, and a
sidewall spacer is formed on both sidewalls of the gate electrode.
Using the sidewall spacer and the gate electrode, the stack
insulating layer is etched to form a charge storage layer that
protrudes from the sidewall of the gate electrode.
Inventors: |
CHOI; Jung-Dal; (Kyunggi-do,
KR) ; PARK; Jong-Woo; (Seoul, KR) ; CHO;
Seong-Soon; (Kyunggi-do, KR) ; LEE; Chang-Hyun;
(Kiheung-eub Yongin-shin, Kyunggi-do, KR) |
Correspondence
Address: |
MARGER JOHNSON & MCCOLLOM, P.C.
210 SW MORRISON STREET, SUITE 400
PORTLAND
OR
97204
US
|
Assignee: |
SAMSUNG ELECTRONICS CO.,
LTD.
416 Maetan-dong, Yeongtong-gu, Suwon-si
Gyeonggi-do
KR
|
Family ID: |
19711443 |
Appl. No.: |
11/422592 |
Filed: |
June 6, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10186153 |
Jun 27, 2002 |
7081651 |
|
|
11422592 |
Jun 6, 2006 |
|
|
|
Current U.S.
Class: |
438/257 ;
257/E21.679; 257/E27.081; 438/261 |
Current CPC
Class: |
H01L 27/11568 20130101;
H01L 27/105 20130101; H01L 27/11573 20130101 |
Class at
Publication: |
438/257 ;
438/261 |
International
Class: |
H01L 21/336 20060101
H01L021/336 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 28, 2001 |
KR |
2001-37420 |
Claims
1. A method of fabricating a non-volatile memory device, comprising
the steps of: forming a stack insulating layer on a semiconductor
substrate by sequentially stacking first, second and third
insulating layers; forming a gate electrode crossing over the stack
insulating layer; and forming a charge storage layer and a blocking
insulating layer which are sequentially stacked between the gate
electrode and the first insulating layer by patterning the third
and second insulating layers, wherein at least the second
insulating layer is patterned so that the charge storage layer has
a protruding part which protrudes from a sidewall of the gate
electrode.
2. The method of claim 1, wherein the first and third insulating
layers are made of silicon oxide, and the second insulating layer
is made of silicon nitride.
3. The method of claim 1, wherein the step of forming the charge
storage layer and the blocking insulating layer includes the steps
of: etching the third insulating layer by using the gate electrode
as an etch mask to form a blocking insulating layer which is
self-aligned to the gate electrode; forming a first sidewall spacer
on the sidewall of the gate electrode and a sidewall of the
blocking insulating layer; and etching the second insulating layer
by using the gate electrode and the first sidewall spacer as an
etch mask to form a charge storage layer whose width is larger than
a width of the gate electrode.
4. The method of claim 3, further comprising a steps of forming a
gate capping oxide layer at least on the sidewall of the gate
electrode prior to formation of the first sidewall spacer.
5. The method of claim 3, further comprising a step of forming a
second sidewall spacer on an outer sidewall of the first sidewall
spacer and the sidewall of the charge storage layer.
6. The method of claim 1, wherein the step of forming the charge
storage layer and the blocking insulating layer includes the steps
of: forming a first sidewall spacer on the sidewall of the gate
electrode; and sequentially etching third and second insulating
layers by using the gate electrode and the first sidewall spacer to
form a blocking insulating layer having a protruding part under the
first sidewall spacer and a charge storage layer which is
self-aligned to the blocking insulating layer.
7. The method of claim 6, further comprising a step of forming a
gate capping oxide layer at least on the sidewall of the gate
electrode prior to formation of the first sidewall spacer.
8. The method of claim 6, further comprising a step of forming a
second sidewall spacer on the outer sidewall of the first sidewall
spacer, the sidewall of the blocking insulating layer, and the
sidewall of the charge storage layer.
9. A method of fabricating a non-volatile memory device, comprising
the steps of: forming a device isolation layer and a stack
insulating layer, wherein the device isolation layer is formed in a
predetermined area of a semiconductor substrate to define an active
region, and the stack insulating layer includes first, second and
third insulating layers which are sequentially stacked at least on
the active region; forming a gate electrode crossing the active
region on the stack insulating layer; and forming a charge storage
layer and a blocking insulating layer which are sequentially
stacked between the first insulating layer and the gate electrode
by patterning the third to second insulating layers, wherein at
least the second insulating layer is patterned so that the charge
storage layer has a protruding part which protrudes from the
sidewall of the gate electrode.
10. The method of claim 9, wherein the first and third insulating
layers are made of silicon oxide, and the second insulating layer
is made of silicon nitride.
11. The method of claim 9, wherein the step of forming the device
isolation layer, the stack insulating layer, and the gate electrode
includes the steps of: sequentially forming a first insulating
layer, a second insulating layer, a third insulating layer, and a
lower gate conductive layer on an entire surface of the substrate;
sequentially patterning the lower gate conductive layer, the third
insulating layer, the second insulating layer, and the first
insulating layer to form a trench region which defines an active
region in a predetermined area of the substrate; forming a device
isolation layer to fill the trench area; forming a lower gate
conductive layer on an entire surface of a resultant structure
including the device isolation layer; and sequentially patterning
the upper gate conductive layer and the patterned lower gate
conductive layer to form a lower gate electrode intervened between
the gate electrode and the active region as well as an upper gate
electrode crossing over the active region and the device isolation
layer.
12. The method of claim 9, wherein the step of forming the device
isolation layer, the stack insulating layer, and the gate electrode
includes the steps of: forming a device isolation layer to define
an active region in a predetermined area of the substrate;
sequentially forming first to third insulating layers and a gate
conductive layer on an entire surface of a resultant structure
including the device isolation layer; and patterning the gate
conductive layer.
13. The method of claim 9, wherein the step of forming the charge
storage layer and the blocking insulating layer includes the steps
of: etching the third insulating layer by using the gate electrode
as an etch mask to form a blocking insulating layer which is
self-aligned to the gate electrode; forming a first sidewall spacer
on the sidewall of the gate electrode and the sidewall of the
blocking insulating layer; and etching the second insulating layer
by using the gate electrode and the first sidewall spacer as an
etch mask to form a charge storage layer whose width is larger than
a width of the gate electrode.
14. The method of claim 13, further comprising a step of forming a
gate capping oxide layer at least on the sidewall of the gate
electrode prior to formation of the first sidewall spacer.
15. The method of claim 13, further comprising a step of forming a
second sidewall spacer on the outer sidewall of the first sidewall
spacer and the sidewall of the charge storage layer.
16. The method of claim 9, wherein the step of forming the charge
storage layer and the blocking insulating layer includes the steps
of: forming a first sidewall spacer on the sidewall of the gate
electrode; and sequentially etching the third and second insulating
layers by using the gate electrode and the first sidewall spacer as
an etch mask to form a blocking insulating layer having a
protruding part under the first sidewall spacer and a charge
storage layer which is self-aligned to the blocking insulating
layer.
17. The method of claim 16, further comprising a step of forming a
gate capping oxide layer at least on the sidewall of the gate
electrode prior to formation of the first sidewall spacer.
18. The method of claim 16, further comprising a step of forming a
second sidewall spacer on the outer sidewall of the first sidewall
spacer, the sidewall of the blocking insulating layer, and the
sidewall of the charge storage layer.
19. A method of fabricating a non-volatile memory device with a
cell array region and a peripheral circuit region, comprising the
steps of: forming not only a device isolation layer in a
predetermined area of a semiconductor substrate to define a first
active region and a second active region in the cell array region
and the peripheral circuit region, respectively, but also a stack
insulating layer including first, second and third insulating
layers which are sequentially stacked on the first active region,
and a gate insulating layer stacked on the second active region;
forming a plurality of wordlines crossing over the stack insulating
layer, and a gate electrode crossing over the gate insulating
layer; and patterning at least the third and second insulating
layers to form a charge storage layer and a blocking insulating
layer which are sequentially stacked between the first insulating
layer and the wordlines, wherein at least the second insulating
layer is patterned so that the charge storage layer has a
protruding part which protrudes from a sidewall of the
wordlines.
20. The method of claim 19, wherein the first and third insulating
layers are made of silicon oxide, and the second insulating layer
is made of silicon nitride.
21. The method of claim 19, wherein the step of forming the device
isolation layer, the stack insulating layer, the gate insulating
layer, the wordlines, and the gate electrode includes the steps of:
selectively forming the stack insulating layer on the substrate in
the cell array region; selectively forming a gate insulating layer
on the substrate in the peripheral circuit region; forming a lower
gate conductive layer under a resultant structure including the
gate insulating layer; sequentially patterning the lower conductive
layer, the stack insulating layer, the gate insulating layer, and
the substrate to form a trench area which defines a first active
region and a second active region in the cell array region and the
peripheral circuit region, respectively; forming a device isolation
layer to fill the trench area; forming an upper gate conductive
layer on an entire surface of a resultant structure including the
device isolation layer; and forming a plurality of wordlines
crossing over the upper gate conductive layer, and a gate electrode
crossing over the second active region, wherein each of the
wordlines includes an upper wordline crossing over the first active
region, and a lower wordline intervened between the upper wordline
and the first active region; and wherein the gate electrode
includes an upper gate electrode crossing over the second active
region, and a lower gate electrode intervened between the upper
gate electrode and the second active region.
22. The method of claim 19, wherein the step of forming the device
isolation layer, the stack insulating layer, the gate insulating
layer, the wordlines, and the gate electrode includes the steps of:
forming a device isolation layer in a predetermined area of the
substrate to define a first active region and a second active
region in the cell array region and the peripheral circuit region,
respectively; selectively forming first, second and third
insulating layers in the cell array region of a resultant structure
including the device isolation layer; forming a gate insulating
layer on the second active region; forming a conductive layer on an
entire surface of a resultant structure including the first to
third insulating layers and the gate insulating layer; and
patterning the conductive layer to form wordlines crossing the
first active region and a gate electrode crossing the second active
region.
23. The method of claim 19, wherein the step of forming the charge
storage layer and the blocking insulating layer includes the steps
of: etching the third insulating layer by using the wordlines as an
etch mask to form blocking insulating layers which are self-aligned
to the wordlines; forming a first sidewall spacer on sidewalls of
the wordlines, sidewalls of the blocking insulating layers, and the
sidewall of the gate electrode; and etching the second insulating
layer by using the wordlines and the first sidewall spacer as an
etch mask to form a charge storage layer whose width is larger than
a width of the wordline.
24. The method of claim 23, further comprising a step of forming a
gate capping oxide layer on surfaces of the wordlines and a surface
of the gate electrode prior to formation of the first sidewall
spacer.
25. The method of claim 23, further comprising a step of implanting
impurities into the second active region by using the gate
electrode and the first sidewall spacer as an ion implanting mask
to form a heavily doped source/drain region, before or after
forming the charge storage layer.
26. The method of claim 25, further comprising a step of implanting
impurities into the first and second active regions by using the
wordlines and the gate electrode as an ion implanting mask, before
or after forming the blocking insulating layer.
27. The method of claim 23, further comprising a step of forming a
second sidewall spacer on the outer sidewall of the first sidewall
spacer and the sidewall of the charge storage layer in the cell
array region, and on an outer sidewall of the first sidewall spacer
in the peripheral circuit region.
28. The method of claim 27, further comprising a step of implanting
impurities into the second active region by using the gate
electrode, the first sidewall spacer, and the second sidewall
spacer as an ion implanting mask to form a heavily doped
source/drain region.
29. The method of claim 28, further comprising a step of implanting
impurities into the first and second active regions by using the
wordlines and the gate electrode as an ion implanting mask to form
a lightly doped source/drain region.
30. The method of claim 28, further comprising a step of implanting
impurities into the first and second active regions by using the
wordlines, the gate electrode, and the first sidewall spacer as an
ion implanting mask to form a lightly doped source/drain
region.
31. The method of claim 19, wherein the step of forming the charge
storage layer and the blocking insulating layer includes the steps
of: forming a first sidewall spacer on the sidewalls of the
wordlines and the sidewall of the gate electrode; and sequentially
etching the third and second insulating layers by using the gate
electrode, the first sidewall spacer, and the first sidewall spacer
as an etch mask to form a blocking insulating layer having a
protruding part under the first sidewall spacer and a charge
storage layer that is self-aligned to the blocking insulating
layer.
32. The method of claim 31, further comprising a step of a gate
capping oxide layer on the surface of the gate electrode and the
surfaces of the wordlines prior to formation of the first sidewall
spacer.
33. The method of claim 31, further comprising a step of implanting
impurities into the second active region by using the wordlines,
the gate electrode, and the first sidewall spacer as an ion
implanting mask to form a heavily doped source/drain region,
following formation of the first sidewall spacer.
34. The method of claim 33, further comprising a step of implanting
impurities into the first and second active regions by using the
wordlines and the gate electrode as an ion implanting mask to form
a lightly doped source/drain region, prior to formation of the
first sidewall spacer.
35. The method of claim 31, further comprising a step of forming a
second sidewall spacer on the outer sidewall of the first sidewall
spacer, the sidewall of the charge storage layer, and the sidewall
of the blocking insulating layer in the cell array region, and on
the outer sidewall of the first sidewall spacer in the peripheral
circuit region.
36. The method of claim 35, further comprising a step of implanting
impurities into the second active region by using the gate
electrode, the first sidewall spacer, and the second sidewall
spacer as an ion implanting mask to form a heavily doped
source/drain region.
37. The method of claim 36, further comprising a step of implanting
impurities into the first and second active regions by using the
wordlines and the gate electrode as an ion implanting mask to form
a lightly doped source/drain region, prior to formation of the
first sidewall spacer.
38. The method of claim 36, further comprising a step of implanting
impurities into the first and second active regions by using the
wordlines, the gate electrode, and the first sidewall spacer as an
ion implanting mask to form a light doped source/drain region,
before or after forming the charge storage layer and the blocking
insulating layer.
Description
RELATED APPLICATION
[0001] This application is a divisional of U.S. patent application
Ser. No. 10/186,153, filed on Jun. 27, 2002, now pending, which
relies for priority upon Korean Patent Application No. 2001-37420,
filed on Jun. 28, 2001, the contents of which are herein
incorporated by this reference in their entirety.
FIELD OF THE INVENTION
[0002] The present invention generally relates to a method of
fabricating a semiconductor device. More specifically, the present
invention is directed to a floating trap-type non-volatile memory
device that stores data in a charge storage layer including one
insulating layer by injecting charges, and to a method of
fabricating the same.
BACKGROUND OF THE INVENTION
[0003] Non-volatile memory devices continuously hold data even when
an external power is turned off. As the integration density of
memory devices increases, there is a need for reducing the area and
vertical height of a memory cell. Since a conventional floating
gate type non-volatile memory device has a floating gate, it is
restrictive to reduce a vertical height of a memory cell. For that
reason, a floating trap-type non-volatile memory device has been
attractive as a candidate to overcome the above disadvantage in
that charges can be stored in at least one insulating layer without
a floating gate.
[0004] FIG. 1 is a top plan view of a conventional floating
trap-type non-volatile memory device. A device isolation layer 11
is formed in a predetermined area of a semiconductor substrate to
define an active region 13. A plurality of gate electrodes 30 cross
the active region, and a charge storage layer 24 is intervened
between the gate electrode 30 and the active region 13. A sidewall
spacer 36 is formed on a sidewall of the gate electrode 30.
[0005] FIG. 2 through FIG. 5 are cross-sectional flow diagrams
showing the steps of fabricating a conventional nonvolatile memory
device, taken along a line I-I' of FIG. 1.
[0006] Referring now to FIG. 2, a device isolation layer 11 is
formed in a predetermined area of a semiconductor substrate to
define active regions 13. A stack insulating layer 18 and a gate
conductive layer 20 are formed on a semiconductor substrate where
the device isolation layer 11 is formed. Generally, the stack
insulating layer 18 includes first, second, and third insulating
layers 12, 14, and 16 which are conventionally made of thin thermal
oxide, silicon nitride, and CVD oxide, respectively.
[0007] Referring now to FIG. 3, the gate conductive layer 20 and
the stack insulating layer 18 are sequentially patterned to form a
plurality of gate electrodes 30 crossing the device isolation layer
11. A tunnel oxide layer 22, a charge storage layer 24, and a
blocking insulating layer 26 are sequentially stacked between the
gate electrode 30 and the active region 13. In case sidewalls of
the tunnel oxide layer 22, the charge storage layer 24, and the
blocking insulating layer 26 are damaged by an etch, a defect
density increases with increased trap density around edges of the
tunnel oxide layer 22 and the blocking insulating layer 26. As a
result, it is likely to generate a trap-assisted leakage current to
the gate electrode 30 and the semiconductor substrate 10 through
the high-density trap.
[0008] Referring now to FIG. 4, a thermal oxidation process is
carried out for the semiconductor substrate in order to alleviate
the damage of the sidewalls of the blocking insulating layer 26 and
the gate electrode 30. As a result, a capping insulating layer 32
is formed on a sidewall and a top surface of the gate electrode
30.
[0009] Referring now to FIG. 5, using the gate electrode 30 and the
capping insulating layer 32 as an ion implanting mask, impurities
are implanted into the semiconductor substrate to form an impurity
diffusion layer 34. A sidewall spacer 36 is then formed on
sidewalls of the charge storage layer 24, the blocking insulating
layer 26, and the capping insulating layer 32 that are sequentially
stacked. As illustrated in FIG. 4 and FIG. 5, oxygen atoms are
diffused through an interface between the semiconductor substrate
10 and the tunnel oxide layer 22 during the thermal oxidation
process. At this time, an edge of the tunnel oxide layer 22 becomes
thick (i.e., a bird's beak phenomenon occurs) because it is
oxidized by the diffused oxygen atoms. This leads to a drop in
device operational speed. Furthermore, a trap density becomes high
at the relatively thicker edge of the tunneling oxide layer 22
thereby increasing trap-assisted leakage current through the edge.
As the bird's beak phenomenon causes a thickness variation of a
tunnel oxide layer to be high in a cell array, device
characteristics become non-uniform. The more a gate line width
decreases, the more the thickness of the tunnel oxide layer 22
increases. Therefore, what is needed is a non-volatile memory
device with a structure to overcome device operational
characteristic defects that result from a tunnel oxide layer of
high trap density and from bird's beak phenomenon.
SUMMARY OF THE INVENTION
[0010] A feature of the present invention is to provide a
non-volatile memory device having a conformal tunnel oxide layer
without a bird's beak phenomenon, and to provide a method of
fabricating the same.
[0011] Another feature of the present invention is to provide a
non-volatile memory device that can minimize the influence of
trap-assisted tunneling, and to provide a method of fabricating the
same.
[0012] According to an aspect of the present invention, a
non-volatile memory device includes a charge storage layer and a
gate electrode. The gate electrode crosses an active region between
device isolation layers formed in a semiconductor substrate. The
charge storage layer intervenes between the gate electrode and the
active region. An edge of the charge storage layer extends to form
a protruding part that protrudes from a sidewall of the gate
electrode.
[0013] In a preferred embodiment of the present invention, the
charge storage layer is isolated by the device isolation layer or
is successive under the gate electrode. A blocking insulating layer
intervenes between the gate electrode and the charge storage layer,
and a tunnel oxide layer intervenes between the charge storage
layer and the active region. The non-volatile memory device further
includes a first sidewall spacer on both sidewalls of the gate
electrode. The width of the charge storage layer is preferably
approximately equal to the sum of a width of the gate electrode and
widths of the first sidewall spacers. Further, the non-volatile
memory device may include a second sidewall spacer that covers a
sidewall of the charge storage layer and the first sidewall spacer.
A gate capping insulating layer may intervene between the sidewall
of the gate electrode and the sidewall spacer.
[0014] The non-volatile memory device has a cell array region and a
peripheral circuit region. A first transistor including a wordline
and a stack insulating layer is formed on an active region. The
stack insulating layer comprises a tunnel oxide layer, a charge
storage layer, and a blocking insulating layer and a first
transistor. A second transistor including at least a gate
insulating layer and a gate electrode is formed in the peripheral
region. The first sidewall spacer may be formed on each sidewall of
the gate electrodes in the first and second transistors. Further, a
second sidewall spacer may be formed on the first sidewall spacer
that is formed on each sidewall of the wordline and the gate
electrode.
[0015] According to another aspect of the present invention, a
method of fabricating a non-volatile memory device is provided. A
stack insulating layer is formed on an active region of a
semiconductor substrate. The stack insulating layer comprises at
least first, second, and third insulating layers that are
sequentially stacked. A plurality of gate electrodes crossing the
active region are formed on a semiconductor substrate including the
stack insulating layer. The stack insulating layer is patterned to
form a tunnel oxide layer, a charge storage layer, and a blocking
insulating layer that are sequentially stacked between the gate
electrode and the active region. The tunneling oxide layer, the
charge storage layer, and the blocking insulating layer correspond
to the first, second, and third insulating layers, respectively. An
edge of the charge storage layer has a protruding part that
protrudes from a sidewall of the gate electrode.
[0016] Specifically, the device isolation layer may be formed using
a conventional trench isolation technology. In this case, the stack
insulating layer is formed on an overall surface of a semiconductor
substrate where the device isolation layer is formed. A gate
conductive layer is formed on the stack insulating layer, and then
is patterned to form a gate electrode crossing the active region.
Alternatively, the device isolation layer may be formed using a
self-aligned trench isolation technology. In this case, a stack
insulating layer and a lower gate conductive layer are sequentially
formed on an active region between the device isolation layers. An
upper gate conductive layer is formed on an overall surface of a
semiconductor substrate where the device isolation layer is formed.
Thereafter, the upper and lower gate conductive layers are
sequentially patterned to form the active region crossing the
active region.
[0017] In a preferred embodiment of the present invention, a first
sidewall spacer is formed on a sidewall of the gate electrode so as
to form the protruding part of the charge storage layer. Using the
first sidewall spacer and the gate electrode as an etch mask, at
least the third and second insulating layers are etched to form a
blocking insulating layer protruding from the sidewall of the gate
electrode and a charge storage layer. Alternatively, prior to
formation of the first sidewall spacer, the third insulating layer
exposed to both sides of the gate electrode may be removed. In this
case, the charge storage layer has a protruding part that protrudes
from the sidewall of the gate electrode, and the first sidewall
spacer covers the sidewall of the gate electrode and an upper
portion of the protruding part. Further, a second sidewall spacer
may be formed to cover sidewalls of the charge storage layer and
the first sidewall spacer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a top plan view of a conventional non-volatile
memory device.
[0019] FIG. 2 through FIG. 5 are cross-sectional flow diagrams
showing the steps of fabricating the conventional non-volatile
memory device, taken along a line I-I' of FIG. 1.
[0020] FIG. 6 is a top plan view of a non-volatile memory device
according to first and second embodiments of the present
invention.
[0021] FIG. 7 is a cross-sectional view of the non-volatile memory
device according to the first embodiment, taken along a line II-II'
of FIG. 6.
[0022] FIG. 8 through FIG. 11 are cross-sectional flow diagrams
showing the steps of fabricating the non-volatile memory device
according to the first embodiment, taken along the line II-II' of
FIG. 6.
[0023] FIG. 12 through FIG. 14 are cross-sectional flow diagrams
showing the steps of fabricating the non-volatile memory device
according to the second embodiment, taken along the line II-II' of
FIG. 6.
[0024] FIG. 15 is a top plan view of a non-volatile memory device
according to third and fourth embodiments of the present
invention.
[0025] FIG. 16 is a cross-sectional view of a non-volatile memory
device according to the third embodiment, taken along a line
III-III' of FIG. 15.
[0026] FIG. 17 through FIG. 19 are cross-sectional flow diagrams
showing the steps of fabricating the non-volatile memory device
according to the third embodiment, taken along the line III-III' of
FIG. 15.
[0027] FIG. 20 is a cross-sectional view of a structure according
to the fourth embodiment, taken along the line III-III' of FIG.
15.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0028] The present invention will now be described more fully
hereinafter with reference to the accompanying drawings, in which
preferred embodiments of the invention are shown. The invention
may, however, be embodied in different forms and should not be
construed as limited to the embodiments set forth herein. Rather,
these embodiments are provided so that this disclosure will be
thorough and complete, and will fully convey the scope of the
invention to those skilled in the art. In the drawings, the
thickness of layers and regions are exaggerated for clarity. It
will also be understood that when a layer is referred to as being
"on" another layer or substrate, it can be directly on the other
layer or substrate, or intervening layers may also be present. Like
numbers refer to like elements throughout.
[0029] FIG. 6 is a top plan view illustrating a non-volatile memory
device according to first and second embodiments of the present
invention, in which a region "a" is a cell array region and a
region "b" is a peripheral circuit region. FIG. 7 is a
cross-sectional view illustrating the non-volatile memory device
according to the first embodiment, taken along a line II-II' of
FIG. 6.
[0030] Referring now to FIG. 6 and FIG. 7, a device isolation layer
101 is formed in a predetermined region of a semiconductor
substrate 100. The device isolation layer 101 defines a plurality
of first active regions 103 in the cell array region "a", and a
second active region 203 in the peripheral circuit region "b". A
plurality of wordlines 140 crossing over the first active regions
103 and the device isolation layer 101 are formed in the cell array
region "a". A stack insulating layer intervenes between the
wordlines 140 and the first active regions 103, and includes a
tunnel oxide layer 152, a charge storage layer 154, and a blocking
insulating layer 156 that are sequentially stacked. It is
preferable that the tunnel oxide layer 154, the charge storage
layer 154, and the blocking insulating layer 156 are made of
thermal oxide, silicon nitride, and CVD oxide, respectively. Also,
the blocking insulating layer 156 and the charge storage layer 154
overlap with the wordline 140 to cross over the first active region
103 and the device isolation layer 101. A sidewall of the wordline
140 is covered with a first sidewall spacer.
[0031] Furthermore, a gate capping oxide layer 142 may intervene
between the wordline 140 and the first sidewall spacer 146. A width
of the charge storage layer 154 is larger than that of the wordline
140 at least, so that the blocking insulating layer 156 has a
protruding part 151 protruding from a sidewall of the wordline 140.
Therefore, although a high electric field is applied between the
wordline 140 and the first active regions 103 by a program voltage
or an erase voltage, an electric field applied to the protruding
part 151 is relatively weak. This causes a conspicuous decrease in
a leakage current flowing through a blocking insulating layer 156
and a tunnel oxide layer 152 that are located over and under the
protruding part 151, respectively. As a result, a soft program
characteristic or a data retention characteristic can be
improved.
[0032] The first sidewall spacer 146 covers not only the sidewall
of the wordline 140 but also a top of the protruding part 151. The
second sidewall spacer 146 may cover an outer sidewall of the first
sidewall spacer 148 and a sidewall of the charge storage layer 154.
A first impurity diffusion layer 150 is formed in the first active
region 103 between the wordlines 140. Therefore, a first cell
transistor is formed at an intersection of the wordline 140 and the
first active region 103. In this case, the tunnel oxide layer 152
under the wordline 140 has a uniform thickness. That is, a thick
tunnel oxide layer caused by a bird's beak phenomenon is not formed
at least under an edge of the wordline 140. Thus, a plurality of
first transistors in the cell array region "a" have the equivalent
threshold voltage.
[0033] A gate electrode 240 crossing over the second active region
203 is formed in the peripheral circuit region "b". The first
sidewall spacer 146 covers the gate insulating layer 202 between
the gate electrode 240 and the second active region 203, and a
sidewall of the gate electrode 240. The second sidewall spacer may
cover an outer sidewall of the first sidewall spacer 146. A gate
capping layer 142 may intervene between the fist sidewall spacer
142 and the gate electrode 240. A dual-structured impurity
diffusion layer 254 is formed in the second active region 203 at
both sides of the gate electrode 240. The dual-structured impurity
diffusion layer 254 includes a second impurity diffusion layer 250
and a third impurity diffusion layer 252 that correspond to a
lightly doped impurity diffusion layer and a heavily doped impurity
diffusion layer, respectively.
[0034] FIG. 8 through FIG. 11 are cross-sectional flow diagrams
showing the steps of fabricating a non-volatile memory device
according to a first embodiment of the present invention, taken
along a line II-II' of FIG. 6.
[0035] Referring now to FIG. 8, a device isolation layer 101 is
formed in a semiconductor substrate 100 to define a first active
region 103 and a second active region 203 in a cell array region
"a" and a peripheral circuit region "b", respectively. A stacking
insulating layer 108 and a gate conductive layer 120 are
sequentially formed in a cell array region "a" of a semiconductor
substrate 100 where the device isolation layer 101 is formed. At
the same time, a gate insulating layer 108 and a gate conductive
layer 120 are sequentially formed in a peripheral region "b" of the
semiconductor substrate where the device isolation layer 101 is
formed. Preferably, the stack insulating layer 108 is formed by
sequentially stacking first, second, and third insulating layers
102, 104, and 106. Preferably, the first insulating layer 102 is
made of thermal oxide. Preferably, the first insulating layer has a
thickness of approximately 15 .ANG.-35 .ANG. in order to lower a
program and erase voltages. In this embodiment, it is preferable
that the second insulating layer 104 has a thickness of
approximately 40 .ANG.-100 .ANG., and the third insulating layer
106 has a thickness of approximately 40 .ANG.-120 .ANG.. The gate
conductive layer 120 may be made of polysilicon, or polycide that
is formed by sequentially stacking polysilicon and metal
silicide.
[0036] Referring now to FIG. 9, the gate conductive layer 120 is
patterned to form a plurality of wordlines 140 crossing the first
active regions 103 in the cell array region "a", and to form a gate
electrode 240 at least on the second active region 203 in the
peripheral circuit region "b". The third insulating layer 106
exposed between the wordlines 140 is overetched or attacked by
plasma while etching the gate conductive layer 120. Therefore, a
defect site may be created in the third insulating layer around an
edge of the wordline 140. Subsequently, a trap-to-trap tunneling
may occur through the defect site. Charges stored in a later-formed
charge storage layer are then discharged to a gate electrode,
having an undesirable influence on device operations. Preferably,
in order to overcome the above disadvantages, a thermal oxidation
process is performed for a semiconductor substrate where the
wordline 140 and the gate electrode 240 are formed. Thus, the
damage of the third insulating layer 106 can be alleviated. As a
result, a gate capping oxide layer 142 is formed on sidewalls and
top surfaces of the wordline 140 and the gate electrode 240.
[0037] Referring now to FIG. 10, impurities are implanted into the
first active region 103 between the wordlines 140 to form a first
impurity diffusion layer 150. Also, impurities are implanted into
the second active region 203 at both sides of the gate electrode
240 to form a second impurity diffusion layer 250. Alternatively,
the first and second impurity diffusion layers 150 and 250 may be
formed at the same time or prior to formation of the gate capping
oxide layer 142. Thereafter, a spacer insulating layer 144 is
conformally formed on an entire surface of the resultant structure
in which the first and second impurity diffusion layers 150 and 250
are formed. Preferably, the spacer insulating layer 144 is made of
silicon nitride or oxide.
[0038] Referring now to FIG. 11, the spacer insulating layer 144 is
anisotropically etched to form a first sidewall spacer 146 on
sidewalls of the wordline 140 and the gate electrode 240. If the
spacer insulating layer 144 is made of oxide, the third insulating
layer 106 is also etched during the anisotropic etch to expose the
second insulating layer 104. If the spacer insulating layer 144 is
made of silicon nitride, the third insulating layer 106 is etched
using the wordline 140 and the first sidewall spacer 146 as an etch
mask following formation of the first sidewall spacer 146.
[0039] Using the first sidewall spacer 146 and the gate electrode
140 as an etch mask, at least the second insulating layer 108 is
then etched to form at least second and third insulating layer
patterns 154 and 156 between the wordline 140 and the first active
region 103. Edges of the second and the third insulating layer
patterns 154 and 156 are extended to form a protruding part 151
that protrudes from both sides of the wordline 140. The second
insulating layer patterns 154 correspond to a charge storage layer,
and the third insulating layer pattern 156 intervened between the
wordline 140 and the second insulating layer 154 corresponds to a
blocking insulating layer. The first insulating layer 152 under the
wordline 140 corresponds to a tunnel oxide layer.
[0040] Following formation of the first sidewall spacer 146,
impurities are implanted into the second active region exposed to
both sides of the gate electrode 240 in the peripheral circuit
region "b" to form a third impurity diffusion layer 252.
Subsequently, a dual-structured impurity diffusion layer 254 is
formed in the second active region at both sides of the gate
electrode 240. The third impurity diffusion layer 252 may be formed
before or after formation of the second insulating layer pattern
154.
[0041] Following formation of the third and the second insulating
layer patterns 156 and 154, a second sidewall spacer 148 (see FIG.
7) may further be formed in the cell array region "a" and the
peripheral circuit region "b". In the cell array region "b", the
second sidewall spacer 148 covers sidewalls of the first sidewall
spacer 146, the third insulating layer pattern 156, and the second
insulating layer pattern 154. In the peripheral circuit region "b",
the second sidewall spacer 148 covers the first sidewall spacer
146. If the second sidewall spacer 148 is further formed, the third
impurity diffusion layer 252 may be formed in the second active
region 203 exposed to both sides of the gate electrode 240
following formation of the second sidewall spacer 148.
Alternatively, the first and second impurity diffusion layers 150
and 250 may be formed following the formation of the first sidewall
spacer 146, and the third impurity diffusion layer 252 may be
formed following the formation of the second sidewall spacer
148.
[0042] As a result, a width of the charge storage layer 158 is
equal to the sum of the width of the gate electrode 140 and the
widths of the sidewall spacers 146. In other words, the
non-volatile memory device of the invention has a protruding part
that is formed by extending an edge of the charge storage layer 158
to protrude from a sidewall of the gate electrode 140. Therefore,
even if defect sites are created in insulating layers over/under
the protruding part, device operation characteristics are scarcely
influenced by the defect sites compared with a prior art. Because
an edge of the tunnel oxide layer 152 also protrudes from the gate
electrode 140 wherein a bird's beak phenomenon may occur in
subsequent annealing processes, the non-volatile memory device of
the invention has an excellent data retention characteristic
compared with the prior art.
[0043] FIG. 12 through FIG. 14 are cross-sectional flow diagrams
for explaining the steps of fabricating a non-volatile memory
device according to a second embodiment of the present
invention.
[0044] Referring now to FIG. 12, steps until formation of a gate
conductive layer 120 (see FIG. 8) in the second embodiment are
identical to those in the first embodiment, as described in FIG. 8.
The gate conductive layer 120 and the third insulating layer 106
(see FIG. 8) are sequentially patterned to form a wordline 140 and
a third insulating layer pattern 156a on the second insulating
layer 104 in the cell array region "a" and to form a gate electrode
240 in the peripheral circuit region "b". The third insulating
layer pattern 156 corresponds to a blocking insulating layer.
Furthermore, a thermal oxidation process is carried out for the
semiconductor substrate to form a gate capping oxide layer 142' on
a sidewall and a top surface of the wordline 140 and the gate
electrode 240.
[0045] Referring now to FIG. 13, in the cell array region "a",
impurities are implanted into a first active region 103 between the
wordlines 140 to form a first impurity diffusion layer 150. In the
peripheral circuit region "b", impurities are implanted into a
second active region 203 exposed to both sides of the gate
electrode 240 to form a second impurity diffusion layer 250. A
spacer insulating layer 144 is conformally formed on an entire
surface of a semiconductor substrate 100 where the wordline 140 and
gate electrode 240 are formed. The spacer insulating layer 144 is
made of silicon nitride or oxide.
[0046] Referring now to FIG. 14, the spacer insulating layer 144 is
anisotropically etched to form a first sidewall spacer 146 on
sidewalls of the wordline 140 and the gate electrode 240. If the
spacer insulating layer 144 is made of silicon nitride, the second
insulating layer 104 is also etched to form the first sidewall
spacer 146 and a second insulating layer pattern 154 with a
protruding part 151a protruding from the sidewall of the wordline
140 while anisotropically etching the spacer insulating layer
144.
[0047] If the spacer insulating layer 144 is made of oxide, it is
anisotropically etched to form a first sidewall spacer 146 on the
sidewall of the wordline 140. Using the first sidewall spacer 146
and the gate electrode 140 as an etch mask, the second insulating
layer 104 is then etched to form a second insulating layer pattern
154 with a protruding part 151a protruding from the sidewall of the
gate electrode 140. The second insulating layer pattern 154
corresponds to a charge storage layer. Following formation of the
first sidewall spacer 146, impurities are implanted into the second
active region 203 at both sides of the gate electrode 240 to form a
third impurity diffusion layer 252. As a result, a dual-structured
impurity diffusion layer 254 is formed in the second active region
203 at both sides of the gate electrode 240. The third impurity
diffusion layer 252 may be formed after or before formation of the
second insulating layer pattern 154.
[0048] Following formation of the second insulating layer pattern
154, a second sidewall spacer 148 (see FIG. 7) may further be
formed in the cell array region "a" and the peripheral circuit
region "b". In the cell array region "a", the second sidewall
spacer 148 of FIG. 7 covers the first sidewall spacer 146 and the
sidewalls of the third and second insulating layer pattern 156a and
154. In the peripheral circuit region "b", the second sidewall
spacer 148 of FIG. 7 covers the first sidewall spacer 146. In this
case, the third impurity diffusion layer 252 may be formed in the
second active region 203 at both sides of the gate electrode 240
following formation of the second sidewall spacer 148.
Alternatively, the first and second impurity diffusion layers 150
and 250 may be formed following formation of the first sidewall
spacer 146, and the third impurity diffusion layer 252 may be
formed following the formation of the second sidewall spacer
148.
[0049] As illustrated in the drawings, constructions of the
non-volatile memory devices according to the first and second
embodiments are very similar to each other. A difference
therebetween is that the third insulating layer pattern 156a is
self-aligned to the wordline 140, and thus a width of the third
insulating layer pattern 156a is identical to a width of the
wordline 140. Therefore, the first sidewall spacer 146 covers a
sidewall of the gate electrode 140, a sidewall of the third
insulating layer 156a, and a top surface of the protruding part
151a.
[0050] FIG. 15 is a top plan view illustrating a non-volatile
memory device according to third and fourth embodiments of the
present invention, in which reference numerals "a" and "b" denote a
cell array region and a peripheral circuit region, respectively.
FIG. 16 is a cross-sectional view illustrating a non-volatile
memory device according to a third embodiment of the present
invention, taken along a line III-III' of FIG. 15.
[0051] Referring now to FIG. 15 and FIG. 16, a device isolation
layer 101' is formed in a predetermined area of a semiconductor
substrate 100 to define a plurality of first active regions 103' in
the cell array region "a", and to define a second active region
203' in the peripheral circuit region "b". A plurality of wordlines
183 crossing over the first active regions 103' and the device
isolation layer 101' are formed in the cell array region "a". A
stack insulating layer intervenes between the wordlines 183 and the
first active regions 103', and includes a tunnel oxide layer 162, a
charge storage layer 194, and a blocking insulating layer 196 that
are sequentially stacked. It is preferable that the tunnel oxide
layer 162, the charge storage layer 194, and the blocking
insulating layer 196 are made of thermal oxide, silicon nitride,
and CVD oxide, respectively. A sidewall of the wordline 183 is
covered with a first sidewall spacer 186.
[0052] Furthermore, a gate capping oxide layer 182 may intervene
between the wordline 183 and the first sidewall spacer 186. Since
the charge storage layer 194 and the blocking insulating layer 196
have larger widths than the wordline 183, they have a protruding
part 191 that protrudes from the sidewall of the wordline 183.
Therefore, although a high electric field is applied between the
wordline 183 and the first active region 103' by a program voltage
or an erase voltage, an electric field applied to the protruding
part 191 is weak. As a result, a leakage current flowing through
the blocking insulating layer 196 and the tunnel oxide layer 162
each being formed over and under the protruding part 191 is
considerably reduced to improve a soft program characteristic or a
data retention characteristic.
[0053] The first sidewall spacer 186 covers not only the sidewall
of the wordline 183 but also a top surface of the protruding part
191. Furthermore, a second sidewall spacer 188 (see FIG. 19) may
cover an outer sidewall of the first sidewall spacer 186, a
sidewall of the blocking insulating layer 196, and a sidewall of
the charge storage layer. A first impurity diffusion layer 190 is
formed in the first active region 103' between the wordlines 183.
Therefore, a first cell transistor is formed at an intersection of
the wordline 183 and the first active region 103'. In this case,
the tunnel oxide layer 152 under the wordline 140 has a uniform
thickness. That is, a thick tunnel oxide layer caused by a bird's
beak phenomenon is not formed at least under an edge of the
wordline 183. Thus, a plurality of first transistors in the cell
array region "a" have the equivalent threshold voltage.
[0054] In the peripheral circuit region "b", a gate electrode 283
is formed to cross over the second active region 203. A gate
insulating layer 262 intervenes between the gate electrode 283 and
the second active region 203. A sidewall of the gate electrode 283
is covered with the first sidewall spacer 186. Furthermore, an
outer sidewall of the first sidewall spacer 186 may be covered with
a second sidewall spacer, as described above. The gate capping
oxide layer 182 may intervene between the first sidewall spacer 186
and the gate electrode 283. Dual-structured impurity diffusion
layers 294 are formed in the second active region 203' at both
sides of the gate electrode 283. The dual-structure impurity
diffusion layer 294 includes second and third impurity diffusion
layers 290 and 292. As a result, the impurity diffusion layer 294
corresponds to an LDD-type source/drain region, and the second
impurity diffusion layer 290 and the third impurity diffusion layer
292 correspond to a lightly doped diffusion layer and a heavily
doped impurity diffusion layers, respectively.
[0055] A difference between the first and third embodiments is that
the device isolation layer 101' is formed using a self-aligned
shallow trench technology (S. A. STI). Accordingly, the wordline
183 includes an upper wordline 180 crossing the first active region
103' and a lower wordline 181 intervened between the upper wordline
180 and the first active region 103'. As shown in FIG. 16, the gate
electrode 283 may include a lower gate electrode 281 and an upper
gate electrode 280.
[0056] FIG. 17 through FIG. 19 are cross-sectional flow diagrams
for explaining the steps of fabricating the non-volatile memory
device according to the third embodiment of the present invention,
taken along a line III-III' of FIG. 15.
[0057] Referring now to FIG. 17, a stack insulating layer 168 is
formed on a semiconductor substrate 100. After the stack insulating
layer 168 formed in a peripheral circuit region "b" is removed and
a gate insulating layer 262 is formed, a lower gate conductive
layer 169 and a hard mask layer are formed on an entire surface of
the substrate 100. The hard mask layer, the lower gate conductive
layer 169, the stack insulating layer 168, and the substrate 100 in
a cell array region "a" and the hard mask layer, the lower gate
electrode 169, and the substrate 100 are sequentially patterned to
form a trench in a predetermined area of the substrate 100.
Preferably, the first insulating layer 162 is formed to a thickness
of 15 .ANG.-35 .ANG. in order to make a tunneling of charges even
in low program and erase voltages. As above-mentioned in the first
embodiment, the second insulating layer 164 is preferably made of
silicon nitride to a thickness of 40 .ANG.-100 .ANG., and the third
insulating layer 166 is preferably made of CVD oxide to a thickness
of 40 .ANG.-120 .ANG.. Thereafter, the trench area is filled with
an insulating layer to form a device isolation layer 101', and the
hard mask layer is removed.
[0058] Referring now to FIG. 18, the upper gate conductive layer
170 is formed on an entire surface of a semiconductor substrate 100
where the device isolation layer 101' is formed. The upper gate
conductive layer 170 is preferably made of polysilicon, or polycide
that is formed by sequentially stacking polysilicon and metal
silicide.
[0059] Referring now to FIG. 19, the upper gate conductive layer
170 and the lower gate conductive layer 169 are sequentially
patterned to form a plurality of wordlines 183 crossing the first
active region 103' in the cell array region "a", and to form a gate
electrode 283 crossing the second active region 203' in the
peripheral circuit region "b". In the same manner as the first
embodiment, a first impurity diffusion layer 190 is formed in the
first active region 103' between the wordlines 183, and a second
impurity diffusion layer 290 is formed in the second active region
203' at both sides of the gate electrode 283. A first sidewall
spacer 186 is formed on sidewalls of a wordline 183 and a gate
electrode 283. The wordline 183 includes lower and upper wordlines
181 and 180 that are sequentially stacked, and the gate electrode
283 includes lower and upper gate electrodes 281 and 280. Using the
sidewall spacer 186 and the gate electrode 183 in the cell array
region "a" as an etch mask, at least the third and second
insulating layers 166 and 164 are etched to form third and second
insulating layer patterns 196 and 194 between the gate electrode
183 and each of the active regions 103'.
[0060] An edge of the second insulating layer pattern 194 is
extended to have a protruding part 191 that protrudes from a
sidewall of the gate electrode 183. The second insulating layer
pattern 194 corresponds to a charge storage layer, and the third
insulating layer pattern 196 intervened between the wordline 183
and the second insulating layer pattern 194 corresponds to a
blocking insulating layer. The first insulating layer 162
intervened between the second insulating layer pattern 194 and the
first active region 103' corresponds to a tunnel oxide layer.
Following formation of the first sidewall spacer 186, impurities
are implanted into the second active region 203' at both sides of
the gate electrode 283 in the peripheral circuit region "b" to form
a third impurity diffusion layer 292. Thus, a dual-structured
impurity diffusion layer 294 is formed in the second active region
203' on either side (both sides) of the gate electrode 283. The
third impurity diffusion layer 292 may be formed before or after
formation of the second insulating layer pattern 194.
[0061] Furthermore, a second sidewall spacer 188 may be formed in
the cell array region "a" and the peripheral circuit region "b".
The second sidewall spacer 188 covers not only sidewalls of the
third and second insulating layer patterns 196 and 194 in the cell
array region "a" but also the first sidewall spacer 186 in the
peripheral circuit region "b". In this case, the first and second
impurity diffusion layers 190 and 290 may be formed following
formation of the first sidewall spacer 186. Also, the third
impurity diffusion layer 292 may be formed in the second active
region 203' on either side (both sides) of the gate electrode 283
following formation of the second sidewall spacer 148.
[0062] FIG. 20 is a cross-sectional view illustrating a
non-volatile memory device according to a modified version of the
second embodiment, taken along a line III-III' of FIG. 15.
[0063] Referring now to FIG. 20, in a fourth embodiment of the
invention, a device isolation layer is formed using a self-aligned
shall trench technology (S. A. STI), like the third embodiment.
Steps until formation of the gate conductive layer are identical to
those in the foregoing modified version of the first embodiment.
Subsequent steps are performed in the same manner as the second
embodiment, forming a wordline 183 crossing a first active region
103' in a cell array region "a" of a semiconductor substrate 100
and a gate electrode 283 extended to an upper part of the device
isolation layer 101' in the second active region 203' in the
peripheral circuit region "b". A gate capping oxide layer 182' may
further be formed on sidewalls and top surfaces of wordline 183 and
gate electrode 283. A tunnel oxide layer 162, a charge storage
layer 194, and a blocking insulating layer 196a are sequentially
stacked on the first active region 103' between device isolation
layers 101a, and are intervened between the wordline 183 and the
first active region 103'. The blocking insulating layer 196a is
self-aligned to the wordline 183, so that their widths are
identical to each other.
[0064] A sidewall of the charge storage layer 194 has a protruding
part 191a that protrudes from a sidewall of the gate electrode. A
first sidewall spacer 186 is formed on the sidewall of the wordline
183 and the protruding part 191a of the charge storage layer 194 in
the cell array region "a", and on the sidewall of the gate
electrode 283 in the peripheral circuit region "b". Furthermore,
the second spacer 188 may be formed to cover the first sidewall
spacer 186 and a sidewall of the charge storage layer 194 in the
cell array region "a", and the first sidewall spacer 186 in the
peripheral circuit region "b". A first impurity diffusion layer 190
is formed in the first active region 103' between the wordlines
183, and a dual-structured impurity diffusion layer 294 is formed
in a second active region 203' on either side (both sides) of the
gate electrode 283. The dual-structured impurity diffusion layer
294 includes second and third impurity diffusion layers 290 and
292.
[0065] According to the present invention, an edge of a charge
storage layer is extended to have a protruding part that protrudes
from a sidewall of a gate electrode. With a high defect density,
edges of a blocking insulating layer and a tunnel oxide layer also
protrude from the sidewall of the gate electrode, which results in
a conspicuous decrease in a leakage current flowing through defect
sites in the edges of the blocking insulating layer and the tunnel
oxide layer. Thus, a data retention characteristic can be improved
in comparison with the prior art.
[0066] Furthermore, the invention makes it possible to lessen
deterioration of repeated operation cycle characteristics, and to
form a tunnel oxide layer without a bird's beak under the gate
electrode. Thus, the threshold voltage distribution range of memory
cells can be reduced.
[0067] Those skilled in the art will readily implement the steps
necessary to provide the structures and the methods disclosed
herein, and will understand that the process parameters, materials,
dimensions, and sequence of steps are given by way of example only
and can be varied to achieve the desired structure as well as
modifications that are within the scope of the invention.
Variations and modifications of the embodiments disclosed herein
may be made based on the description set forth herein, without
departing from the spirit and scope of the invention as set forth
in the following claims.
* * * * *