U.S. patent application number 11/159542 was filed with the patent office on 2006-09-14 for multi-plane type flash memory and methods of controlling program and read operations thereof.
This patent application is currently assigned to Hynix Semiconductor Inc.. Invention is credited to Byoung Sung You.
Application Number | 20060203548 11/159542 |
Document ID | / |
Family ID | 36914845 |
Filed Date | 2006-09-14 |
United States Patent
Application |
20060203548 |
Kind Code |
A1 |
You; Byoung Sung |
September 14, 2006 |
Multi-plane type flash memory and methods of controlling program
and read operations thereof
Abstract
A multi-plain type flash memory device comprises a plurality of
plains each including a plurality of memory cell blocks, page
buffers each latching an input data bit to be output to its
corresponding plain or latching an output data bit to be received
from the corresponding plain, cache buffers each storing an input
or output data bits in response to one of cache input control
signals and each transferring the stored data bit to the page
buffer or an external device in response to one of cache output
control signals, and a control logic circuit generating the cache
input and output control signals in response to command and chip
enable signals containing plural bits. The program and read
operations for the plural plains are conducted simultaneously in
response to the chip enable signal containing the plural bits,
which increases an operation speed and data throughput processed
therein.
Inventors: |
You; Byoung Sung;
(Icheon-si, KR) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW, LLP
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Assignee: |
Hynix Semiconductor Inc.
Icheon-si
KR
|
Family ID: |
36914845 |
Appl. No.: |
11/159542 |
Filed: |
June 22, 2005 |
Current U.S.
Class: |
365/185.12 |
Current CPC
Class: |
G11C 16/26 20130101;
G11C 16/10 20130101 |
Class at
Publication: |
365/185.12 |
International
Class: |
G11C 16/04 20060101
G11C016/04; G11C 11/34 20060101 G11C011/34 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 10, 2005 |
KR |
10-2005-0020169 |
Claims
1. A flash memory device comprising: a plurality of plains each
including a plurality of memory cell blocks; a plurality page
buffers, each page buffer arranged in correspondence with one of
the plural plains, each page buffer latching an input data bit to
be output to its corresponding plain or latching an output data bit
to be received from the corresponding plain; a plurality of cache
buffers, each cache buffer arranged in correspondence with one of
the page buffers, each cache buffer storing the input data bit or
the latched output data bit in response to one of cache input
control signals and each cache buffer transferring the stored data
bit to the corresponding page buffer or an external device in
response to one of cache output control signals; and a control
logic circuit generating the cache input and output control signals
in response to command and chip enable signals containing plural
bits.
2. The flash memory device as set forth in claim 1, wherein the
control logic circuit generates one among a program command, a read
command, and an erase command in response to the command signal,
and generates row and column address signals in response to an
external address signal.
3. The flash memory device as set forth in claim 1, wherein the
number of bits of the chip enable signal is identical to the number
of the plains.
4. The flash memory device as set forth in claim 2, further
comprising: a high voltage generator generating bias voltages in
response to one among the program voltage, the read command, and
the erase command; an X-decoder selecting one of the memory cell
blocks included in each of the plains on basis of the row address
signal and supplying the bias voltages to the selected memory cell
block; and a Y-decoder decoding the column address signal and
applying the column address signal to the page buffers, wherein the
page buffers select bitlines of corresponding plains partially or
entirely in response to the column decoding signal, and output the
input data bits to the selected bitlines or latch the output data
bits received from the selected bitlines.
5. The flash memory device as set forth in claim 2, wherein the
control logic circuit generates the program command when the
command signal contains a page program setup code, and disables a
ready/busy signal for a first predetermined time when receiving the
command signal containing a confirmation code after generating the
program command.
6. The flash memory device as set forth in claim 5, wherein the
control logic circuit, after generating the program command,
enables the cache input control signals one by one in sequence for
a second predetermined time when the plural bits are changed into a
predetermined logic value one by one in sequence for the second
predetermined time, and enables the cache output control signals at
the same time while the ready/busy signal is being disabled when
the plural bits are changed into the predetermined logic value at
the same time for the first predetermined time; and wherein the
cache buffers stores the input data bits one by one in sequence
when the cache input control signals are enabled one by one in
sequence, and outputs the stored data bits to the page buffers at
the same time when the cache output control signals are enabled at
the same time.
7. The flash memory device as set forth in claim 6, wherein after
storing the input data bits stored in the last one of the cache
buffers, the plural bits are changed to the predetermined logic
value at the same time for the first predetermined time.
8. The flash memory device as set forth in claim 2, wherein the
control logic circuit generates the read command when the command
signal contains a read code, and disables a ready/busy signal for a
first predetermined time when the external address signal is
received after generating the read command.
9. The flash memory device as set forth in claim 8, wherein the
control logic circuit, after generating the read command, enables
the cache input control signals at the same time while the
ready/busy signal is being disabled, and enables the cache output
control signals one by one in sequence for a second predetermined
time when the plural bits are changed into a predetermined logic
value one by one in sequence for the second predetermined time; and
wherein the cache buffers store the latched output data bits
received from the page buffers when the cache input control signals
are enabled at the same time, and output the stored data bits to
the external device one by one in sequence when the cache output
control signals are enabled one by one in sequence.
10. The flash memory device as set forth in claim 9, wherein the
plural bits are changed into the predetermined logic value when the
control logic circuit receives the command signal, being maintained
in the predetermined logic value when the ready/busy signal is
being disabled.
11. The flash memory device as set forth in claim 9, wherein the
plural bits are changed into the predetermined logic value one by
one in sequence for the second predetermined time after the latched
output data bits are sequentially stored in the cache buffers.
12. A method of controlling a program operation of a multi-plain
type flash memory device, the method comprising: generating a
program command in response to a command signal; storing input data
bits into cache buffers arranged in correspondence with a plurality
of plains; generating bias voltages for the program operation in
response to the program command; selecting one of memory cell
blocks of each of the plural plains according to row and column
address signals; applying the bias voltages to the selected memory
cell block; and outputting data bits stored in the cache buffers to
the plural plains.
13. The method as set forth in claim 12, wherein the
storing-input-data-bits step comprises: enabling cache input
control signals one by one in sequence for a predetermined time in
response to a chip enable signal; storing the input data bits in a
corresponding one of the cache buffers in response to one of the
cache input control signals; and repeating the
enabling-cache-input-control-signals step and storing-the
-input-data-bits step until the input data bits are stored up to
the last one of the cache buffers.
14. The method as set forth in claim 13, wherein the enabling step
comprises: changing bits of the chip enable signal into a
predetermined logic value one by one in sequence for the
predetermined time after generation of the program command.
15. The method as set forth in claim 13, wherein the
storing-input-data-bits step further comprises: changing bits of
the chip enable signal into a predetermined logic value
simultaneously for a predetermined time after the input data bits
are stored up to the last one of the cache buffers.
16. The method as set forth in claim 12, wherein the outputting
step comprises: enabling cache output control signals
simultaneously, when bits of a chip enable signal are changed into
a predetermined logic value simultaneously for a first
predetermined time, for a second predetermined time after
generation of the program command; outputting data bits stored in
the cache buffers to page buffers that are each coupled to at least
one of the cache buffers and arranged in correspondence with the
plural plains, in response to the cache output control signals; and
latching the stored data bits each in the page buffers and
outputting the latched data bits each to the plural plains.
17. A method of controlling a read operation of a multi-plain type
flash memory device, the method comprising: generating a read
command in response to a command signal; generating bias voltages
for the read operation in response to the read command; selecting
one of memory cell blocks of each of the plural plains according to
row and column address signals; applying the bias voltages to the
selected memory cell block; storing output data bits of the plural
plains simultaneously in cache buffers arranged in correspondence
with the plural plains; and outputting data bits stored in the
cache buffers to an external device one by one in sequence.
18. The method as set forth in claim 17, wherein the step of
storing comprises: latching the output data bits in page buffers
arranged in correspondence with the plural plains; enabling cache
input control signals at the same time when a ready/busy signal is
disabled after generation of the read command; and storing the
latched data bits simultaneously in the cache buffers coupled to
the page buffers in response to the cache input control
signals.
19. The method as set forth in claim 18, wherein the step of
enabling comprises: changing bits of the chip enable signal
simultaneously into a predetermined logic value when the read
command is generated and maintaining the bits in the predetermined
logic value while the ready/busy signal is being disabled.
20. The method as set forth in claim 17, wherein the step of
outputting comprises: enabling cache output control signals one by
one in sequence for a predetermined time in response to bits of a
chip enable signal; outputting the data bit, which is stored in
corresponding to one of the cache buffers, to the external device
in response to an enabled one of the cache output control signals;
and repeating the enabling-cache-output-control-signals step and
outputting step until the data bit stored in the last one of the
cache buffers is output to the external device.
21. The method as set forth in claim 20, wherein the step of
enabling further comprises: changing bits of the chip enable signal
into a predetermined logic value one by one in sequence for the
predetermined time after the output data bits are simultaneously
stored in the cache buffers.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] The present application claims priority to Korean Patent
Application No. 10-2005-0020169, filed Mar. 10, 2005, which is
incorporated by reference.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to flash memory devices and
specifically, to a multi-plain type flash memory device and method
of controlling program and read operations thereof.
[0003] Flash memory devices may be generally classified into
single-plain types and multi-plain types in accordance with the
structural configuration of memory cell array thereof. The
single-plain type flash memory device includes a single plain
composed of a plurality of memory cell blocks, while the
multi-plain type flash memory device includes a plurality of plains
each being composed of a plurality of memory cell blocks. FIG. 1 is
a block diagram of a conventional flash memory device, showing the
single-plain type flash memory device. Referring to FIG. 1, the
flash memory device 10 has an input buffer 11, a control logic
circuit 12, a high voltage generator 13, memory cell blocks
B1.about.BK, an X-decoder 14, a Y-decoder 16, and a data
input/output circuit 17. Referring to FIG. 2, it will be described
about a program operation of the flash memory device shown in FIG.
1. FIG. 2 is a timing diagram relevant to a program operation of
the flash memory device shown in FIG. 1. First, a chip enable
signal CEb is disabled and a write enable signal Web is toggled.
Responding to the chip enable signal CEb and the write enable
signal Web, the control logic circuit 12 receives a command signal
CMD1 and an address signal ADD that are successively applied
through the input buffer 11, and then generates a program command
PGM, a row address signal RADD, and a column address signal CADD.
While this, the command signal CMD1 contains a page program setup
code determining an operation mode of the flash memory device 10,
and the address signal ADD corresponds to one of the pages included
in one of the memory cell blocks B1.about.BK.
[0004] The high voltage generator 13 generates bias voltages in
response to the program command PGM and the X-decoder 14 supplies
the bias voltage to one of the memory cell blocks B1.about.BK in
response to the row address signal RADD. The page buffer 15 latches
a data signal D1 received through the data input/output circuit 17
and the Y-decoder 16 and transfers the data signals D1 to bitlines
(not shown) shared by the memory cell blocks B1.about.BK. After
then, the control logic circuit 12 receives another command signal
CMD2 and disables a ready/busy signal R/Bb for a predetermined time
T. The command signal CMD2 contains a confirmation code for
instructing the flash memory to start a program operation therein.
An external controller (not shown) receives the ready/busy signal
R/Bb and identifies the flash memory device in the state of a
program operation. In other words, while the ready/busy signal R/Bb
is being disabled, the program operation is carried out for one
among pages included in one of the memory cell blocks B1.about.BK.
As such, the program operation of the flash memory device 10 is
prosecuted by one page in one time. Therefore, it needs to repeat
the aforementioned procedure in order to complete the program
operation for all of the memory cell blocks B1.about.BK, which
causes the whole program time to be longer due to an increase of
the number of the memory cell blocks.
[0005] In recent, in purpose of reducing the whole program time,
the flash memory device adopts a cache program scheme. In the cache
program scheme, a cache buffer preliminarily stores data to be
programmed next and transfers the stored data to the page buffer in
the program operation, so that the whole program time is shortened.
Thus, it enhances the program speed of the flash memory device by
the cache program scheme. On the other side, there have been
recently proposed various multi-plain type flash memory devices
including a plurality of plains in order to overcome the demerits
of the single-type flash memory device having smaller data
throughput relatively. The multi-plain type flash memory device is
capable of having increased data throughput, but the whole program
time therein increases because the plural plains are programmed in
sequence. In other words, while one of the plains is being
programmed in the unit of page, the rest plains are not programmed.
Therefore, there is a problem that the whole program time of the
multi-plain type flash memory device is longer than the whole
program time of the single-plain flash memory device. Furthermore,
there is the cumbersome that it is required of selecting one of the
plains and generating an address signal by an external memory
controller in addition to a block address in order to program data
in the selected plain or to read data from the selected plain. And,
the flash memory device needs to comprise complicated control
circuits to regulate the plains each by each.
SUMMARY OF THE INVENTION
[0006] The present invention relates to a flash memory device and
improving an operation speed and data throughput by simultaneously
conducting program and read operations for plural plains in
response to a chip enable signal containing plural bits without the
construction of complicated circuits.
[0007] One embodiment of the present invention is directed to
provide a method of controlling program operations in a flash
memory device, capable of improving an operation speed and data
throughput by simultaneously conducting program operations for
plural plains in response to a chip enable signal containing plural
bits without the construction of complicated circuits.
[0008] One embodiment of the present invention is directed also to
provide a method of controlling read operations in a flash memory
device, capable of improving an operation speed and data throughput
by simultaneously conducting read operations for plural plains in
response to a chip enable signal containing plural bits without the
construction of complicated circuits.
[0009] An aspect the present invention is to provide a flash memory
device comprising: a plurality of plains each including a plurality
of memory cell blocks; page buffers arranged in correspondence
respectively with the plural plains, each latching an input data
bit to be output to its corresponding plain or latching an output
data bit to be received from the corresponding plain; cache buffers
arranged in correspondence respectively with the page buffers, each
storing the input data bit or the latched output data bit in
response to one of cache input control signals and each
transferring the stored data bit to the page buffer or an external
device in response to one of cache output control signals; and a
control logic circuit generating the cache input and output control
signals in response to command and chip enable signals containing
plural bits.
[0010] Another aspect of the present invention is to provide a
method of controlling a program operation of a multi-plain type
flash memory device. The method comprises the steps of: generating
a program command in response to a command signal; storing input
data bits into cache buffers arranged in correspondence with a
plurality of plains; generating bias voltages for the program
operation in response to the program command, selecting one of
memory cell blocks of each of the plural plains ob basis of row and
column address signals, and applying the bias voltages to the
selected memory cell block; and outputting data bits stored in the
cache buffers to the plural plains.
[0011] One embodiment of the present invention also provides a
method of controlling a read operation of a multi-plain type flash
memory device, comprising the steps of: generating a read command
in response to a command signal; generating bias voltages for the
read operation in response to the read command, selecting one of
memory cell blocks of each of the plural plains ob basis of row and
column address signals, and applying the bias voltages to the
selected memory cell block; storing output data bits of the plural
plains simultaneously in cache buffers arranged in correspondence
with the plural plains; and outputting data bits stored in the
cache buffers to an external device one by one in sequence.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
example embodiments of the present invention and, together with the
description, serve to explain principles of the present invention.
In the drawings:
[0013] FIG. 1 is a block diagram of a conventional flash memory
device;
[0014] FIG. 2 is a timing diagram relevant to a program operation
of the flash memory device shown in FIG. 1;
[0015] FIG. 3 is a block diagram of a conventional flash memory
device;
[0016] FIG. 4 is a timing diagram relevant to a program operation
of the flash memory device shown in FIG. 3;
[0017] FIG. 5 is a timing diagram relevant to a read operation of
the flash memory device shown in FIG. 3; and
[0018] FIG. 6 is a graphic diagram comparatively illustrating data
throughput processed by the program operation of the present flash
memory device and by a program operation of a single-plain type
flash memory device.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0019] Preferred embodiments of the present invention will be
described below in more detail with reference to the accompanying
drawings. The present invention may, however, be embodied in
different forms and should not be constructed as limited to the
embodiments set forth herein. Rather, these embodiments are
provided so that this disclosure will be thorough and complete, and
will fully convey the scope of the invention to those skilled in
the art. Like numerals refer to like elements throughout the
specification.
[0020] FIG. 3 is a block diagram of a conventional flash memory
device. Referring to FIG. 3, the flash memory device 100 is
comprised of an input buffer 110, a control logic circuit 120, a
high voltage generator 130, an X-decoder 150, a plurality of plains
PL1.about.PLM (M is an integer), a plurality of page buffers
PB1.about.PBM (M is an integer), a plurality of cache buffers
CB1.about.CBM (M is an integer), and a data input/output circuit
160. The input buffer 110 receives and an external address signal
ADD or a command signal (one of CMD1, CMD2, and CMD3), and then
transfers the received signal to the control logic circuit 120. The
control logic circuit 120 receives the command signal (one among
CMD1, CMD2, and CMD3) or the external address signal ADD in
response to the chip enable signal CEb and control signals REb,
Web, ALE, and CLE. Preferably, the chip enable signal CEb contains
bits B1.about.BM (M is an integer). The control logic circuit 120
generates one of a program command PGM, a read command READ, and an
erasure command ERS in response to the command signal CMD1, CMD2,
or CMD3. Preferably, the control logic circuit 120 generates the
program command PGM in response to the command signal CMD1
containing a page program setup code (e.g., 80h). The control logic
circuit 120 generates the read command PGM in response to the
command signal CMD3 containing a read code (e.g., 00h or 01h). The
control logic circuit 120 disables the ready/busy signal R/Bb for a
predetermined time T4 (refer to FIG. 4), after generating the
program command PGM, when receiving the command signal CMD2
including a confirmation code (e.g., 10h). As a result, an external
control unit such as a memory controller (not shown) identifies the
flash memory device 100 in the state of program operation by
receiving the ready/busy signal R/Bb. Further, the control logic
circuit 120 disables the ready/busy signal R/Bb for a predetermined
time D2 (refer to FIG. 5), after generating the read command READ,
when receiving the external address signal ADD. As a result, an
external control unit such as a memory controller (not shown)
identifies the flash memory device 100 in the state of read
operation by receiving the ready/busy signal R/Bb.
[0021] The control logic circuit 120 generates cache input control
signals CIS1.about.CISM (M is an integer) and cache output control
signals COS1.about.COSM (M is an integer) in response to the
command signals CMD1 and CMD2, and the bits B1.about.BM of the chip
enable signal CEb. Describing in more detail, the control logic
circuit 120 enables the cache input control signals CIS1.about.CISM
by one in sequence for the predetermined time T2, after generating
the program command PGM in response to the command signal CMD1,
when the bits B1.about.BM change to their predetermined logic
values one by one in sequence for the predetermined time T2 (refer
to FIG. 4). For instance, the predetermined logic value may be
established in `0`. The control logic circuit 120 enables the cache
output control signals COS1.about.COSM by one in sequence for the
predetermined time T4, after generating the program command PGM,
when the bits B1.about.BM change to the predetermined logic value
simultaneously for the predetermined time T4.
[0022] The control logic circuit 120, after generating the read
command READ in response to the command signal CMD3, enables the
cache output control signals COS1.about.COSM at the same time while
the ready/busy R/Bb is being disabled. Preferably, when the control
logic circuit 120 receives the command signal CMD3, the bits
B1.about.BM are changed to the predetermined logic value and
maintained therein while the ready/busy signal R/Bb is being
disabled. The control logic circuit 120, after generating the read
command READ, enables the cache output control signals
COS1.about.COSM one by one in sequence for a predetermined time D3
when the bits B1.about.BM change into the predetermined logic value
one by one in sequence for the predetermined time D3 (refer to
D3).
[0023] The high voltage generator 130 outputs bias voltages VD, VS,
and VW1.about.VWK (K is an integer) in response to the program
command PGM, the read command READ, and the erasure command ERS.
The VD is a voltage to be supplied to a drain selection line (not
shown), the VS is a voltage to be supplied to a source selection
line (not shown), and the VW1.about.VWK are voltages to be supplied
to wordlines (nor shown). The X-decoder 140 selects one of the
memory cell blocks MB1.about.MBn included in each of the plural
plains PL1.about.PLM and supplies the bias voltages VD, VS, and
VW1.about.VWK to the selected memory cell block, on basis of the
row address signal RADD. Even not shown in FIG. 3, the X-decoder
140 decodes the row address signal RADD to generate row decoding
signals, and selects one of the memory cell blocks MB1.about.MBn in
each of the plural plains PL1.about.PLM on basis of the row
decoding signals. The Y-decoder 150 decodes the column address
signal CADD to generate column decoding signals CDEC and outputs
the column decoding signals CDEC to the page buffers
PB1.about.PBM.
[0024] The page buffers PB1.about.PBM are each arranged in the
plains PL1.about.PLM, connected each to the cache buffers
CB1.about.CBM. The page buffers PB1.about.PBM each latch input data
Di1.about.DiM (M is an integer) received from the cache buffers
CB1.about.CBM corresponding thereto, or select the bitlines (not
shown) of their corresponding plains PL1.about.PLM partially or
wholly in response to the column decoding signals CDEC and then
latch output data Do1.about.DoM (M is an integer) supplied from the
selected bitlines. The page buffers PB1.about.PBM select the
bitlines (nor shown) of their corresponding plains PL1.about.PLM
partially or wholly, and transfers their latched data to the
selected bitlines or to their corresponding cache buffers
CB1.about.CBM, in response to the column decoding signals CDEC.
[0025] The cache buffers CB1.about.CBM store the input
Di1.about.DiM received through the data input/output circuit 160 or
store the output data Do1.about.DoM received from the page buffers
PB1.about.PBM, in response to the cache input control signals
CIS1.about.CISM respectively. Preferably, when the cache input
control signals CIS1.about.CISM are enabled, the cache buffers
CB1.about.CBM store the input data Di1.about.DiM or the output data
Do1.about.DoM, respectively. Further, the cache buffers
CB1.about.CBM output the data Di1.about.DiM or Do1.about.DoM,
stored therein, to an external device through the page buffers
PB1.about.PBM or the data input/output circuit 160, in response to
the cache output control signals COS1.about.COSM. Preferably, the
cache buffers CB1.about.CBM output their stored data Di1.about.DiM
or Do1.about.DoM while the cache output control signals
COS1.about.COSM are being enabled.
[0026] Then, it will be described about the program operation of
the flash memory device 100 with reference to FIGS. 3 and 4. FIG. 4
is a timing diagram of signals relevant to the program operation of
the flash memory device shown in FIG. 3. First, logic values of the
bits B1.about.BM of the chip enable signal CEb are changed into
logic `0` at the initial time. The control signals CLE and ALE are
enabled in sequence and the control signal WEb is toggled. The
control logic circuit 120 receives the command signal CMD1 and
generates the program command PGM, in response to the control
signals CLE and Web. And, the control logic circuit receives the
external address signal ADD in response to the control signals ALE
and WEb, and generates the row address signal RADD and the column
address signal CADD on basis of the external address signal
ADD.
[0027] After then, the logic values of the bits B1.about.BM are
changed into logic `0` in sequence for the predetermined time T2.
One of the logic values of the bits B1.about.BM is set on logic
`0`, the logic values of the rest bits are maintained in logic
`1`.
[0028] The control logic circuit 120 enables the cache input
control signals CIS1.about.CISM one by one in sequence for the
predetermined time T2 in response to the bits B1.about.BM. For
instance, the control logic circuit 120 enables the cache input
control signal CIS1 for the predetermined time T2 when the bit B1
changes to logic `0`. The cache buffers CB1.about.CBM store the
input data Di1.about.DiM one by one in sequence in response to the
cache input control signals CIS1.about.CISM. For instance, the
cache buffer CB1 stores the input data Di1 when the cache input
control signal CIS1 is enabled. As like the cache buffer CB1, the
other cache buffers CB2.about.CBM store the input data
Di2.about.DiM, respectively, when the cache input control signals
CIS2.about.CISM are enabled. After storing the input data
Di1.about.DiM in all of the cache buffers CB1.about.CBM, the logic
values of the bits B1.about.BM are simultaneously changed into
logic `0` for the predetermined time T3. Further, the control logic
circuit 120 receives the command signal CMD2 in response to the
control signals CLE and Web, and disables the ready/busy signal
R/Bb for the predetermined time T4 in response to the command
signal CMD2. The logic control logic circuit 120 enables the cache
output control signals COS1.about.COSM at the same time while the
bits B1.about.BM changes to logic `0` and the ready/busy signal
R/Bb is being disabled. Responding to the cache output control
signals COS1.about.COSM, the cache buffers CB1.about.CBM output the
input data Di1.about.DiM, that are stored therein, to the page
buffers PB1.about.PBM, respectively, at the same time. As a result,
the page buffers PB1.about.PBM latch the input data Di1.about.DiM,
respectively.
[0029] The high voltage generator 130 outputs bias voltages VD, VS,
and VW1.about.VWK in response to the program command PGM. The
X-decoder 140 selects one of the memory cell blocks MB1.about.MBn
included in each of the plains PL1.about.PLM, on basis of the row
address signal RADD. For example, when the X-decoder 140 selects
the memory cell blocks MB1s in each of the plains PL1.about.PLM, it
supplies the bias voltage VD, VS, and VW1.about.VWM to the memory
cell blocks MB1s of the plains PL1.about.PLM. The Y-decoder 150
decodes the column address signal CADD and outputs the column
decoding signal CDEC to the page buffers PB1.about.PBM. The page
buffers PB1.about.PBM select the bitlines of each of the plains
PL1.about.PLM partially or entirely in response to the column
decoding signal CDEC, and then output the latched input data
Di1.about.DiM to the selected bitlines. As a result, the pages
corresponding to the row address signal RADD of the memory cell
blocks MB1s of the plains PL1.about.PLM are programmed at the same
time.
[0030] Next, it will be described about the read operation of the
flash memory device 100 with reference to FIGS. 3 and 5. FIG. 5 is
a timing diagram of signals relevant to the read operation of the
flash memory device shown in FIG. 3. Referring to FIG. 5, first,
logic values of the bits B1.about.BM of the chip enable signal CEb
are changed into logic `0` for a predetermined time D1 at the
initial. The control signals CLE and ALE are enabled in sequence
and the control signal WEb is toggled. The control logic circuit
120 receives the command signal CMD3 and generates the read command
READ, in response to the control signals CLE and WEb. And, the
control logic circuit 120 receives the external address signal ADD
in response to the control signals ALE and Web, and generates the
row address signal RADD and the column address signal CADD on basis
of the external address signal ADD.
[0031] The high voltage generator 130 outputs bias voltages VD, VS,
and VW1.about.VWK in response to the read command READ. The
X-decoder 140 selects one of the memory cell blocks MB1.about.MBn
included in each of the plains PL1.about.PLM, on basis of the row
address signal RADD. For example, when the X-decoder 140 selects
the memory cell blocks MB2s in each of the plains PL1.about.PLM, it
supplies the bias voltage VD, VS, and VW1.about.VWM to the memory
cell blocks MB2s of the plains PL1.about.PLM. The Y-decoder 150
decodes the column address signal CADD and outputs the column
decoding signal CDEC to the page buffers PB1.about.PBM. The page
buffers PB1.about.PBM select the bitlines of each of the plains
PL1.about.PLM partially or entirely in response to the column
decoding signal CDEC, and then latch the output data Do1.about.DoM
received from the selected bitlines. As a result, the pages buffers
latch the output data Do1.about.DoM of pages corresponding to the
row address signal RADD of the memory cell blocks MB2s of the
plains PL1.about.PLM. Thus, data of the pages corresponding to the
row address signal RADD of the memory cell blocks MB2s of the
plains PL1.about.PLM are read at the same time.
[0032] On the other hand, the control logic circuit 120, when the
external address signal ADD is received, disables the ready/busy
signal R/Bb for a predetermined time D2. During this, the control
signal REb is toggling. The logic control logic circuit 120 enables
the cache input control signals CIS1.about.CISM at the same time
while the ready/busy signal R/Bb is being disabled. As a result,
the page buffers PB1.about.PBM store the latched output data
Do1.about.DoM, respectively, in response to the cache input control
signals CIS1.about.CISM.
[0033] Thereafter, the logic values of the bits B1.about.BM are
changed into logic `0` each by each in sequence for a predetermined
time D3. When one of the bits B1.about.BM is set on logic `0`, the
logic values of the rest bits are maintained in logic `1`.
[0034] The control logic circuit 120 disables the cache output
control signals COS1.about.COSM one by one in sequence for the
predetermined time D3 in response to the bits B1.about.BM. For
instance, the control logic circuit 120 enables the cache output
control signal COS1 for the predetermined time D3 when the bit B1
changes to logic `0`. The cache buffers CB1.about.CBM output the
their stored output data Do1.about.DoM through the data
input/output circuit 160 one by one in sequence in response to the
cache output control signals COS1.about.COSM. As a result, the
output data Do1.about.DoM are sequentially output from the data
input/output circuit 160 in sequence.
[0035] FIG. 6 is a graphic diagram comparatively illustrating data
throughput processed by the program operation of the present flash
memory device and by a program operation of a single-plain type
flash memory device. A curve A1 plots the data throughput by the
program operation of the flash memory device according to the
present invention. A curve A2 plots the data throughput by the
program operation of the single-plain type flash memory device
including a cache buffer. And, a curve A3 plots the data throughput
by the program operation of the single-plain type flash memory
device without the cache buffer. The curves A1, A2, and A3
represent the features of data throughput in the condition that a
program time tPROG is 200 .mu.s. As illustrated in FIG. 6, it can
be seen that the data throughput T1 of the flash memory device
according to the present invention is much larger than the data
throughputs of the single-plain type flash memory devices. In more
detail, the following Equation 1 summarizes the data throughput T1
by the program operation of the flash memory device according to
the present invention and the data throughput T2 by the program
operation of the single-plain type flash memory device without the
cache buffer. T .times. .times. 1 = 4 .times. .times. M .times.
tDIN .times. S .times. .times. 4 .times. .times. M .times. +
.times. tPROG .times. S .times. .times. M .times. 4 .times. .times.
( but , tDIN .times. S .times. 4 .times. M < tPROG ) .times.
.times. T .times. .times. 1 = 4 .times. .times. M .times. tDIN
.times. S .times. .times. 4 .times. .times. M .times. + .times.
tPROG .times. S .times. .times. M .times. 4 [ Equation .times.
.times. 1 ] ##EQU1## [0036] where, M is the whole number of pages,
tDIN is tWC (write cycle time) of a page, and TPROG is a program
time.
[0037] As referred to Equation 1, the data throughput by the
program operation of the flash memory device according to the
present invention is larger than the data throughput T2 by the
program operation of the single-plain type flash memory device.
[0038] As described above, the present invention is able to improve
an operation speed and data throughput by simultaneously conducting
program and read operations for plural plains in response to a chip
enable signal containing plural bits without the construction of
complicated circuits.
[0039] Although the present invention has been described in
connection with the embodiment of the present invention illustrated
in the accompanying drawings, it is not limited thereto. It will be
apparent to those skilled in the art that various substitution,
modifications and changes may be thereto without departing from the
scope and spirit of the invention.
* * * * *