U.S. patent application number 11/420736 was filed with the patent office on 2006-09-14 for apparatus and methods for adjusting performance characteristics of circuitry in programmable logic devices.
Invention is credited to Sergey Shumarayev.
Application Number | 20060202713 11/420736 |
Document ID | / |
Family ID | 36076773 |
Filed Date | 2006-09-14 |
United States Patent
Application |
20060202713 |
Kind Code |
A1 |
Shumarayev; Sergey |
September 14, 2006 |
APPARATUS AND METHODS FOR ADJUSTING PERFORMANCE CHARACTERISTICS OF
CIRCUITRY IN PROGRAMMABLE LOGIC DEVICES
Abstract
A programmable logic device (PLD) includes at least one general
PLD circuit and at least one intellectual property (IP) block or
circuit. The PLD further includes a power management circuit. The
power management circuit is configured to control power to the PLD
circuit and to the IP block.
Inventors: |
Shumarayev; Sergey; (San
Leandro, CA) |
Correspondence
Address: |
LAW OFFICES OF MAXIMILIAN R. PETERSON
P.O. BOX 93005
AUSTIN
TX
78709-3005
US
|
Family ID: |
36076773 |
Appl. No.: |
11/420736 |
Filed: |
May 27, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11006420 |
Dec 7, 2004 |
|
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11420736 |
May 27, 2006 |
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Current U.S.
Class: |
326/38 |
Current CPC
Class: |
G06F 2119/12 20200101;
G06F 30/34 20200101; H03K 19/0016 20130101; H01L 2924/00 20130101;
H01L 2924/0002 20130101; H01L 2924/0002 20130101; H03K 19/00369
20130101; H03K 19/17784 20130101; H03K 19/17748 20130101; H03K
19/17792 20130101; H03K 19/17732 20130101 |
Class at
Publication: |
326/038 |
International
Class: |
H03K 19/173 20060101
H03K019/173 |
Claims
1. A PLD, comprising: at least one PLD circuitry; at least one IP
block; and a power management circuit configured to control power
provided to the at least one PLD circuitry and to the at least one
IP block.
2. The PLD according to claim 1, wherein the at least one PLD
circuitry comprises programmable logic.
3. The PLD according to claim 1, wherein the at least one PLD
circuitry comprises programmable interconnect.
4. The PLD according to claim 1, wherein the at least one PLD
circuitry receives power from a first supply.
5. The PLD according to claim 4, wherein the at least one IP block
receives power from a second supply.
6. The PLD according to claim 5, wherein the first and second
supplies each comprise a regulator integrated within the PLD.
7. The PLD according to claim 1, wherein the power management
circuit is further configured to control whether the at least one
IP block receives power.
8. The PLD according to claim 1, wherein the power management
circuit is further configured to control a level of a power supply
voltage.
9. The PLD according to claim 1, wherein the at least one IP block
comprises analog circuitry.
10. The PLD according to claim 1, wherein the at least one IP block
comprises mixed-signal circuitry.
11. The PLD according to claim 1, wherein the at least one IP block
comprises HSSI circuitry.
12. The PLD according to claim 1, wherein the HSSI circuitry
comprises a PMA circuit, a PCS circuit, and a MAC circuit.
13. A method of adjusting performance of a PLD, the method
comprising: determining whether the PLD meets a first performance
characteristic; adjusting a body bias level of at least a part of
the PLD to a first level according to whether the PLD meets the
first performance characteristic; determining whether the PLD meets
a second performance characteristic; and characterizing the PLD
depending on whether the PLD fails to meet the second performance
characteristic.
14. The method according to claim 13, further comprising burning at
least one fuse in the PLD according to whether the PLD meets the
first performance characteristic.
15. The method according to claim 14, wherein burning at least one
fuse in the PLD comprises burning the at least one fuse according
to the first level.
16. The method according to claim 13, further comprising adjusting
the body bias level of at least a part of the PLD to a second
level, while monitoring leakage, until a desired performance
characteristic is met.
17. The method according to claim 16, further comprising
characterizing the PLD and burning at least one fuse in the PLD
according to the second level.
18. A method of adjusting performance of a PLD used to implement a
user's design, wherein the PLD comprises a set of IP blocks, the
method comprising: determining whether all IP blocks in the set of
IP blocks are used, and selectively disabling provision of power to
unused IP blocks; determining whether the user's design is to meet
performance specifications of a standard; and controlling a level
of power provided to at least one IP block in the set of IP blocks
depending on whether the user's design is to meet performance
specifications of the standard.
19. The method according to claim 18, wherein controlling the level
of power provided to the at least one IP block in the set of IP
blocks comprises providing power so as to meet the performance
specifications of the standard, and disabling any unused IP blocks
in the set of IP blocks.
20. The method according to claim 18, wherein controlling the level
of power provided to the at least one IP block in the set of IP
blocks comprises: determining at least one power level
corresponding to the performance specifications of the standard;
providing power so as to meet the performance specifications of the
standard; and disabling any unused IP blocks in the set of IP
blocks.
21. A method of adjusting performance of a PLD, the method
comprising: sorting the PLD according to its performance
capability; determining whether any circuit blocks in the PLD
inhibit the PLD from meeting desired performance characteristics;
and adjusting a body bias level within the PLD if the any circuit
blocks in the PLD inhibit the PLD from meeting the desired
performance characteristics.
22. The method according to claim 21, further comprising re-sorting
the PLD.
23. The method according to claim 22, further comprising
re-adjusting the body bias level.
24. The method according to claim 21, further comprising adjusting
a supply voltage provided to a circuit within the PLD.
25. The method according to claim 24, wherein the circuit comprises
an IP block.
26. The method according to claim 24, further comprising
determining whether the PLD meets the desired performance
characteristics.
27. The method according to claim 26, further comprising
characterizing a device grade of the PLD.
28. A method of adjusting performance of a PLD during operation of
the PLD, the method comprising: monitoring at least one performance
characteristics of the PLD; determining whether the at least one
performance characteristic of the PLD exceeds a desired performance
characteristic; and disabling power to at least one IP block within
the PLD if the at least one performance characteristic of the PLD
exceeds the desired performance characteristic.
29. The method according to claim 28, further comprising adjusting
a supply voltage provided to the ate least one IP block.
30. The method according to claim 28, further comprising adjusting
a supply voltage provided to the ate least one IP block rather than
disabling power to the at least one IP block if the at least one
performance characteristic of the PLD exceeds the desired
performance characteristic.
31. The method according to claim 30, wherein the at least one IP
block comprises HSSI circuitry.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part application of
U.S. patent application Ser. No. 11/006,420, titled "Apparatus and
Methods for Adjusting Performance Characteristics of Programmable
Logic Devices," Attorney Docket No. ALTR:042, filed on Dec. 7,
2004, and incorporated here in its entirety.
TECHNICAL FIELD
[0002] The inventive concepts relate generally to adjusting the
performance of programmable logic devices (PLDs). More
particularly, the invention concerns adjusting the supply
voltage/power consumption of PLDs, as well as noise reduction and
isolation in PLDs.
BACKGROUND
[0003] PLDs are ubiquitous electronic devices that provide
flexibility to not only designers, but also end-users. During the
design cycle of an electronic circuit or system, a designer may
perform a relatively large number of design iterations by simply
re-programming the PLD for each design. Thus, the length and
expense of the design cycle decreases compared to other
alternatives. Similarly, the end-user may have a desired level of
control over the functionality of a design that includes PLD(s). By
programming the PLD(s) in the field or even on a real-time basis,
the user can change the way the circuit or system behaves.
[0004] To accommodate increasingly complex designs, modern PLDs
include a relatively large number of transistors. Furthermore,
users demand ever higher performance, which results in larger
operating frequencies. Consequently, the power consumption, power
dissipation, die temperatures and, hence, power density (power
dissipation in various circuits or blocks), of PLDs has tended to
increase. The upward march of the power density, however, may make
PLDs design and implementation impractical or failure-prone. A need
exists for PLDs that feature adjustable performance, such as
adjustable power consumption in various PLD blocks and
circuits.
SUMMARY
[0005] The disclosed concepts relate to the management and control
of power consumption, the provision of power to various blocks and
circuits in PLDs, and the performance of those blocks and circuits
and therefore the PLD overall. In one illustrative embodiment, a
PLD includes at least one IP block and at least one PLD circuit.
The PLD further includes a power management circuit. The power
management circuit is configured to control the power provided to
the PLD circuit and the at least one IP block.
[0006] In another exemplary embodiment, a method of adjusting
performance of a PLD includes determining whether the PLD meets a
performance characteristic, and adjusting a body bias level of at
least a part of the PLD to a prescribed or desired level, according
to whether the PLD meets the performance characteristic. The method
also includes determining whether the PLD meets another performance
characteristic, and characterizing the PLD depending on whether the
PLD fails to meet that performance characteristic.
[0007] In a third exemplary embodiment, a method of adjusting
performance of a PLD that is used to implement a user's design. The
PLD includes a set of IP blocks. The method includes determining
whether all IP blocks in the set of IP blocks are used, and
selectively disabling provision of power to any unused IP blocks.
The method further includes determining whether the user's design
is to meet performance specifications of a standard, and
controlling a level of power provided to at least one of the IP
blocks, depending on whether the user's design should meet the
performance specifications of the standard.
[0008] In a fourth exemplary embodiment, a method of adjusting
performance of a PLD includes sorting the PLD according to its
performance capability, and determining whether any circuit blocks
in the PLD inhibit the PLD from meeting desired performance
characteristics. The method further includes adjusting a body bias
level within the PLD if the any circuit blocks in the PLD inhibit
the PLD from meeting the desired performance characteristics.
[0009] Moreover, in a fifth illustrative embodiment, a method of
adjusting performance of a PLD during operation of the PLD includes
monitoring at least one performance characteristics of the PLD, and
determining whether the at least one performance characteristic of
the PLD exceeds a desired performance characteristic. The method
further includes disabling power to at least one IP block within
the PLD if the at least one performance characteristic of the PLD
exceeds the desired performance characteristic.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The appended drawings illustrate only exemplary embodiments
of the invention and therefore should not be considered as limiting
its scope. Persons of ordinary skill in the art who have the
benefit of the description of the invention appreciate that the
disclosed inventive concepts lend themselves to other equally
effective embodiments. In the drawings, the same numeral
designators used in more than one drawing denote the same, similar,
or equivalent functionality, components, or blocks.
[0011] FIG. 1 shows a general block diagram of a PLD according to
an illustrative embodiment of the invention.
[0012] FIG. 2 illustrates a floor-plan of a PLD according to an
exemplary embodiment of the invention.
[0013] FIG. 3 depicts a block diagram of an exemplary embodiment of
programmable logic in a PLD according to the invention.
[0014] FIG. 4 shows a circuit arrangement for adjusting the supply
voltage of a desired circuit in a PLD according to an exemplary
embodiment of the invention.
[0015] FIG. 5 illustrates another circuit arrangement for adjusting
the supply voltage of a desired circuit in a PLD according to an
exemplary embodiment of the invention.
[0016] FIG. 6 depicts a circuit arrangement for reducing the noise
level in a PLD according to an exemplary embodiment of the
invention.
[0017] FIG. 7 shows another circuit arrangement for reducing the
noise level in a PLD according to an exemplary embodiment of the
invention.
[0018] FIG. 8 illustrates an arrangement for providing a flexible
mechanism for adjusting the performance of the various parts of a
PLD according to an exemplary embodiment of the invention.
[0019] FIGS. 9A-9C depict circuit arrangements for distributing and
generating power supply voltages in PLDs according to exemplary
embodiments of the invention.
[0020] FIG. 10 shows an example of using n-wells to isolate
noise-sensitive circuits in a PLD according to an illustrative
embodiment of the invention.
[0021] FIG. 11 illustrates various software modules that PLD
computer-aided design (CAD) software according to illustrative
embodiments of the invention uses.
[0022] FIG. 12 depicts a flow diagram for a PLD CAD software
according to an exemplary embodiment of the invention.
[0023] FIG. 13 shows a block diagram of circuitry within a PLD
according to exemplary embodiments of the invention to adjust,
program, or set the supply voltage levels of desired parts of the
PLD.
[0024] FIG. 14 illustrates a circuit arrangement according to
exemplary embodiments of the invention for adjusting supply voltage
levels within a PLD in response to an external source.
[0025] FIG. 15 depicts a circuit arrangement for adjusting supply
voltage level(s) within a PLD according to exemplary embodiments of
the invention.
[0026] FIG. 16 shows a simplified block diagram of an exemplary
embodiment of the invention for adjusting the performance of
circuitry within the PLD, including IP block(s).
[0027] FIG. 17 illustrates a simplified block diagram of another
exemplary embodiment of the invention for adjusting the performance
of circuitry within the PLD, including IP block(s).
[0028] FIG. 18 depicts a simplified block diagram of an
illustrative embodiment according to the invention for adjusting
the performance of IP block(s) in PLDs.
[0029] FIG. 19 shows a simplified block diagram of an illustrative
embodiment according to the invention for adjusting the performance
of a particular IP block.
[0030] FIGS. 20-23 illustrate simplified flow diagrams for methods
according to various aspects of the invention for adjusting the
performance of PLDs that include IP block(s).
DETAILED DESCRIPTION
[0031] The inventive concepts contemplate apparatus and associated
methods for PLDs that feature adjustable supply voltage (and,
hence, power consumption and performance), reduced noise levels,
and noise isolation. The inventive concepts help to overcome
excessive power density levels that conventional PLDs suffer.
Moreover, one may adjust the performance level of a desired
portion, circuit, or block (or all circuits and blocks), of a PLD
according to the invention. Put another way, one may adjust the
performance by programming the supply voltage and the attendant
power dissipation of the circuitry within the PLD with a desired
level of granularity, ranging from individual circuit blocks, all
the way to the entire PLD circuitry.
[0032] More specifically, and as described below in detail, the
inventive concepts contemplate controlling the supply voltage and
power consumption of one or more circuits or blocks of circuits
within the PLD by using a variable impedance circuit. In addition,
one may use the variable impedance circuit to form a filter that,
simultaneously with the adjustment of the power consumption, tend
to reduce the noise levels present within the PLD. The reduced
noise levels help to protect sensitive circuitry within the PLD
from adverse effects of electrical noise. Furthermore, one may
protect noise-sensitive circuitry within the PLD by using deep
n-well structures within the PLD that help to isolate the sensitive
circuitry from sources of electrical noise.
[0033] The inventive concepts provide the following benefits over
traditional implementations. First, they allow trading off
performance and power consumption or optimizing the
performance-power consumption tradeoff. Second, one may selectively
set, program, or adjust the supply voltage and power consumption in
critical circuit paths or parts of the PLD so as to increase their
performance as desired. Conversely, one may selectively set,
program, or adjust the supply voltage and power consumption in
non-critical circuit paths or parts of the PLD to levels
commensurate with their desired performance.
[0034] One may also employ the inventive concepts to prevent (or
reduce the probability of) thermal runaway. More specifically, in a
traditional PLD, circuits operating at relatively high speeds tend
to consume more power, resulting in temperature increase of the
PLD. The increased power consumption may in turn cause those
circuits to consume more power. This positive feedback mechanism
may increase the power densities to unsafe or destructive levels.
In PLDs according to the invention, one may adjust or control the
supply voltage and power consumption levels of various blocks and,
hence, reduce the likelihood of thermal runaway. Furthermore, the
inventive concepts help to provide better performance by reducing
the noise levels within the PLD and to isolate noise-sensitive
circuitry from the undesirable effects of noise.
[0035] FIG. 1 shows a general block diagram of a PLD 103 according
to an illustrative embodiment of the invention. PLD 103 includes
configuration circuitry 130, configuration memory 133, control
circuitry 136, programmable logic 106, programmable interconnect
109, and I/O circuitry 112. In addition, PLD 103 may include
test/debug circuitry 115, one or more processors 118, one or more
communication circuitry 121, one or more memories 124, one or more
controllers 127, as desired.
[0036] Note that FIG. 1 shows a simplified block diagram of PLD
103. Thus, PLD 103 may include other blocks and circuitry, as
persons of ordinary skill in the art understand. Examples of such
circuitry include clock generation and distribution circuits,
redundancy circuits, and the like. Furthermore, PLD 103 may
include, analog circuitry, other digital circuitry, and/or
mixed-mode or mixed-signal circuitry, as desired.
[0037] Programmable logic 106 includes blocks of configurable or
programmable logic circuitry, such as look-up tables (LUTs),
product-term logic, multiplexers, logic gates, registers, memory,
and the like. Programmable interconnect 109 couples to programmable
logic 106 and provides configurable interconnects (coupling
mechanisms) between various blocks within programmable logic 106
and other circuitry within or outside PLD 103.
[0038] Control circuitry 136 controls various operations within PLD
103. Under the supervision of control circuitry 136, PLD
configuration circuitry 130 uses configuration data (which it
obtains from an external source, such as a storage device, a host,
etc.) to program or configure the functionality of PLD 103. The
configuration data typically reside in configuration memory 133.
The configuration data determine the functionality of PLD 103 by
programming programmable logic 106 and programmable interconnect
109, as persons skilled in the art with the benefit of the
description of the invention understand.
[0039] I/O circuitry 112 may constitute a wide variety of I/O
devices or circuits, as persons of ordinary skill in the art who
have the benefit of the description of the invention understand.
I/O circuitry 112 may couple to various parts of PLD 103, for
example, programmable logic 106 and programmable interconnect 109.
I/O circuitry 112 provides a mechanism and circuitry for various
blocks within PLD 103 to communicate with external circuitry or
devices.
[0040] Test/debug circuitry 115 facilitates the testing and
troubleshooting of various blocks and circuits within PLD 103.
Test/debug circuitry 115 may include a variety of blocks or
circuits known to persons of ordinary skill in the art who have the
benefit of the description of the invention. For example,
test/debug circuitry 115 may include circuits for performing tests
after PLD 103 powers up or resets, as desired. Test/debug circuitry
115 may also include coding and parity circuits, as desired.
[0041] As noted above, PLD 103 may include one or more processors
118. Processor 118 may couple to other blocks and circuits within
PLD 103. Processor 118 may receive data and information from
circuits within or external to PLD 103 and process the information
in a wide variety of ways, as persons skilled in the art with the
benefit of the description of the invention appreciate. One or more
of processor(s) 118 may constitute a digital signal processor
(DSP). DSPs allow performing a wide variety of signal processing
tasks, such as compression, decompression, audio processing, video
processing, filtering, and the like, as desired.
[0042] PLD 103 may also include one or more communication circuitry
121. Communication circuitry 121 may facilitate data and
information exchange between various circuits within PLD 103 and
circuits external to PLD 103, as persons of ordinary skill in the
art who have the benefit of the description of the invention
understand. As an example, communication circuitry 121 may provide
various protocol functionality (e.g., Transmission Control
Protocol/Internet Protocol (TCP/IP), User Datagram Protocol (UDP)
etc.), as desired. As another example, communication circuitry 121
may include network (e.g., Ethernet, token ring, etc.) or bus
interface circuitry, as desired.
[0043] PLD 103 may further include one or more memories 124 and one
or more controller(s) 127. Memory 124 allows the storage of various
data and information (such as user-data, intermediate results,
calculation results, etc.) within PLD 103. Memory 124 may have a
granular or block form, as desired. Controller 127 allows
interfacing to, and controlling the operation and various functions
of circuitry outside the PLD. For example, controller 127 may
constitute a memory controller that interfaces to and controls an
external synchronous dynamic random access memory (SDRAM), as
desired.
[0044] In addition to the circuitry that FIG. 1 shows, PLD 103 may
include analog or mixed-mode or mixed-signal circuitry 139,
sometimes known as analog or mixed-mode or mixed-signal IP blocks
(e.g., blocks of circuits, modules, sub-modules, sub-circuits,
groups of transistors, etc.). For example, PLD 103 may include
amplifiers, digital-to-analog converters, analog-to-digital
converters, filters, and the like. By their nature,
analog/mixed-mode circuits tend to exhibit sensitivity to noise. As
described below in detail, the inventive concepts help to isolate
noise-sensitive circuitry from noise-generating circuitry.
Furthermore, the inventive concepts include techniques that tend to
reduce the noise levels present in PLDs.
[0045] FIG. 2 shows a floor-plan of a PLD 103 according to an
exemplary embodiment of the invention. PLD 103 includes
programmable logic 106 arranged as a two-dimensional array.
Programmable interconnect 109, arranged as horizontal interconnect
and vertical interconnect, couples the blocks of programmable logic
106 to one another.
[0046] One may adjust the supply voltage and, hence, the power
dissipation level, of each block of programmable logic 106, each
segment of programmable interconnect 109, or both, as desired.
Furthermore, one may adjust the supply voltage and the power
dissipation level of a portion of one or more blocks of
programmable logic 106, a portion of programmable interconnect 109,
or both, as desired.
[0047] In illustrative embodiments, PLDs according to the invention
have a hierarchical architecture. In other words, each block of
programmable logic 106 in FIG. 2 may in turn include smaller or
more granular programmable logic blocks or circuits. One may adjust
the supply voltage and power consumption or dissipation in each
level of the hierarchical architecture of the PLD, as desired.
[0048] FIG. 3 shows a block diagram of an exemplary embodiment of
programmable logic 106 in a PLD according to the invention.
Programmable logic 106 includes logic elements or programmable
logic circuits 250, local interconnect 253, interface circuit 256,
and interface circuit 259. Logic elements 250 provide configurable
or programmable logic functions, for example, LUTs, registers,
product-term logic, etc., as persons of ordinary skill in the art
who have the benefit of the description of the invention
understand. Local interconnect 253 provides a configurable or
programmable mechanism for logic elements 250 to couple to one
another or to programmable interconnect 109 (sometimes called
"global interconnect"), as desired.
[0049] Interface circuit 256 and interface circuit 259 provide a
configurable or programmable way for programmable logic 106 block
of circuitry to couple to programmable interconnect 109 (and hence
to other programmable logic 106, as FIG. 2 shows). Interface
circuit 256 and interface circuit 259 may include multiplexers
(MUXs), registers, buffers, drivers, and the like, as persons of
ordinary skill in the art who have the benefit of the description
of the invention understand.
[0050] One may adjust the supply voltage and power consumption of
each portion or block of circuitry within PLD 103 (see FIGS. 1-3),
as desired. Furthermore, one may adjust the supply voltage and
power consumption of each portion or block of circuitry
independently of others, on an individual or collective basis, as
desired. Within each portion or block of circuitry, one may adjust
the supply voltage and power consumption of each sub-block, or
groups of sub-blocks, as desired.
[0051] For example, one may adjust the supply voltage and power
consumption of all or a portion of the following circuitry within a
PLD according to exemplary embodiments of the invention: one or
more of the blocks in FIG. 1 (e.g., programmable logic 106,
programmable interconnect 109, etc.); one or more logic elements
250 within one or more programmable logic blocks 106; one or more
interface circuits 256 and/or 259, within one or more programmable
logic blocks 106; one or more local interconnect within one or more
programmable logic 106; and one or more MUXs, drivers, buffers,
etc., within one or more interface circuits 256 and/or 259.
[0052] As noted above, one may make the supply voltage and power
consumption adjustments in any desired level of granularity. In
other words, one may make the adjustments applicable to sub-blocks,
blocks, regions, or the entire PLD, as desired, and as applicable.
For example, one may make supply voltage and power consumption
adjustments to one or more of such elements of the PLD
independently of one or more of other elements within the PLD, as
desired. As persons of ordinary skill in the art with the benefit
of the description of the invention understand, one may adjust the
supply voltage and power consumption of some parts of a PLD and yet
provide a fixed or default supply voltage and power consumption for
other parts of the PLD, as desired.
[0053] FIG. 4 shows a circuit arrangement for adjusting the supply
voltage and, hence, the power consumption of a desired circuit in a
PLD according to an exemplary embodiment of the invention. More
specifically, the circuit arrangement in FIG. 4 shows a controlled
PLD circuit 300 that includes control circuit 303, PLD circuit 306,
and variable impedance device 309.
[0054] The circuit operates as follows: In response to one or more
signals not shown explicitly in FIG. 4 (such as a bias signal and
configuration signals, described in connection with FIG. 13)
circuit 303 applies a corresponding control signal (or signals,
depending on the nature of variable impedance device 309) so as to
cause adjustment of the supply voltage that variable impedance
device 309 provides to PLD circuit 306. Consequently, control
circuit 303 can cause the adjustment of the power consumption (and
other performance criteria, such as operating speed) of PLD circuit
306.
[0055] Variable impedance device 309 couples the supply voltage,
V.sub.DD, to PLD circuit 306. When variable impedance device 309
has a relatively high impedance, PLD circuit 306 conducts
relatively little current, and has a nearly zero supply voltage.
Thus, PLD circuit 306 effectively shuts down or enters an OFF state
or sleep mode. In this state, PLD circuit 306 consumes nearly zero
power.
[0056] At the other extreme, when variable impedance device 309 has
a relatively low impedance, PLD circuit 306 receives nearly the
voltage V.sub.DD as its supply voltage (minus any drop across
variable impedance device 309). In this state, PLD circuit 306
typically has higher power consumption, but also higher speed.
Thus, by varying the effective supply voltage of PLD circuit 306
between the two extremes of near-zero and near-VDD supply voltages,
one may trade off its various performance measures, such as power
consumption and speed.
[0057] PLD circuit 306 may constitute any desired region, block,
circuitry, sub-block, or collection of each of those parts, of a
PLD. For example, PLD circuit 306 may constitute one or more of the
elements shown in FIGS. 1-3, such as programmable interconnect 109,
logic elements 250, etc., as desired.
[0058] As described below in detail, control circuit 303 may
operate under the supervision of one or more other parts of the
PLD, or under the control of an external source, or a combination
of internal and external sources, as desired. Control circuit 303
causes the impedance of the variable impedance device to change. As
a result, the effective supply voltage provided to PLD circuit 306
varies. The effective supply voltage of PLD circuit 306 affects its
characteristics, such as operating speed, power consumption, and
the like. By adjusting the supply voltage level for PLD circuit
306, one may trade off its various characteristics, such as speed
versus power consumption.
[0059] Variable impedance device 309 may constitute a desired type
of device, depending on factors such as the particular PLD
implementation, circuit and process technology, and the like, as
persons of ordinary skill in the art who have the benefit of the
description of the invention understand. As one example, variable
impedance device 309 may constitute a transistor.
[0060] FIG. 5 illustrates another circuit arrangement for adjusting
the supply voltage of a desired circuit in a PLD according to an
exemplary embodiment of the invention. The circuit arrangement in
FIG. 5 is similar to the circuit in FIG. 4. FIG. 5, however, uses a
transistor 320 and, more particularly, a metal oxide semiconductor
field effect transistor (MOSFET) transistor, as a particular type
of variable impedance device.
[0061] Depending on factors such as the particular PLD
implementation, circuit and process technology, and the like, as
persons of ordinary skill in the art who have the benefit of the
description of the invention understand, transistor 320 may
constitute a variety of devices, such as bipolar junction
transistors (BJTs), bipolar hetero-junction transistor (BHT), and
the like.
[0062] In one embodiment implemented using metal oxide
semiconductor (MOS) or complementary MOS (CMOS) technology,
transistor 320 may constitute a native transistor, as desired.
Native transistors may have a negative or small threshold voltage,
V.sub.T, thus making biasing or driving transistor 320 easier in
situations where a relatively small V.sub.DD results in a small
headroom in the output voltage of control circuit 303.
[0063] As noted above, PLDs according to the invention may include
noise-sensitive analog or mixed-mode or mixed-signal circuitry. One
may use filtering techniques to help reduce the overall noise in
the PLD or the noise level that the analog or mixed-mode circuitry
experiences.
[0064] FIG. 6 depicts a circuit arrangement for reducing the noise
level in a PLD according to an exemplary embodiment of the
invention. Controlled PLD circuit 300 in FIG. 6 is analogous to the
circuit shown in FIG. 4, and provides similar benefits. Thus, the
circuitry in FIG. 6 provides the capability of controlling the
supply voltage and, hence, the performance, of PLD circuit 306, as
described above in detail. In the circuit of FIG. 6, PLD circuit
306 constitutes a circuit with relatively high sensitivity to
noise, such as an analog or mixed-mode circuit.
[0065] In addition to the elements shown in FIG. 4, the circuit
arrangement in FIG. 6 includes capacitor 323 and capacitor 326.
Together with various impedances present in the circuit, each of
those capacitors forms a filter. For example, capacitor 326,
together with the parallel impedance of variable impedance device
309 and PLD circuit 306, forms a low-pass filter. By filtering
higher frequencies, the low-pass filters tend to reduce the overall
noise level that PLD circuit 306 experiences. Note that one may
omit one of capacitors 323 and 326, depending on factors such as
the desired level of filtering, the size and value of components,
and the like, as persons of ordinary skill in the art who have the
benefit of the description of the invention understand.
[0066] FIG. 7 shows another circuit arrangement for reducing the
noise level in a PLD according to an exemplary embodiment of the
invention. The circuit arrangement in FIG. 7 constitutes a more
specific implementation of the circuit in FIG. 6. More
specifically, rather than a general variable impedance device 309
in FIG. 6, the circuit arrangement in FIG. 7 uses transistor 320.
Transistor 320 may generally constitute any of the devices
described above with respect to FIG. 5, as desired. Note that, as
described above, one may omit one of capacitors 323 and 326,
depending on factors such as the desired level of filtering, the
size and value of components, and the like, as persons of ordinary
skill in the art who have the benefit of the description of the
invention understand.
[0067] Using controlled PLD circuit 300 described above, one may
adjust the supply voltage and power consumption and thus
performance of various parts of PLDs. FIG. 8 shows an arrangement
for providing a flexible mechanism for adjusting the performance of
the various parts of a PLD 103 according to an exemplary embodiment
of the invention. PLD 103 includes one or more PLD circuit regions
or "islands" 400A-400C. Each PLD circuit region 400A-400C includes
one or more controlled PLD circuits 300, as described above.
[0068] Each of PLD circuit regions 400A-400C may receive one or
more power supply voltages, labeled as V.sub.DD1-V.sub.DDN. As
examples, PLD circuit region 400A receives V.sub.DD1, whereas
circuit region 400B receives V.sub.DD1-V.sub.DD3, and circuit
region 400C receives V.sub.DDN. Each of controlled PLD circuits 300
can adjust the supply voltage provided to its respective PLD
circuit 306 (see, for example, FIG. 4), as described above in
detail.
[0069] By assigning a desired set of power supply voltages to each
of PLD circuit regions 400A-400C, one may adjust the supply voltage
and power consumption of circuitry within the circuit regions.
Furthermore, by including a desired set of controlled PLD circuits
300 within a given circuit region 400A-400C, one may match the type
of supply voltage adjustment in each circuit region 400A-400C with
one or more suitable controlled PLD circuits 300. Thus, the
arrangement in FIG. 8 provides a flexible mechanism for allocating
various PLD resources to implementing an appropriate part of the
user's design or system so as to provide an efficient
implementation with improved performance adjustment capabilities
and better overall performance (e.g., speed-power consumption
tradeoff).
[0070] Note that, in addition to, or rather than, receiving
external power supply voltages (e.g., V.sub.DD1-V.sub.DDN in FIG.
8), PLD 103 may generate power supply voltages internally, as
desired. FIGS. 9A-9C show circuit arrangements for distributing and
generating power supply voltages in PLDs according to exemplary
embodiments of the invention.
[0071] In FIG. 9A, PLD 103 simply uses the external power supply
voltages that it receives, e.g., V.sub.DD1-V.sub.DDN. In this
scenario, PLD 103 may use a power distribution and supply voltage
adjustment scheme, such as the arrangement in FIG. 8.
[0072] In FIG. 9B, PLD 103 receives power supply voltages
V.sub.DD1-V.sub.DDN. PLD 103 may regulate one or more of the power
supply voltages to generate one or more internal power supply
voltages. PLD 103 may then use the external and the internally
generated powers supply voltages in a power distribution and supply
voltage adjustment scheme, e.g., as shown in FIG. 8. In the
particular example shown, PLD 103 uses voltage regulator 450 to
generate internal power supply voltage V.sub.DD2' from external
power supply voltage V.sub.DD2.
[0073] In FIG. 9C, PLD 103 receives power supply voltages
V.sub.DD1-V.sub.DDN. PLD 103 may use one or more charge pumps 453
to generate one or more internal power supply voltages. PLD 103 may
then use the external and the internally generated powers supply
voltages in a power distribution and supply voltage adjustment
scheme, e.g., as shown in FIG. 8. In the particular example shown,
PLD 103 uses charge pump 453 to generate internal power supply
voltage V.sub.DD1' from external power supply voltage V.sub.DD1.
Internal power supply voltage V.sub.DD1' has a higher voltage level
than V.sub.DD1.
[0074] As noted above, the inventive concepts include techniques
for isolating noise-sensitive circuits from noise-generating
circuitry with the PLD. More particularly, in PLDs fabricated using
CMOS technology, various PLD circuits typically reside in a number
of deep n-wells. By strategically placing noise-sensitive circuits
in isolated n-wells, one may shield or isolate the noise-sensitive
circuits from sources of noise. Thus, one may provide islands
within the PLD, each with its own supply voltage, power
consumption, noise generation, and noise isolation characteristics.
The islands provide a mechanism in PLDs according to the invention
for providing a flexible implementation of a user's design or
system.
[0075] FIG. 10 shows an example of using n-wells to isolate
noise-sensitive circuits in a PLD according to an illustrative
embodiment of the invention. The PLD resides in substrate 500.
Substrate 500 includes deep n-wells 503, 506, and 509. Each of deep
n-wells 503, 506, and 509 may include a variety of PLD circuitry,
such as the circuits shown in FIGS. 1-3.
[0076] As noted, one may place the various circuits in deep n-wells
503, 506, and 509 so as to reduce interference and noise. For
example, one may place circuitry with relatively high noise
sensitivity (labeled as 506A) in a PLD that includes circuits that
generate moderate amounts of noise (labeled as 506B) as well as
circuits that produce relatively high levels of noise (labeled as
506C). As the example in FIG. 10 illustrates, one may place
circuits 506A, 506B, and 506C in deep n-wells 503, 506, and 509,
respectively. Noise and interference tends to decrease by the
virtue of placing noise-sensitive circuit 506A farthest from the
relatively high levels of noise that circuit 506C generates, but
nearer to the moderate levels of noise that circuit 506B
produces.
[0077] Note that deep n-wells represent an illustrative construct
in a PLD fabrication technology. Depending on a number of factors,
one may use other constructs and devices in current and future
fabrication technologies, as persons of ordinary skill in the art
who have the benefit of the description of the invention
understand. The factors include the type and characteristics of the
technology and the devices and constructs available, the desired
design and performance specifications, cost, complexity, area
efficiency, and the like.
[0078] As an example, one may use silicon-on-insulator (SOI)
technology to provide noise isolation and control within PLDs. More
specifically, and as persons of ordinary skill in the art who have
the benefit of the description of the invention understand, SOI
circuits tend to provide isolation between transistors because of
the insulator layer (typically silicon dioxide). Thus, SOI circuits
provide a mechanism for isolating noise-sensitive circuits from
noise-generating circuits of the PLD.
[0079] As noted above, the user may adjust the supply voltage and
power consumption and noise exposure or performance of various
portions of PLDs according to the invention. The user may do so by
using the software used to map a design to a PLD. FIG. 11 depicts
various software modules that PLD computer-aided design (CAD)
software according to illustrative embodiments of the invention
uses. The modules include design-entry module 550, synthesis module
553, place-and-route module 556, and verification module 559.
[0080] Design-entry module 550 allows the integration of multiple
design files. The user may generate the design files by using
design-entry module 550 or by using a variety of electronic design
automation (EDA) or CAD tools (such as industry-standard EDA
tools), as desired. The user may enter the design in a graphic
format, a waveform-based format, a schematic format, in a text or
binary format, or as a combination of those formats, as
desired.
[0081] Synthesis module 553 accepts the output of design-entry
module 550. Based on the user-provided design, synthesis module 553
generates appropriate logic circuitry that realizes the
user-provided design. One or more PLDs (not shown explicitly)
implement the synthesized overall design or system.
[0082] Synthesis module 553 may also generate any glue logic that
allows integration and proper operation and interfacing of various
modules in the user's designs. For example, synthesis module 553
provides appropriate hardware so that an output of one block
properly interfaces with an input of another block. Synthesis
module 553 may provide appropriate hardware so as to meet the
specifications of each of the modules in the overall design or
system.
[0083] Furthermore, synthesis module 553 may include algorithms and
routines for optimizing the synthesized design. Through
optimization, synthesis module 553 seeks to more efficiently use
the resources of the one or more PLDs that implement the overall
design or system. In some embodiments, synthesis module 553 may
identify critical paths within the synthesized design or system.
Synthesis module 553 provides its output to place-and-route module
556.
[0084] Place-and-route module 556 uses the designer's timing
specifications to perform optimal logic mapping and placement. The
logic mapping and placement determine the use of routing resources
within the PLD(s). In other words, by use of particular
programmable interconnects with the PLD(s) for certain parts of the
design, place-and-route module 556 helps optimize the performance
of the overall design or system.
[0085] By proper use of PLD routing resources, place-and-route
module 556 helps to meet the critical timing paths of the overall
design or system. Place-and-route module 556 optimizes the critical
timing paths to help provides timing closure faster in a manner
known to persons of ordinary skill in the art with the benefit of
the description of the invention. As a result, the overall design
or system can achieve faster performance (i.e., operate at a higher
clock rate or have higher throughput).
[0086] Furthermore, place-and-route module 556 adjusts the supply
voltage and power consumption and the noise performance or exposure
of a portion of or all of the PLD(s) that implement the design or
system. Place-and-route module 556 may do so automatically,
according to user-specified criteria, or a combination of the two.
Place-and-route module 556 may use the user-specified criteria (for
example, performance specifications, such as power dissipation,
noise exposure or performance, speed, and/or current-drive
capability). In addition, or instead, place-and-route module 556
may use the information about critical paths within the design or
system to adjust the supply voltage(s), physical placement so as to
reduce noise generation and exposure, and power consumption of
parts or all of the design or system, as desired.
[0087] For example, place-and-route module 556 may adjust the
supply voltage and power consumption of the critical parts of the
design or system so as to achieve higher performance.
Place-and-route module 556 may take into account power dissipation
criteria (e.g., maximum power density) so as to trade off power and
performance, as desired. Place-and-route module 556 provides the
optimized design to verification module 559.
[0088] Verification module 559 performs simulation and verification
of the design. The simulation and verification seek in part to
verify that the design complies with the user's prescribed
specifications. The simulation and verification also aim at
detecting and correcting any design problems before prototyping the
design. Thus, verification module 559 helps the user to reduce the
overall cost and time-to-market of the overall design or
system.
[0089] Verification module 559 may support and perform a variety of
verification and simulation options, as desired. The options may
include design-rule checking, functional verification, test-bench
generation, static timing analysis, timing simulation,
hardware/software simulation, in-system verification, board-level
timing analysis, signal integrity analysis and electromagnetic
compatibility (EMC), formal netlist verification, noise generation
and exposure, and power-consumption estimation, as desired. Note
that one may perform other or additional verification techniques as
desired and as persons of ordinary skill in the art who have the
benefit of the description of the invention understand.
[0090] FIG. 12 illustrates a flow diagram for a PLD CAD software
according to an exemplary embodiment of the invention. The PLD CAD
shown in FIG. 12 incorporates the choice of supply voltage and
power consumption for each region of the PLD into a timing-driven
place-and-route CAD system. Note that, as desired, one may include
criteria for noise generation, noise exposure, and/or noise
isolation into the PLD CAD in FIG. 12 by making modifications that
fall within the knowledge of persons of ordinary skill in the art
who have the benefit of the description of the invention.
[0091] Starting the process, at 603 the PLD CAD sets initial supply
voltage levels (corresponding to estimated power consumption
levels). At 606 the software generates an initial placement. Then,
at 609 it analyzes the timing of the circuitry using delay
estimates that reflect the various settings, such as supply voltage
settings. At 612 the software determines whether it has met the
user's various criteria, such as timing and power goals. If so, at
615 it records the placement and supply voltage selections. If not,
the software checks at 618 to determine whether it has reached the
iteration limit. If so, it proceeds to 615 to record the current
placement and supply voltage selections.
[0092] If the software has not reached the iteration limit, it
increments the iteration count (not shown explicitly), and at 621
changes the settings of at least some regions, circuits, blocks, or
parts of the PLD. At 624 it analyzes the timing of the circuitry
using delay estimates that reflect the changed settings. At 356 it
improves the placement of the circuit, and jumps to 612 to
determine whether it has met the user's timing and power goals.
Once the PLD CAD has implemented a design (i.e., synthesized,
placed and routed the design), the CAD software should
automatically provide data for programming the PLD that set the
supply voltages of various parts of the PLD.
[0093] FIG. 13 shows a block diagram of circuitry within a PLD
according to exemplary embodiments of the invention to adjust,
program, or set the supply voltage levels of desired parts of the
PLD. The circuitry includes bias circuit 703, a plurality of
configuration memory (configuration random-access memory, or CRAM,
or other implementations of the memory) cells 709, and controlled
PLD circuits 300.
[0094] Bias circuit 703 generates one or more signals 706 and
provides those signal(s) to controlled PLD circuits 300 (more
particularly, to control circuit 303, as shown, for example, in
FIG. 4). In other word, bias circuit 703 provides one or more
global bias signals to controlled PLD circuits 300. Furthermore,
each of CRAM cells 709 provides to a respective one of controlled
PLD circuits 300 (more particularly, to control circuit 303). The
signals from CRAM cells 709 represent configuration data for the
various circuits within the PLD, as provided by the PLD CAD program
described above. In response to configuration data from CRAM cells
709, the control circuit (not shown explicitly) in each of
controlled PLD circuits 300 generates one or more signals to
control the impedance of the variable impedance device (not shown
explicitly) as a function of signal(s) 706.
[0095] In other variations, each of CRAM cells 709 may provide
configuration data to more than one controlled PLD circuit, as
desired. Conversely, one may modify the control circuit within
controlled PLD circuits 300 so as to make it responsive to
configuration data from more than one CRAM cell 709, as
desired.
[0096] Note that one may adjust, program, or set supply voltage
levels in response to sources external to the PLD. For example, one
may communicate supply voltage levels to a PLD to adjust or modify
its performance. FIG. 14 shows a circuit arrangement according to
exemplary embodiments of the invention for adjusting supply voltage
levels within PLD 103 in response to an external source 753. The
circuit arrangement includes external source 753,
communication/interface circuit 762, and bias circuit 703 (see FIG.
13).
[0097] Communication/interface circuit 762 provides a mechanism for
external source 753 and bias circuit 703 to communicate and
exchange information. External source 753 may provide one or more
control signal(s) 756 to communication/interface circuit 762 within
PLD 103. Communication/interface circuit 762 provides the
information received from external source 753 to bias circuit 703.
In response, bias circuit 703 generates one or more signals 706,
with levels corresponding to control signal(s) 756.
Communication/interface circuit 762 may provide information, such
as status signals, from bias circuit 703 (or PLD 103 generally) to
external source 753.
[0098] External source 753 may constitute a variety of devices,
structures, or arrangements, as persons of ordinary skill in the
art with the benefit of the description of the invention
understand. For example, external source 753 may constitute a
computer network (e.g., the Internet), a telephone-line
communication link, a wireless communication link, a bus, etc., as
desired.
[0099] Note that one may adjust, program, or set the supply voltage
levels in PLDs on a dynamic or time-varying basis, as desired, to
take into account or respond to changing conditions (for example,
changes in performance specifications). As one example, referring
to FIG. 14, external source 753 may update or modify control
signal(s) 756 that it provides to PLD 103. Bias circuit 703
responds accordingly to the updated or modified signal(s) 756.
[0100] As another example, one may change or adjust supply levels
in response to changes within PLD 103 itself, for instance, a
change in temperature, noise, power consumption, and the like, in
one or more circuits or areas of PLD 103. FIG. 15 shows a circuit
arrangement for modifying supply voltage level(s) within a PLD
according to exemplary embodiments of the invention.
[0101] The circuit arrangement includes one or more sensor(s) 803,
one or more reference source(s) 806, subtracter 818, and bias
circuit 703. Sensor(s) 803 sense a desired parameter (e.g.,
temperature, noise, etc.) in one or more areas, circuits, or blocks
within PLD 103 and provide signal(s) 809 to subtracter 818.
Reference source(s) 806 provide reference signal(s) 812 to
subtracter 818. Reference signal(s) 812 may have values that
correspond to various levels of the sensed parameter.
[0102] Subtracter 818 subtracts reference signal(s) 812 from
signal(s) 809 and provides difference signal(s) 815 to bias circuit
703. Difference signal(s) 815 may constitute the difference between
actual sensed value(s) and the desired value(s) in one or more
parts of PLD 103. In response to difference signal(s) 815, bias
circuit 703 generates signal(s) 706 (see also FIG. 13).
[0103] Bias circuit 703 may use difference signal(s) 815 to
generate signal(s) 706 that ultimately affect various aspects of
the performance of PLD 103. For example, if difference signal(s)
815 indicate a lower sensed value (say, speed) than a threshold or
maximum value, bias circuit 703 may generate signal(s) that
increase supply voltage level(s) to increase operating speed of the
desired parts of PLD 103. In contrast, if difference signal(s) 815
indicate a sensed level higher than a safe or maximum level, bias
circuit 703 may generate signal(s) that decrease supply voltage
level(s) to safe or desired levels (albeit with a decreased
resulting speed).
[0104] More generally, one may implement a feedback loop that
generates supply voltage level(s) so as to target specific
performance criteria. Put another way, one may compare actual
performance measures of a PLD to desired or specified measures or
criteria and adjust, program, or set supply voltage levels
accordingly.
[0105] As noted above, one aspect of the inventive concepts relates
to the performance and power consumption, and their adjustment or
configuration, of IP blocks within PLD 103. Broadly speaking, as
noted above, PLDs according to the invention include not only
digital circuitry, but also mixed-mode or mixed-signal circuitry or
circuitry that is analog in nature.
[0106] Typically, the analog and/or mixed-mode or mixed-signal
circuitry resides in IP block(s) within the PLD. IP blocks, as
persons of ordinary skill in the art who have the benefit of the
description of the invention understand, generally denote a
pre-designed circuit or block. For example, an IP block might
constitute a core or block of circuitry designed by another
designer, group of designers, or even another organization. PLD 103
might include one or more IP block(s), as desired.
[0107] As persons of ordinary skill in the art who have the benefit
of the description of the invention understand, IP blocks might
include a wide variety of circuits. Examples include
analog-to-digital converters (ADCs), digital-to-analog converters
(DACs), data converters, various types of amplifiers, gain blocks,
mixers or multipliers, phase-locked loops (PLLs), oscillators,
voltage-controlled oscillators (VCOs), filters, clock sources,
clock multipliers, clock recovery circuits, receivers,
transmitters, transceivers, and various types of interfaces, such
as high-speed serial interfaces (HSSI). Note that, generally, IP
blocks might include digital circuitry and/or analog circuitry, as
desired (i.e., all digital, all analog, digital and analog,
mixed-mode, mixed-signal etc.).
[0108] Not only the particular type of circuitry in IP block, but
also the amount or number of IP blocks, makes them relatively
important from performance, noise, and power consumption
perspectives. In present-day PLDs, designers or users might
replicate an IP block up to 20 times across the PLD. Because of
that repetition, any gains in the performance and power consumption
of the IP block(s) would make a relatively large impact on the
overall performance of the PLD and, hence, the circuit or system in
which they reside.
[0109] Furthermore, as noted above, some of the circuitry in PLDs
according to the inventive concepts uses a dedicated (or shared
with similar circuits) power supply. Separate power supplies supply
power to the traditional PLD fabric, e.g., programmable logic 106
and programmable interconnect 109 (see FIG. 1). The separation of
the power supplies helps overcome noise and power consumption
problems, as persons of ordinary skill in the art who have the
benefit of the description of the invention understand.
[0110] Although one may use separate external power supplies (e.g.,
regulators outside the PLD's package), doing so has certain
disadvantages. First, external regulators tend to increase the
overall cost of the solution or system. Second, external regulators
tend to increase the complexity of the design from a user's
perspective because of the increased complexity of the printed
circuit board and additional components.
[0111] In contrast, PLDs according to the inventive concepts
contemplate integrating regulators or power supplies for IP blocks,
or at least noise-sensitive portions, circuits, or parts in IP
blocks, within the PLD. Integrated regulators overcome the
disadvantages of external regulators.
[0112] More specifically, integrated regulators reside within the
same package as the PLD's die, thus resulting in lower overall
cost. Moreover, integrated regulators reduce the number of
components in the bill of materials. Integrated regulators also
tend to reduce coupling to nearby or other circuitry on the printed
circuit board and, hence, reduce noise, coupling, or interference
problems. In addition, integrated regulators tend to increase
system robustness and overall reliability.
[0113] The circuitry within typical IP blocks can itself lead to
special consideration in circuit and system design and, hence,
affect performance and power consumption. Because of their
relatively high performance specifications and goals, IP blocks
tend to exhibit increased sensitivity to process, voltage-level,
and power quality variations.
[0114] For example, leakage can prove detrimental to the
performance of high-speed dynamic logic. Dynamic logic relies on
storage of relatively small amounts of charge on a capacitor.
Leakage in the circuit can cause the charge on the capacitor to
reduce, and might lead to the logic circuit losing its state or
having an incorrect state. The incorrect state can propagate to
other circuitry and cause errors or malfunctions in the circuit or
system.
[0115] Natural device-to-device variations within a given
semiconductor fabrication process can lead to variations in device
leakage levels. The variations might lead to reduced performance or
failure of dynamic logic circuits, as described above. If the
devices in question happen to reside in sensitive IP blocks or
mixed-mode circuits, the PLD itself might experience problems or
fail. This phenomenon would result in reduced manufacturing yield
and increased costs.
[0116] As another example, device-to-device variations might lead
to variations in the edge rates in driver circuits. This phenomenon
adversely impacts the PLD's performance. Slow edges, for example,
are more prone to jitter, while faster edges tend to result in
increased power consumption and generate additional noise in the
power supply for the circuit (i.e., in the power supply for the IP
block or the particular part of the IP block).
[0117] In such situations, one might trade off performance and
yield. In other words, by reducing performance goals, one might
avoid leakage and edge rate problems and the resulting device
failure and, consequently, avoid reduced yields. Conventional
approaches to these problem focus on power management of particular
parts of the circuitry or system. The inventive concepts provide a
more general or system-level approach that includes power
management considerations for the IP blocks and PLD circuitry into
a higher end system for PLDs.
[0118] FIG. 16 shows a simplified block diagram of an exemplary
embodiment of the invention for adjusting the performance of
circuitry within the PLD, including IP block(s). The particular
embodiment includes power management circuitry 1003, PLD circuitry
306, and one or more IP blocks 1000.
[0119] Power management circuitry 1003 communicates with PLD
circuitry 306 via signal link 1006. Signal link 1006 might provide
signal flow in one or both directions between power management
circuitry 1003 and PLD circuitry 306. Generally speaking, signal
link 1006 might include one of more status signals and one or more
control signals, as desired. The particular implementation of
signal link 1006 depends on the details of the desired performance
and circuit specifications, as persons of ordinary skill in the art
who have the benefit of the description of the invention
understand.
[0120] Similarly, power management circuitry 1003 communicates with
IP block(s) 1000 via signal link 1009. Signal link 1009 might
provide signal flow in one or both directions between power
management circuitry 1003 and IP block(s) 1000. Generally speaking,
signal link 1009 might include one of more status signals and one
or more control signals, as desired. The particular implementation
of signal link 1009 depends on the details of the desired
performance and circuit specifications, as persons of ordinary
skill in the art who have the benefit of the description of the
invention understand.
[0121] One may implement signal link 1006 and signal link 1009 in a
wide variety of ways. For example, one may use individual
conductors or coupling mechanisms, a bus, or the like, as desired.
Again, the details of the implementation depend on the particular
situation, as persons of ordinary skill in the art who have the
benefit of the description of the invention understand.
[0122] Power management circuitry 1003 controls or manages the
provision of power to PLD circuitry 306. Power management circuitry
1003 may set, vary, or control the voltage levels to one or more
parts of PLD circuitry 306, as desired, and as described above.
Power management circuitry 1003 might also cause one or more parts
of PLD circuitry 306 to become disabled or hibernate, as desired,
and as described above.
[0123] In addition, power management circuitry 1003 may set, vary,
or control body bias levels for one or more parts of PLD circuitry
306, as desired, and as described above. As noted, body bias levels
impact the performance of the affected transistors and, hence, of
the overall circuit. Put simply, one may trade off speed and power
consumption of the transistors and the overall circuit. More
details of body bias and leakage control appear in U.S. patent
application Ser. No. 10/865,402, titled "Apparatus and Methods for
Adjusting Performance of Integrated Circuits," filed on Jun. 10,
2004, Attorney Docket No. ALTR:026CIP, assigned to Altera
Corporation, and incorporated here by reference in its
entirety.
[0124] In a similar manner, power management circuitry 1003
controls or manages the provision of power to IP block(s) 1000. The
affected parts of IP block(s) 1000 may include analog circuitry,
digital circuitry, mixed-mode or mixed-signal circuitry, or
combinations of them, as desired, and as persons of ordinary skill
in the art who have the benefit of the description of the invention
understand.
[0125] Power management circuitry 1003 may set, vary, or control
the voltage levels to one or more parts of IP block(s) 1000, as
desired, and as described above. Power management circuitry 1003
might also cause one or more parts of IP block(s) to become
disabled or hibernate, as desired, and as described above.
[0126] Furthermore, power management circuitry 1003 may set, vary,
or control body bias levels for one or more parts of IP block(s)
1000, as desired, and as described above. Body bias levels have the
effect on performance of the affected transistors and the overall
circuit, described above and, in more detail, in U.S. patent
application Ser. No. 10/865,402, incorporated here by
reference.
[0127] Note that power management circuitry 1003 may control the
provision of power, voltage level(s), and body bias level(s) to PLD
circuitry 306 and IP block(s) 1000 with any desired level of
granularity. Thus, the level of granularity may affect individual
transistors, to groups or blocks of transistors or circuits, to
entire blocks, all of PLD circuitry 306, all of IP block(s) 1000,
etc., as desired. The choice of the level of granularity depends on
a number of factors, such as the desired performance and design
specifications in a given situation, as persons of ordinary skill
in the art who have the benefit of the description of the invention
understand.
[0128] Note that FIG. 16 provides merely one exemplary embodiment,
and that many alternative embodiments according to the inventive
concepts are possible, as persons of ordinary skill in the art who
have the benefit of the description of the invention understand.
For example, FIG. 17 illustrates a simplified block diagram of
another exemplary embodiment of the invention. This embodiment
includes PLD circuitry 306, IP block(s) 1000, PLD power management
circuitry 1003A, and IP power management circuitry 1003B.
[0129] PLD power management circuitry 1003A communicates with PLD
circuitry 306 via signal link 1006A and signal link 1006B. Signal
link 1006A and signal link 1006B may be similar to the
corresponding parts of signal link 1006 in FIG. 16, as desired, and
as persons of ordinary skill in the art who have the benefit of the
description of the invention understand. Signal link 1006A,
however, provides a mechanism for communication from PLD power
management circuitry 1003A to PLD circuitry 306, whereas signal
link 1006B provides a way for PLD circuitry 306 to communicate with
PLD power management circuitry 1003A.
[0130] Likewise, IP power management circuitry 1003B communicates
with IP block(s) 1000 via signal link 1009A and signal link 1009B.
Signal link 1009A and signal link 1009B may be similar to
corresponding parts of signal link 1006 in FIG. 16, as desired, and
as persons of ordinary skill in the art who have the benefit of the
description of the invention understand. Note, however, that signal
link 1009A provides a mechanism for communication from IP power
management circuitry 1003B to IP block(s) 1000. Signal link 1009B,
on the other hand, provides a way for IP block(s) 1000 to
communicate with IP power management circuitry 1003B.
[0131] Generally speaking, the embodiment in FIG. 17 operates in a
like manner and achieves similar goals as does the embodiment in
FIG. 16. By providing individualized control of power management
functions for PLD circuitry 306 and IP block(s) 1000, however, the
embodiment in FIG. 17 allows for finer control over the power
control and performance of PLD circuitry 306 and IP block(s) 1000
and, hence, of PLD 103 overall.
[0132] As an example, the embodiment in FIG. 17 provides the
capability for either the PLD CAD software (see FIG. 11) and/or the
user to have finer control over the power consumption, power
supply, and performance of one or more PLD circuits 306 and/or one
of more IP block(s) 1000. As another example, one may provide power
management capability to the PLD CAD software but to the user, or
vice-versa, for PLD circuitry 306 and/or IP block(s) 1000.
[0133] IP power management circuitry 1003B (or PLD power management
circuitry 1003) may control and manage the power consumption and
performance of IP blocks 1000 with a desired level of granularity.
FIG. 18 depicts a simplified block diagram of an illustrative
embodiment according to the invention for adjusting the performance
of various IP block(s) in PLDs.
[0134] The embodiment in FIG. 18 includes a particular kind of IP
block, i.e., a high-speed serial interface (HSSI) circuit 1000A.
The embodiment may include other types of IP block(s), or even
multiple HSSI circuits, as desired. Generally, the circuit
arrangement may include a set of N IP blocks, where N is a desired
positive integer.
[0135] The circuit arrangement in FIG. 18 also includes an IP power
management circuitry 1003. IP power management circuitry 1003B may
have similar characteristics and perform similar functions as
described above. In the circuit arrangement shown, IP power
management circuitry 1003B communicates with HSSI circuit 1000A via
signal links 1009A-1009B.
[0136] Note that, in addition to, or instead of communicating with
HSSI circuit 1000A, IP power management circuitry 1003B may
communicate with other IP blocks(s) (e.g., IP block 1000N), using
the same or different signal links, as desired, and as persons of
ordinary skill in the art who have the benefit of the description
of the invention understand. In either case, IP power management
circuitry 1003B controls the power consumption, provision of power,
and performance of one or more of IP blocks 1000A-1000N, as
desired, and as described above.
[0137] FIG. 19 shows a simplified block diagram of another
illustrative embodiment according to the invention. The figure
shows an exemplary circuit arrangement in HSSI circuit 1000A. In
the example shown, HSSI circuit 1000A include physical coding
sub-layer (PCS) 1026, physical medium attachment (PMA) 1029 and,
optionally, medium access control (MAC) layer 1023. PCS circuit
1026, PMA circuit 1029, and MAC circuit 1023 fall within the
knowledge of persons of ordinary skill in the art who have the
benefit of the description of the invention.
[0138] Generally speaking, PCS circuit 1026 includes circuitry of a
primarily digital nature. PMA circuit 1029, on the other hand,
includes primarily analog circuitry. As noted above, each of the
types of circuitry entail different power provision, power control,
and performance adjustment considerations.
[0139] The circuit arrangement may optionally include power
controller circuit 1020. Power controller circuit 1020 communicates
with other circuitry in the PLD (e.g., IP power management
circuitry 1003B) via signal links 1009A-1009B. Furthermore, power
controller circuit 1020 may communicate with one or more of MAC
circuit 1023, PCS circuit 1026, and PMA circuit 1029 via,
respectively, signal link 1032, signal link 1035, and/or signal
link 1038. Through those signal links, power controller circuit
1020 can control the provision of power and adjustment of
performance of the corresponding circuit or block.
[0140] The circuit arrangement in FIG. 19 provides a hierarchical
or modular approach to power and performance adjustment control.
Note, however, that one may omit power controller 1020, as desired.
For example, as an alternative, one may communicate power control
and performance adjustment signals from another circuit, such as IP
power management circuitry 1003B (see FIG. 18), as desired. In this
situation, IP power management circuitry 1003 may subsume the
circuitry and/or functionality of power controller circuit 1020, as
desired.
[0141] In either situation, the inventive concepts contemplate
providing separate mechanisms for adjusting the supply of power to
MAC circuit 1023, PCS circuit 1026, and PMA circuit 1029. More
specifically, one may control not only whether each of those
circuits receives power, but also the corresponding levels or
magnitudes (and also body bias levels, as desired), if it does.
This concept takes advantage of the fact that, often, the various
parts or blocks of IP block(s) do not operate at their maximum
specified or potential data rates. The reason may lie in the user's
particular circuit demands, the specifications for a particular
end-use, etc.
[0142] By making individualized adjustments, one may fine-tune the
performance of each block and, hence, the overall IP block. For
example, in order to meet standard performance specifications, one
may control the provision of power, various power/voltage levels,
and/or body bias levels, for each block. In case of standard
specifications, one may determine the desired or appropriate
parameters a priori (e.g., through testing and characterization),
and use those parameters if the user's application calls for
meeting the standard specifications.
[0143] As one particular example, consider that the 6G HSSI
standard covers not only CEI (6G specifications), but also XAUI (3G
specifications), PCI-E (2.5G specifications), and others. In this
case, analog and digital parts or blocks of HSSI circuit 1000A may
be set or tuned to either highest power level for 6G operation, or
proportionally lower levels, as pre-determined for 3G, 2.5G, 1G,
operation, etc., as desired.
[0144] One may do so either by using the techniques (e.g., feedback
loops) described in U.S. application Ser. No. 11/204,570, titled
"Apparatus and Methods for Optimizing the Performance of
Programmable Logic Devices," Attorney Docket No. ALTR:044, filed on
Aug. 16, 2005, or without it, as desired. Given that one knows
(through testing, characterization, etc.) the requisite
configuration for each IP block (or part(s) of IP block(s))
together with the requisite data rate, one may derive the
appropriate power level(s) via simulations and confirmation through
characterization. Note that this approach differs from the
techniques described in application Ser. No. 11/204,570 because
those techniques do not assume a priori knowledge of the critical
paths in the user's design.
[0145] The inventive concepts contemplate additional techniques for
adjusting the power consumption and performance of PLDs. FIGS.
20-23 illustrate simplified flow diagrams corresponding to those
techniques.
[0146] FIG. 20 shows a simplified flow diagram for a technique
according to the invention for improving yield and performance. The
technique assumes that PLDs manufactured according to the invention
include fuses or other similar mechanisms that allow one to set
body bias values, supply voltages, and whether one or more parts of
the PLD receive power.
[0147] The method starts at 1050, where one performs a test to
determine the low data rate performance of the relevant IP block(s)
(or other blocks) whose performance one wishes to adjust or set. In
other words, one obtains performance characteristics at a lower
boundary of the specified or desired performance. One adjusts the
body bias levels (and/or supply levels) of those blocks or parts of
those blocks if the specified performance is not met so as to
attempt and obtain the desired performance.
[0148] Subsequently, at 1053, one tests the high data rate
performance of the set of IP block(s) or, put another way, at a
higher boundary of the specified or desired performance. At 1056,
one tests to determine whether the specifications for the high data
rate performance are met.
[0149] If not, at 1059 one characterizes the device, and burns
fuses according to the selected body bias level (and optionally the
supply voltages and whether a specified block or set of blocks
should receive power). In other words, at this point, the device
would be characterized as a relatively slow performance device and
put in a corresponding "bin."
[0150] Otherwise, at 1062, one adjusts the body bias level, while
monitoring leakage in one or more devices, until the desired
performance specifications are met. Subsequently, at 1065, one
characterizes the PLD, and burns fuses according to the selected
body bias level (and optionally the supply voltages and whether a
specified block or set of blocks should receive power).
[0151] Note that one may use the above technique can not only
adjust the body bias during wafer sort, but also dynamically during
device initialization (after power-up, but before control is
released to the user, i.e., the user mode). In such a case, the
body bias level(s) and/or power level(s) can be adjusted. (Note
that the technique assumes that during wafer sort a determination
was made that the PLD could be functional with respect to the
desired performance characteristics with final tuning to be
performed during programming, but before entering the user mode of
operation.)
[0152] In the situation where the user's desired specific data
rates or performance characteristics do not correspond to a
particular standard, but may rather fall between the performance
specified by two different standards (e.g., between 1G and 2G).
FIG. 21 shows a simplified flow diagram of a technique according to
an exemplary embodiment of the invention that one may use in this
situation.
[0153] More specifically, one may adjust the parameters for various
parts or blocks of the PLD in order to meet the desired
performance. One may do so via programmable vendor software during
device configuration, as desired (and without using a feedback
loop).
[0154] Referring to FIG. 21, at 1070, one determines whether all IP
blocks are used in the user's design. If so, at 1079 one provides
power to all IP blocks. If not, at 1073 one disables provision of
power to the unused IP block(s). At 1076, one determines whether
the user desired performance specified by a particular standard. If
so, at 1082 one provides power to pre-determined or predefined IP
block(s) of the PLD, and disables power to any unused IP block(s)
or sub-block(s).
[0155] If not, at 1085 one determines the appropriate power
level(s) for the affected IP block(s) according to the desired
performance characteristics. Furthermore, one provides the
appropriate power level(s) to those block(s), and disables any
unused IP block(s) or sub-block(s).
[0156] One may use additional techniques according to the inventive
concepts in order to change driver edge rates until a desired
performance level is met. Doing so will tune the drivers that
otherwise operate too fast or too slowly because of shifts in
semiconductor manufacturing process. To speed up a device that is
otherwise too slow, the technique uses leakage monitoring, as
described above.
[0157] The sorting and repair (or tuning of performance) improves
yield for IP block(s) that include analog circuitry and, hence, for
the PLD itself. Once one has determined the non-performing part(s),
circuit(s), or block(s), one may use fuses in order to apply
appropriate body bias level(s) to as to affect the performance of
various parts or blocks of the PLD. Doing so helps obtain a device
that meets the desired performance characteristics. If one cannot
obtain a device that meets the desired performance specifications,
one may burn the fuses so as to yield a lower-speed grade, but
functional, PLD, thus improving overall yield.
[0158] FIG. 22 illustrates a simplified flow diagram of a technique
according to an exemplary embodiment of the invention in order to
adjust performance and power consumption of a PLD. At 1090, one
sorts the device in order to determine its performance capability.
At 1093, one determines whether any IP block(s) inhibit the desired
performance. If not, one sets the device grade accordingly (e.g., a
higher-speed grade device).
[0159] If so, at 1096 one adjusts the body bias and/or supply
voltage(s) of the pertinent block(s) or sub-blocks. Thereafter, at
1099, one may optionally repeat the sorting and adjusting steps for
a desired number of times. Then, at 1103 one determines whether the
devices meets the desired performance characteristics. One then
sets the device grade accordingly (e.g., a lower-speed grade
device, or a higher-speed grade device, depending on the results of
the test at 1103).
[0160] Furthermore, one may use a higher-level algorithm or
technique to allow the user to control the performance of the IP
block(s) and of the overall PLD. The technique takes into account
various operational condition (e.g., level of activity at certain
nodes or within certain circuits, blocks, etc.), which are known to
the user, but not to the PLD's vendor, as they depend on the user's
application and particular circuit or system. Depending on the
operational parameters, one may vary the provision of power to
certain parts or blocks of the PLD.
[0161] FIG. 23 depicts a simplified flow diagram to illustrate the
technique. At 1120, one monitors at least one device performance
characteristic or criterion, such as throughput or activity. At
1123, one determines whether the actual performance exceeds the
desired performance (or put another way, how the actual performance
compares to the desired performance). If so, one may disable power
to selected IP block(s) or sub-block(s) and/or adjust the supply
level(s) for the block(s) or sub-block(s). If not, however, one may
optionally return to 1120 one or more times, generally any desired
number of times (in other words, one may continue the performance
monitoring).
[0162] Note that one may apply the inventive concepts effectively
to various programmable logic circuitry or ICs known by other names
in the art, as desired, and as persons skilled in the art with the
benefit of the description of the invention understand. Such
circuitry include devices known as complex programmable logic
device (CPLD), programmable gate array (PGA), and field
programmable gate array (FPGA).
[0163] Referring to the figures, persons of ordinary skill in the
art will note that the various blocks shown may depict mainly the
conceptual functions and signal flow. The actual circuit
implementation may or may not contain separately identifiable
hardware for the various functional blocks and may or may not use
the particular circuitry shown. For example, one may combine the
functionality of various blocks into one circuit block, as desired.
Furthermore, one may realize the functionality of a single block in
several circuit blocks, as desired. The choice of circuit
implementation depends on various factors, such as particular
design and performance specifications for a given implementation,
as persons of ordinary skill in the art who have the benefit of the
description of the invention understand. Other modifications and
alternative embodiments of the invention in addition to those
described here will be apparent to persons of ordinary skill in the
art who have the benefit of the description of the invention.
Accordingly, this description teaches those skilled in the art the
manner of carrying out the invention and are to be construed as
illustrative only.
[0164] The forms of the invention shown and described should be
taken as the presently preferred or illustrative embodiments.
Persons skilled in the art may make various changes in the shape,
size and arrangement of parts without departing from the scope of
the invention described in this document. For example, persons
skilled in the art may substitute equivalent elements for the
elements illustrated and described here. Moreover, persons skilled
in the art who have the benefit of this description of the
invention may use certain features of the invention independently
of the use of other features, without departing from the scope of
the invention.
* * * * *