U.S. patent application number 11/418709 was filed with the patent office on 2006-09-07 for semiconductor switches and switching circuits for microwave.
Invention is credited to Hiroshi Mizutani.
Application Number | 20060197106 11/418709 |
Document ID | / |
Family ID | 16874461 |
Filed Date | 2006-09-07 |
United States Patent
Application |
20060197106 |
Kind Code |
A1 |
Mizutani; Hiroshi |
September 7, 2006 |
Semiconductor switches and switching circuits for microwave
Abstract
The purpose of the present invention is to provide a small-sized
switch attaining high isolation of not less than 80 dB, maintaining
low insertion loss also in high frequencies not less than 60 GHz. A
semiconductor switch according to the present invention utilizes
FETs a gate electrode, a source electrode, and a drain electrode of
each of which are formed on a semiconductor. The source electrode
and the drain electrode are connected with the earth as well as are
disposed in parallel to each other, and the gate electrode is
formed between the source electrode and the drain electrode, and
both the ends of the gate electrode are connected to the first
input-output terminal 1 and the second input-output terminal.
Inventors: |
Mizutani; Hiroshi; (Tokyo,
JP) |
Correspondence
Address: |
Muirhead and Saturnelli, LLC
Suite 1001
200 Friberg Parkway
Westborough
MA
01581
US
|
Family ID: |
16874461 |
Appl. No.: |
11/418709 |
Filed: |
May 5, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10737261 |
Dec 15, 2003 |
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11418709 |
May 5, 2006 |
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09372322 |
Aug 11, 1999 |
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10737261 |
Dec 15, 2003 |
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Current U.S.
Class: |
257/192 ;
257/E29.249 |
Current CPC
Class: |
H01L 29/7783 20130101;
H01P 1/15 20130101 |
Class at
Publication: |
257/192 |
International
Class: |
H01L 31/0328 20060101
H01L031/0328 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 12, 1998 |
JP |
228311/1998 |
Claims
1. A semiconductor switch, comprising: a first electrode, a second
electrode, and a third electrode formed on a semiconductor
substrate; said first electrode and said second electrode connected
with the earth and are disposed in parallel to each other, said
third electrode formed between said first and said second
electrode; a first terminal coupled to one end of said third
electrode; and a second terminal coupled to the other end of said
third electrode.
2. The switch is as claimed in claim 1, wherein said first
electrode is a drain electrode of a transistor, said second
electrode is a source electrode of said transistor, said third
electrode is a gate electrode of said transistor.
3. The switch is claimed in claim 1, wherein said first electrode
is a first cathode electrode of a diode, said second electrode is a
second cathode electrode of said diode, said third electrode is an
anode electrode of said diode.
4. (canceled)
5. A switching circuit, comprising: a coplanar transmission line
having a signal line, conductors arranged such that said signal
line is sandwiched between the conductors, said conductors applied
to ground potential; an element having a first electrode coupled to
said coplanar transmission line, a second electrode, a third
electrode, said second and third electrodes applied to ground
potential; and a signal terminal coupled to said coplanar
transmission line.
6. The switching circuit is as claimed in claim 5, wherein said
first electrode is a drain electrode of a diode, said second
electrode is a source electrode of said diode, said third electrode
is a gate electrode of said diode.
7. The switching circuit is claimed in claim 5, wherein said first
electrode is a first cathode electrode of a diode, said second
electrode is a second cathode electrode of said diode, said third
electrode is an anode electrode of said diode.
8. (canceled)
9. The switching circuit as claimed in claim 5, wherein said first,
second, and third electrode are formed on a substrate including an
AlGaAs layer and an InGaAs layer.
10. A semiconductor switch, comprising: an i-GaAs layer; a first
i-AlGaAs layer formed on said first i-GaAs layer; an i-InGaAs layer
formed on said i-AlGaAs layer; a n-AlGaAs layer formed on said
i-InGaAs layer; a first cathode electrode of a diode formed on said
n-AlGaAs layer and supplied with a ground potential; a second
cathode electrode of a diode formed on said n-AlGaAs layer and
supplied with said ground potential; an n.sup.+ GaAs layer formed
between said first and second anodes on said n-AlGaAs layer; and an
anode electrode of a diode formed on said n.sup.+ GaAs layer and
having a first end coupled to a first terminal and a second end
coupled to a second terminal.
11. The switch as claimed in claim 10, wherein said diode acts as
capacitance when said ground potential is applied to said anode
electrode thereby said switch being rendered in ON state.
12. The switch as claimed in claim 10, further comprising: a
resistor having a first end connected to said anode electrode and a
second end supplied with said ground potential.
13. The switch as claimed in claim 10, wherein each of said anode
electrode and first and second cathode electrodes are a metal
layer.
14. The switch as claimed in claim 10, wherein said anode electrode
is provided to have a Schottky junction with said active
region.
15. The switch as claimed in claim 10, wherein said cathode
electrodes are provided to have an ohmic junction with said active
region.
16. The switch as claimed in claim 10, wherein said switch is
arranged to use for microwave or millimeter wave.
17. A switching circuit, comprising: a first coplanar transmission
line having a first signal line and a first pair of conductors
arranged so that said first signal line is sandwiched between said
first pair of conductors, said first pair of conductors being
applied to a ground potential; a second coplanar transmission line
having a second signal line and a second pair of conductors
arranged so that said signal line is sandwiched between said second
pair of conductors, said second pair of conductors being applied to
the ground potential; and a diode coupled to a signal line coupling
said first signal line of said first coplanar transmission line and
said second signal line of said second coplanar transmission line,
an anode of the diode being coupled to said signal line and a
cathode of the diode being coupled to the ground potential.
18. The switch circuit as claimed in claim 17, wherein said anode
is supplied with a positive voltage so that the switching circuit
is to be in an off state and is supplied with a zero bias so that
the switching circuit is to be in an on state.
19. The switch circuit as claimed in claim 17, wherein said switch
circuit is arranged to use for microwave or millimeter wave.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to semiconductor switches, and in
particular to semiconductor switches for microwave as well as
millimeter wave bands using a transmission line comprising a
dielectric substance substrate and metal conductors, and diodes or
field effect transistors (FETs) showing distributed parameter
effect.
[0003] 2. Description of the Prior Art
[0004] As a semiconductor switching circuit which is contemplated
for use in microwave as well as millimeter wave bands, in
particular with high frequencies not less than 60 GHz, various
kinds of circuits have been proposed and manufactured for
trial.
[0005] Single-pole 3-throw (SP3T) switches for the 77 GHz band
(hereinafter to be referred to as Conventional example 1) were
reported by M. Case et al. in "1997 MTT-S IMS Digest pp. 1047-1050"
and can be nominated as an example of conventional switches.
[0006] An SP3T switch of Conventional example 1 comprises
configuration as shown in FIG. 12. An input terminal 20 is
connected with a signal junction N via a transmission line 21. One
end of each transmission line 22-24 having length of a quarter of
propagating wave length (a quarter wave length transmission line)
is connected via capacitance C1, C2, and C3 for DC cutting
respectively to each signal junction. The other end of each of a
quarter wave length transmission lines 22-24 is connected
respectively to one end of PIN diode D1, D2, or D3 as well as to
the first, the second, or third output terminal 25-27. The other
end of each PIN diode D1, D2, or D3 is connected with the earth.
Capacitance C1, C2, and C3 for DC cutting, a quarter wave length
transmission lines 22-24, diodes D1, D2, and D3, and the first, the
second, and the third output terminals 25-27 form three output
signal passes.
[0007] A diode can be expressed as a resistance for equivalent
circuit thereof when the diode is biased forward, and can be
expressed as a capacitance for equivalent circuit thereof when the
diode is biased in the reverse direction. Accordingly, when a diode
is biased forward, there exists little impedance, and the anode and
cathode thereof may be regarded to be short-circuited. In addition,
the impedance for frequencies in correspondence with propagating
wave length when this diode is seen via a quarter wave length
transmission line is close to infinite, and thus may be regarded as
almost open. That is, a signal pass where a diode is biased forward
will be seen as almost open from the signal junction, and as a
consequence, an RF signal having propagated the signal pass will be
almost totally reflected. On the other hand, since a diode which is
biased in the reverse direction functions as a capacitance, the
impedance will get high for low frequencies, and accordingly a
signal pass where a diode is biased in the reverse direction is
transparent. As the frequency gets higher, the impedance of a
capacitance gets lower, and therefore, signal reflection at a
signal junction will increase. As a result, a signal pass where a
diode is biased in the reverse direction allows signals to travel
transparently, but on the other hand, an increase in frequency will
result in an increase in loss due to reflection.
[0008] Thus, in switches of Conventional example 1, among the three
output signal passes, the signal pass to make signals travel
transparently comprises a diode, which is biased in the reverse
direction, and on the other hand, the other remaining signal passes
comprise diodes, which are biased forward, to cut off signals on
the other remaining signal passes, which will enable to switch the
signal passes.
[0009] Insertion loss as well as isolation in a single-pole
single-throw (SPST) of Conventional example 1 as described above
can for the purpose of simplicity be supposed that characteristic
impedance of the transmission line equals impedance of the
input-output terminals, and then can be expressed as the equation
(1) and the equation (2). IL = 4 4 + .omega. 2 .times. C 2 .times.
Z 0 2 ( 1 ) I SO = 4 ( 2 + Z 0 R ) ( 2 ) ##EQU1##
[0010] As apparent from the equation (2), isolation is expressed
with the resistance R and the impedance Z.sub.0 of the input-output
terminals, but does not depend on frequencies. In switches of
Conventional example 1, however, when isolation of, for example,
not less than 40 dB is to be attained, the resistance values of
diode will have to be not more than 0.13 .OMEGA.. Here, in the
disclosed document of Conventional example 1, the resistance value
of the diode is described as 3 .OMEGA.. Accordingly, in switches of
Conventional example 1, for the purpose of realizing a resistance
value of 0.13 .OMEGA., the anode electrode area to be multiplied
approximately by 23 will do. However, the anode electrode area
being 23 times as much means that the capacitance value will
simultaneously be 23 times as much as well. As a result, since the
capacitance value of the diode disclosed in the document is 33 fF,
the capacitance to attain isolation of 40 dB will be 759 fF which
is 23 times as much. Based on this, with reference to the equation
(1), insertion loss for a capacitance of 33 fF
(=33.times.10.sup.-15 F) is 0.6 dB, while insertion loss reaches as
much as 19 dB when the anode electrode area is made 23 times as
much. That is, in switching circuit of the above-described
Conventional example 1, insertion loss and isolation are in a
trade-off relationship, and high isolation characteristics such as
40 dB were not attainable.
[0011] In addition, single-pole single-throw (SPST) switches for
the 94 GHz band (hereinafter to be referred to as Conventional
example 2) were reported by H. Takasu et al. in "IEEE MICROWAVE AND
GUIDED LETTERS, Vol. 6, pp. 315-316" and can be nominated,
conventionally, as an example of another switch. This switch of
Conventional example 2 is also one of possible circuits as
switching circuits for high frequency bands not less than 60
GHz.
[0012] An SPST switch of Conventional example 2 comprises
configuration as shown in FIG. 13. An SPST switch of Conventional
example 2 comprises a field effect transistor (FET), an inductor,
and a resistance. The input-output terminals 31, 32 are
respectively connected with the source and drain of an FET, between
which an inductor L configured with a microstrip line pass is
connected in parallel. To the gate of FET, a resistance R of 2.5
k.OMEGA. is connected, and via the resistance a direct current bias
is arranged to be applied to the gate. In the state that the
channel of FET is closed, the FET can be treated equivalently as a
capacitance C, which, therefore, as shown in FIG. 14, together with
the inductance L connected with the FET in parallel, resonance
takes place at a frequency obtainable from the equation (3), and as
a consequence, resulting in high impedance so that signal
propagation between the input-output terminals will be cut off.
That is, the switch enters the off state. f = 1 2 .times. .pi.
.times. LC ( 3 ) ##EQU2##
[0013] FIG. 15 shows frequency characteristics on insertion loss as
well as isolation in the switch of Conventional example 2. As
obvious from FIG. 15, in the switching circuit of Conventional
example 2, isolation characteristics around 30 dB are attainable
with comparatively low insertion loss. However, since, as described
before, the switching circuit of Conventional example 2 makes use
of resonance, its frequency characteristics will fall in narrow
band width. Moreover, for the purpose of making a resonance circuit
start resonance at a desired frequency, it is necessary to
accurately know LC being a constant of the circuit. Accordingly,
for the purpose of using a switch of Conventional example 2, not
only the capacitance C to appear at closure of the FET channel will
have to be accurately estimated, but also as concerns the inductor
L accurate modeling will become necessary. On the contrary, FETs as
well as PIN diodes, etc., normally have variation of forming
process to a certain extent, but for example, due to this
variation, the value of capacitance C could deviate from the
design, and as a result the resonance frequency will deviate from
the design as well, and resonance will not be available at a
desired frequency, which, as a consequence, will give rise to
reduction of yield.
[0014] Switching circuits (hereinafter to be referred to as
Conventional example 3) were conventionally proposed by H. Mizutani
and Y. Takayama in "1997 MTT-S IMS Digest pp. 439-442" and can be
nominated as technology to solve the problems with the
aforementioned Conventional example 1 as well as Conventional
example 2. The switching circuit of Conventional example 3 is a
switching circuit utilizing an FET showing distributed parameter
effect, and its wide band width characteristics were proved in the
document. Incidentally, the contents of the document has been
disclosed in Japanese Patent Laid-Open No. 10-41404 specification
as well.
[0015] A switching circuit of Conventional example 3 comprises the
configuration as shown in FIG. 16. As understandable with reference
to FIG. 16, the switching circuit of Conventional example 3
comprises plural transmission lines and plural FETS. For the
switching circuit of Conventional example 3 in detail, each
transmission line as well as each FET is respectively defined per
micro unit length, and transmission lines are connected in series,
and the drain of each FET is connected to the respective junction
of them. Incidentally, the source of each FET is connected with the
earth. The configuration is made in an infinite connection of these
transmission line as well as FET per micro unit length.
[0016] Such switching circuit of Conventional example 3 is
implemented as a plane surface pattern, where each FET (hereinafter
to be referred to as distributed parameter FET) comprises a source
connected with the earth, a gate finger with a length of 400 .mu.m,
and a drain electrode, both longitudinal ends of which have been
connected with the input-output terminals.
[0017] A switching circuit of Conventional example 3 comprising
such a configuration acts equivalently as a transmission line
without any loss as shown in FIG. 17 in the state that the channel
of FET is closed. As apparent from FIG. 17, the switch enters the
ON state, and insertion loss is expressed by the equation (4)
through the equation (6). S 21 ON = 2 .times. ZZ 0 2 .times. ZZ 0
.times. cos .times. .times. .beta.1 + j .times. .times. ( Z 2 + Z 0
2 ) .times. .times. sin .times. .times. .beta.1 ( 4 ) .beta. =
.omega. .times. ( L .times. .times. ( C IL + C FET ) ( 5 ) Z = L (
C IL + C FET ) ( 6 ) ##EQU3##
[0018] Here, "Z" represents impedance of the switch, "1" represents
length of a finger of an FET, Z.sub.0 represents impedance of the
input-output terminal. In addition, ".omega." represents angular
frequency, and L, R, C, and G respectively represent inductance,
resistance, parallel capacitance, parallel conductance per unit
length of the switch.
[0019] On the other hand, an FET is equivalently expressed as a
mere resistance in the state where its channel is open, thus, the
equivalent circuit on the switch at that time will be as shown in
FIG. 18. As understandable with reference to FIG. 18, a switching
circuit of Conventional example 3 acts equivalently as a
transmission line with loss in the state that the channel of FET is
open, that is, the switch enters the OFF state, and its isolation
can be expressed by the equation (7) through the equation (9). S 21
ON = 2 .times. ZZ 0 2 .times. ZZ 0 .times. cosh .times. .times.
.psi. + ( Z 2 + Z 0 2 ) .times. .times. sinh .times. .times. .psi.
( 7 ) .gamma. .ident. .alpha. + j.beta. .ident. j.omega. .times.
.times. L .times. .times. ( j.omega. .times. .times. C IL + G ) ( 8
) Z = j.omega. .times. .times. L j.omega. .times. .times. C IL + G
( 9 ) ##EQU4##
[0020] From these equations, in a wide band as shown in FIG. 19,
low insertion loss and high isolation are obtainable. As
understandable from FIG. 19, frequency characteristics of isolation
in the switching circuit of Conventional example 3 are in gradual
increase.
[0021] However, not only in switching circuits of the
above-described Conventional example 1 as well as Conventional
example 2 without doubt, but also in switching circuit of
Conventional example 3 it was practically difficult to maintain low
insertion loss and realize high isolation in a wide band as a
comparatively compact type. This point is explained in detail as
follows.
[0022] In a switch according to Conventional example 3, the
0.sup.th digit term concerning the frequency of isolation is
expressed by the equation (10). IL DC = ( 2 2 + Z 0 r ) 2 ( 10 )
##EQU5##
[0023] As understandable from the equation (10), as resistance "r"
of distributed parameter FET gets smaller, isolation gets greater.
Incidentally, in the switching circuit using a distributed
parameter FET, the 0.sup.th digit close resemblance on the
isolation frequency corresponds with the isolation of the switching
circuit with shunt configuration using a lumped constant FET
expressed in the aforementioned equation (2).
[0024] Accordingly, for the purpose of attaining high isolation in
the switching circuit of Conventional example 3, the gate finger
length must be lengthened so that the resistance "r" of distributed
parameter FET be reduced. In particular, for the purpose of
attaining high isolation of not less than 80 dB in the switching
circuit of Conventional example 3, the gate finger length must be
lengthened to, for example, 1 mm so that the resistance "r" of
distributed parameter FET be reduced. To extend the gate finger
length like this means the chip size of microwave or millimeter
wave single integrated circuit (MMIC) will get bigger.
[0025] As understandable from these features, in microwave or
millimeter wave band switching circuits there was a problem that it
was difficult for the prior art to realize high isolation of not
less than 80 dB covering a wide band width with a comparatively
small type configuration, while maintaining low insertion loss.
This was originated in circuit configurations in the respective
prior arts, such as, existence respectively of the trade-off
relationship between insertion loss and isolation, narrow band
width characteristics due to usage of resonance, or the trade-off
relationship between resistance of distributed parameter FET and
the chip size.
BRIEF SUMMARY OF THE INVENTION
OBJECT OF THE INVENTION
[0026] The present invention was made contemplating on those
problems presented by these prior arts, and in particular the
purpose thereof is to provide small-sized switching circuits for
microwave or millimeter wave band which can attain high isolation
of not less than 80 dB covering a wide band width with a low loss,
which the prior arts were hardly successful in realizing in high
frequencies not less than 60 GHz.
SUMMARY OF THE INVENTION
[0027] The present invention provides semiconductor switches and
switching circuits shown as follows as means for solving the
above-described problems.
[0028] Operation of semiconductor switches and switching circuits
of the present invention comprising such configuration can be
explained as follows by exemplifying a first semiconductor switch
as well as a third semiconductor switch for example.
[0029] The first semiconductor switch as well as the third switch
circuit according to the present invention functions as a coplanar
line without any loss under the ON state, and functions as a
coplanar line with loss under the OFF state. On such points, these
switches are similar to those switching circuits of Conventional
example 3. Accordingly, the insertion loss of switches according to
the present invention is expressed by the aforementioned equations
(4) through (6), and likewise isolation is expressed by the
equations (7) through (9). Moreover, in the switches according to
the present invention, isolation gradually increases on
frequency.
[0030] As described above, in the switching circuit functioning as
a coplanar line without loss and with loss respectively in the ON
state and in the OFF state, the 0.sup.th digit close resemblance on
the isolation frequency is expressed by the equation (10). In
addition, as being understood from this equation, larger isolation
may be obtained by reducing the resistance "r", which is as
mentioned before.
[0031] Qualitatively, with a constant sheet resistance value, wider
width of an element reduces the resistance value, and longer length
of an element increases the resistance value, which is generally
known.
[0032] Here, with the width of an FET being constant, comparison
between the switching circuits of Conventional example 3 and
semiconductor switches and switching circuits according to the
present invention leads to the following understanding. That is,
the resistance value of the distributed parameter FET in
Conventional example 3 is already defined by the source-drain
distance. On the contrary, the resistance values of the resistance
defining isolation in the switches according to the present
invention depend on the gate-source, and the gate-drain distances.
In detail, a switch according to the present invention comprises
such a configuration that the source, the gate, and the drain of a
so-called Schottky barrier FET are enclosed by an active layer, and
the source as well as the drain is connected with the earth. Thus,
when forward bias voltage which is to determine the current value
to flow to the gate by the source-drain resistance is supplied as
gate voltage to between the gate and source as well as between the
gate and the drain, the resistance which determines the isolation
in the switches of the present invention is understood to be the
source resistance between the gate and the source or the drain
resistance between the gate and the drain of Schottky barrier
diode. That is, unlike Conventional example 3, in the switches
according to the present invention, the resistance value to
determine isolation is determined by distances between gate and
source as well as between gate and drain. This leads to
understanding that the resistance value of the resistance to
determine isolation in the switches of the present invention is
simply considered to be decreased to approximately a half of that
of Conventional example 3 since the gate electrode of an FET to be
used for switches is disposed in general in the middle between the
source and the drain. Incidentally, for easier understanding, the
contact resistance is set to be constant. As understandable from
the foregoing, the semiconductor switches according to the present
invention can realize compactness as well as lower loss, and high
isolation when compared with not only Conventional examples 1 and 2
but also Conventional example 3.
BRIEF DESCRIPTION OF THE DRAWINGS
[0033] This above-mentioned and other objects, features and
advantages of this invention will become more apparent by reference
to the following detailed description of the invention taken in
conjunction with the accompanying drawings, wherein:
[0034] FIG. 1A is a plan view showing a semiconductor switch
according to a first embodiment of the present invention and FIG.
1B is a cross sectional view taking along a line 1' of FIG. 1A;
[0035] FIG. 2 is a circuit diagram showing a switching circuit
equivalent to the semiconductor switch according to the first
embodiment of the present invention;
[0036] FIG. 3 is a graph showing frequency characteristics on
insertion loss as well as isolation of the semiconductor switch
according to an example in correspondence with the first embodiment
of the present invention;
[0037] FIG. 4A is a plan view showing the semiconductor switch
according to a second embodiment of the present invention and FIG.
4B is a cross sectional view takng along a line 4' of FIG. 4A;
[0038] FIG. 5 is a circuit diagram showing the switching circuit
equivalent to the semiconductor switch according to the second
embodiment of the present invention;
[0039] FIG. 6 is a graph showing frequency characteristics on
insertion loss as well as isolation of the semiconductor switch
according to an example in correspondence with the second
embodiment of the present invention, which is controlled by using
only negative electric power;
[0040] FIG. 7 is a graph showing frequency characteristics on
insertion loss as well as isolation of the semiconductor switch
according to an example in correspondence with the second
embodiment of the present invention, which was controlled by using
both positive and negative electric power;
[0041] FIG. 8A is a plan view showing the semiconductor switch
according to a third embodiment of the present invention and FIG.
8B is a cross sectional view taking along a line 8' of FIG. 8A;
[0042] FIG. 9 is a circuit diagram showing the switching circuit
equivalent to the semiconductor switch according to the third
embodiment of the present invention;
[0043] FIG. 10 is a graph showing frequency characteristics on
insertion loss as well as isolation of the semiconductor switch
according to one example in correspondence with the third
embodiment of the present invention;
[0044] FIG. 11 is a graph showing frequency characteristics on
insertion loss as well as isolation of the semiconductor switch
according to another example in correspondence with the third
embodiment of the present invention;
[0045] FIG. 12 is a circuit diagram showing an SP3T switch of
Conventional example 1;
[0046] FIG. 13 is a circuit diagram showing an SPST switch of
Conventional example 2;
[0047] FIG. 14 is an equivalent circuit diagram showing an OFF
state SPST switch of Conventional example 2;
[0048] FIG. 15 is a graph showing frequency characteristics on
insertion loss as well as isolation of the SPST switch of
Conventinal example 2;
[0049] FIG. 16 is an equivalent circuit diagram showing an SPST
switch of Conventional example 3;
[0050] FIG. 17 is an equivalent circuit diagram showing an ON state
SPST switch of Conventional example 3;
[0051] FIG. 18 is an equivalent circuit diagram showing an OFF
state SPST switch of Conventional example 3; and
[0052] FIG. 19 is a graph showing frequency characteristics on
insertion loss as well as isolation of the SPST switch of
Conventinal example 3.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0053] The semiconductor switch according to a first embodiment of
the present invention comprises the configuration as shown in FIGS.
1A and 1B, and the switching circuit according to the first
embodiment of the present invention comprises the configuration as
shown in FIG. 2.
[0054] With reference to FIG. 1, the semiconductor switch according
to the present embodiment comprises the source electrode 4, drain
electrode 5, and the gate electrode 6 which are enclosed by an
active layer 3. These electrodes are disposed in parallel to each
other in a predetermined direction on the semiconductor substrate
(in this example, in the right-left lateral direction on the paper
surface). The source electrode 4 and the drain electrode 5 are
respectively connected with-the earth, and the gate electrode 6 is
disposed in between these source electrode 4 and drain electrode 5.
Both the ends of the gate electrode 6 in the predetermined
direction operate respectively as the first and the second
input-output units, and are connected to the first input-output
terminal 1 and the second input-output terminal 2.
[0055] Circuit-wise, as shown in FIG. 2, this configuration is
equivalent to a switching circuit comprising the coplanar lines and
field effect transistors, wherein the first input-output terminal 1
is connected with one end of the signal line of the first coplanar
line 9, and the gate of the first field effect transistor 10 is
connected with the other end of the signal line of the first
coplanar line 9, and the second input-output terminal 2 is
connected with one end of the signal line of the second coplanar
line 11, and the gate of the second field effect transistor 12 is
connected with the other end of the signal line of the second
coplanar line 11, and further, to and between the first field
effect transistor 10 and the second field effect transistor 12
plural coplanar lines and plural field effect transistors are
alternately connected in series. Incidentally, in the present
embodiment, each coplanar line comprises such a configuration that
the signal line is sandwiched by a grounded conductor, and each
field effect transistor is a distributed parameter FET, and its
source as well as its drain is connected with the earth. Thus
configured semiconductor switches and switching circuits are
mounted as a plane pattern where in the distributed parameter FET
the source electrode as well as the drain electrode of which is
connected with the earth the input-output terminal has been
connected with both the ends of the gate electrode disposed in the
longitudinal direction, and also can be easily formed by connecting
the source-drain electrodes of MESFET (metal-semiconductor
field-effect transistor) with the earth.
[0056] The semiconductor switch and the switching circuits
comprising such configurations are arranged so that positive
voltage as well as zero bias is applied to the gate electrode 6
outside the active layer 3 by a not-shown bias line via a
resistance. At this time, when required, capacitance C1, C2, and C3
for DC cutting is inserted between the gate electrode 6 and each
input-output terminal.
[0057] When positive voltage is applied to the gate electrode 6,
and a current flows into the gate electrode, forward bias is to be
given to between the gate and the source as well as between the
gate and the drain, which can be regarded as short-circuited. At
this time, a gate-source line as well as a gate-drain line can
respectively be equivalently expressed as a resistance, and
accordingly, an equivalent circuit of the switch will be a coplanar
line with loss in shunt due to conductance. That is, the switch
enters the OFF state. The isolation characteristics under this
state can be calculated by the aforementioned equations (7) through
(9), using the conductance G of shunt.
[0058] On the other hand, in the case where zero bias is supplied
to the gate electrode 6, lines between the gate and the source as
well as between the gate and the drain can be regarded as open, and
their equivalent circuits can be expressed in capacitance. At this
time, the switch is equivalently the same as circuit configuration
of a coplanar line without loss, and enters the ON state.
[0059] Here, the semiconductor switch and the switching circuits
according to the present embodiment are partly characterized by low
characteristic impedance of the coplanar line due to shunt
capacitance between the gate and the source as well as between the
gate and the drain. Accordingly, mismatching between characteristic
impedance and impedance of the input-output terminal will give rise
to reflection, and that reflection will give rise to insertion
loss. This insertion loss can be calculated by the aforementioned
equations (4) through (6). With the semiconductor switch and the
switching circuits according to the present embodiment, switching
between the ON state and the OFF state can be conducted by a
positive electric power, which is additional characteristics.
[0060] For the purpose of cultivating better understanding on the
present embodiment, an example of the semiconductor switch and the
switching circuits will be introduced hereunder, and explained in
detail with reference to the drawings.
[0061] In the present example, a heterojunction FET of AlGaAs and
InGaAs systems was used as the FET in the above-described first
embodiment. In detail, referring to FIG. 1B, a n-AlGaAs layer is
formed on an i-GaAs layer. An i-InGaAs layer as a channel layer is
formed on the n-AlGaAs layer. A n-AlGaAs layer is formed on the
i-InGaAs layer. 2 n.sup.+-GaAs layers are formed on the n-AlGaAs
layer apart from each other. The gate electrode 6 is formed on the
n-AlGaAs layer between the n.sup.+-GaAs layers. The gate electrode
6 is made by aluminum, gold, molybdenum, titanium, or tungsten
silicide. The source electrode 4 is formed on one of the
n.sup.+-GaAs layer. The drain electrode 5 is formed on the other of
the n.sup.+-GaAs layer. The source and drain electrodes are made by
an alloy including AuGe or nickel. In addition, the area of the
gate electrode 6 was set to 2.times.400 .mu.m, and the distances
between the gate electrode 6 and the source electrode 4 or the
drain electrode 5 were set to 2.5 .mu.m. Moreover, the first
input-output terminal 1 and the second input-output terminal 2 are
respectively connected with both the ends of the gate electrode 6,
and further, 50 .OMEGA. loads are respectively connected with the
first input-output terminal 1 and the second input-output terminal
2. Incidentally, capacitance with zero bias between the gate and
the source and between the gate and the drain is 20 fF per 100
.mu.m, and on the other hand, resistance with forward bias is 3.3
.OMEGA. per 100 .mu.m. In addition, entire length of the coplanar
line is 400 .mu.m.
[0062] In the semiconductor switch according to the present example
comprising such configuration, 2 V and 0 V are applied to the gate
so as to alternate the ON and OFF states. The principle of its
operation is as described before.
[0063] Frequency characteristics on insertion loss as well as
isolation of the semiconductor switch according to the present
example are shown in FIG. 3. As understandable with reference to
FIG. 3, both show wide band width characteristics, and insertion
loss at 76.0 GHz is 1.7 dB, and isolation is 81 dB. That is, the
semiconductor switch according to the present example is the one
which has realized high isolation of not less than 80 dB,
maintaining low insertion loss, which was conventionally hardly
successful in realizing in high frequencies not less than 60 GHz.
Such effects become obtainable since, as mentioned before, in the
switch in the OFF state conductance of shunt is twice as much as
that in switching circuits according to the prior arts, that is,
resistance is reduced by half. Incidentally, it goes without saying
that the switch according to the present example features its
operability only by positive electric power as described above.
[0064] The semiconductor switch according to a second embodiment of
the present invention comprises the configuration as shown in FIGS.
4A and 4B, and the switching circuit according to the second
embodiment of the present invention comprises the configuration as
shown in FIG. 5.
[0065] With reference to FIG. 4A, the semiconductor switch
according to the present embodiment comprises the two anode
electrodes 7, and the cathode electrode 8 which are enclosed by an
active layer 3. From two anode electrodes 7, one together with the
cathode electrode 8 forms a Schottky barrier diode. In detail,
referring to FIG. 4B, an i-AlGaAs layer is formed on an i-GaAs
layer. An i-InGaAs layer as a channel layer is formed on the
i-AlGaAs layer. A n-AlGaAs layer is formed on the i-InGaAs layer.
The anode electrodes 7 are formed on the n-AlGaAs layer apart from
each other. The cahorde electrode 8 is formed on the n-AlGaAs layer
through a n.sup.+-GaAs layers. The anode electrode 7 are made by
aluminum, gold, molybdenum, titanium, or tungsten silicide. The
cathodelectrode is made by an alloy including AuGe or nickel. In
addition, the other anode electrode 7, likewise, together with the
cathode electrode 8 may be considered to form a Schottky barrier
diode, or may be considered to be an additional electrode
established as an annex to the Schottky barrier diode. Anyway the
two anode electrodes 7 are both connected with the earth, and are
disposed in parallel to each other in a predetermined direction on
the semiconductor substrate (in this example, in the right-left
lateral direction on the paper surface). In addition, the cathode
electrode 8 is disposed so as to be sandwiched between the two
anode electrodes 7 as well as, likewise, to be in parallel to each
other in a predetermined direction on the semiconductor substrate.
The anode electrodes 7 have undergone Schottky junction with
semiconductor crystal, and the cathode electrode 8 has undergone
ohmic junction with semiconductor crystal. Both the ends of the
cathode electrode 8 in the predetermined direction operate
respectively as the first input-output unit and the second
input-output unit, and are respectively connected with the first
input-output terminal 1 and the second input-output terminal 2.
Such semiconductor switches are driven by supplying the cathode
electrode 8 with negative voltage as well as zero bias outside the
active layer 3 by a not-shown bias line via a resistance. At this
time, when required, capacitance C1, C2, and C3 for DC cutting is
inserted between the cathode electrode 8 and each input-output
terminal.
[0066] Circuit-wise, as shown in FIG. 5, this configuration is
equivalent to a switching circuit comprising the coplanar lines and
diodes, wherein the first input-output terminal 1 is connected with
one end of the signal line of the first coplanar line 9, and the
cathode of the first diode 13 is connected with the other end of
the signal line of the first coplanar line 9, and the second
input-output terminal 2 is connected with one end of the signal
line of the second coplanar line 11, and the cathode of the second
diode 14 is connected with the other end of the signal line of the
second coplanar line 11, and further, to and between the first
diode 13 and the second diode 14 plural coplanar lines and plural
diodes are alternately connected in series. Incidentally, in the
present embodiment, each coplanar line comprises such a
configuration that the signal line is sandwiched by the grounded
conductor, and each diode is a distributed parameter diode, and its
anode is connected with the earth.
[0067] For the purpose of cultivating a better understanding on the
present embodiment, an example of the semiconductor switch and the
switching circuits will be introduced hereunder, and explained in
detail with reference to the drawings.
[0068] In the present example, the area of the cathode electrode 8
was set to 5.times.400 .mu.m, and the distance between the cathode
electrode 8 and the anode electrode 7 was set to 3 .mu.m. In
addition, the first input-output terminal 1 and the second
input-output terminal 2 are respectively connected with both the
ends of the cathode electrode 8, and further, 50 .OMEGA. loads are
respectively connected with the first input-output terminal 1 and
the second input-output terminal 2. Incidentally, capacitance with
zero bias between the cathode and the anode is 20 fF per 100 .mu.m,
and on the other hand, resistance with forward bias is 4 .OMEGA.
per 100 .mu.m. In addition, entire length of the coplanar line is
400 .mu.m.
[0069] In the semiconductor switch according to the present example
comprising such configuration, negative voltage (-2 V for the
present example), and zero bias are supplied to the cathode so as
to alternate the states of the switch. That is, when negative
voltage is applied to the cathode of the semiconductor switch
according to the present example, forward bias is to be given to
the diode, an equivalent circuit of which is expressed by
resistance, thus the switch can be regarded as a coplanar line with
loss in shunt due to conductance. That is, at this time, the switch
enters the OFF state. On the other hand, when zero bias was
supplied to the cathode of the semiconductor switch according to
the present example, an equivalent circuit of the diode is
expressed by capacitance, thus the switch is equivalent to a
coplanar line without loss. Accordingly, the switch enters the ON
state.
[0070] Frequency characteristics on insertion loss as well as
isolation of the semiconductor switch according to the present
example are shown in FIG. 6. As understandable with reference to
FIG. 6, both show wide band width characteristics, and insertion
loss at 110.0 GHz is 1.7 dB, and isolation is 82 dB. That is, it
can be easily understood that the semiconductor switch according to
the present example is the one which has realized high isolation of
not less than 80 dB, maintaining low insertion loss, which was
conventionally hardly successful in realizing in high frequencies
not less than 60 GHz.
[0071] Here, both of positive and negative electric power should be
applicable to the cathode. In this case, the diode is to be biased
in the opposite direction when the positive voltage is 5 V, its
capacity will decrease compared with that at the time of zero bias.
In addition, at this time the switch is in the ON state, but the
impedance of the switch approaches 50 .OMEGA. and thus insertion
loss gets lowered.
[0072] Frequency characteristics on insertion loss as well as
isolation of the semiconductor switch according to the present
example in this case are shown in FIG. 7. As obvious with reference
to FIG. 7, compared with the time of zero bias, insertion loss is
reduced to 1.5 dB at 110.0 GHz. Incidentally, as obvious from the
aforementioned equations (7) through (9), isolation, which does not
depend on capacitance of diodes, is 82 dB, which remains same as in
the time of zero bias without any changes to occur.
[0073] The semiconductor switch according to a third embodiment of
the present invention comprises the configuration as shown in FIGS.
8A and 8B, and the switching circuit according to the third
embodiment of the present invention comprises the configuration as
shown in FIG. 9.
[0074] With reference to FIG. 8, the semiconductor switch according
to the present embodiment comprises two cathode electrodes 8, and
the anode electrode 7 which are enclosed by an active layer 3. From
two cathode electrodes 8, one together with the anode electrode 7
form a Schottky barrier diode. In addition, the other cathode
electrode 8, likewise, together with the anode electrode 7 may be
considered to form a Schottky barrier diode, or may be considered
to be an additional electrode established as an annex to the
Schottky barrier diode. Anyway the two cathode electrodes 8 are
both connected with the earth, and are disposed in parallel to each
other in a predetermined direction on the semiconductor substrate
(in this example, in the right-left lateral direction on the paper
surface). In addition, the anode electrode 7 is disposed so as to
be sandwiched between the two cathode electrodes 8 as well as,
likewise, to be in parallel to each other in a predetermined
direction on the semiconductor substrate. The anode electrode 7 has
undergone Schottky junction with semiconductor crystal, and the
cathode electrodes 8 have undergone ohmic junction with
semiconductor crystal. In detail, referring to FIG. 8B, an i-AlGaAs
layer is formed on an i-GaAs layer. An i-InGaAs layer as a channel
layer is formed on the i-AlGaAs layer. A n-AlGaAs layer is formed
on the i-InGaAs layer. The cathodelectrodes 8 are formed on the
n-AlGaAs layer apart from each other through the respective
n.sup.+-GaAs layer. The anode electrode 7 is formed on the n-AlGaAs
layer. The anode electrode 7 is made by aluminum, gold, molybdenum,
titanium, or tungsten silicide. The cathodelectrodes 8 are made by
an alloy including AuGe or nickel. Both the ends of the anode
electrode 7 in the predetermined direction operate respectively as
the first input-output unit and the second input-output unit, and
are respectively connected with the first input-output terminal 1
and the second input-output terminal 2. Such semiconductor switches
are driven by supplying the anode electrode 7 with positive voltage
as well as zero bias outside the active layer 3 by a not-shown bias
line via a resistance.
[0075] Circuit-wise, as shown in FIG. 9, this configuration is
equivalent to a switching circuit comprising the coplanar lines and
diodes, wherein the first input-output terminal 1 is connected with
one end of the signal line of the first coplanar line 9, and the
anode of the first diode 13 is connected with the other end of the
signal line of the first coplanar line 9, and the second
input-output terminal 2 is connected with one end of the signal
line of the second coplanar line 11, and the anode of the second
diode 14 is connected with the other end of the signal line of the
second coplanar line 11, and further, to and between the first
diode 13 and the second diode 14 plural coplanar lines and plural
diodes are alternately connected in series. Incidentally, in the
present embodiment, each coplanar line comprises the configuration
that the signal line is sandwiched by conductor connected with the
earth, and each diode is a distributed parameter diode, and its
cathode is connected with the earth.
[0076] For the purpose of cultivating a better understanding on the
present embodiment, an example of the semiconductor switch and the
switching circuits is introduced hereunder, and is explained in
detail with reference to the drawings.
[0077] In the present example, the area of the anode electrode 7
was set to 10.times.400 .mu.m, and the distance between the cathode
electrode 8 and the anode-electrode 7 was set to 3 .mu.m. In
addition, the first input-output terminal 1 and the second
input-output terminal 2 are respectively connected with both the
ends of the anode electrode 7, and further, 50 .OMEGA. loads are
respectively connected with the first input-output terminal 1 and
the second input-output terminal 2. Incidentally, capacitance with
zero bias between the cathode and the anode is 20 fF per 100 .mu.m,
and on the other hand, resistance with forward bias is 4 .OMEGA.
per 100 .mu.m. In addition, entire length of the coplanar line is
400 .mu.m.
[0078] In the semiconductor switch according to the present example
comprising such configuration, positive voltage (2 V for the
present example), and zero bias are supplied to the anode so as to
alternate the states of the switch. That is, when positive voltage
is applied to the anode of the semiconductor switch according to
the present example, forward bias is to be given to the diode, an
equivalent circuit of which is expressed by resistance, thus the
switch can be regarded as a coplanar line with loss in shunt due to
conductance. That is, at this time, the switch enters the OFF
state. On the other hand, when zero bias was supplied to the anode
of the semiconductor switch according to the present example, an
equivalent circuit of the diode is expressed by capacitance, thus
the switch is equivalent to a coplanar line without loss.
Accordingly, the switch enters the ON state.
[0079] Frequency characteristics on insertion loss as well as
isolation of the semiconductor switch according to the present
example are shown in FIG. 10. As understandable with reference to
FIG. 10, both of insertion loss and isolation show the same wide
band width characteristics as in two examples respectively in
correspondence with the aforementioned first and second
embodiments. In addition, insertion loss at 114.0 GHz is 1.6 dB,
and isolation is 79 dB. That is, it can be easily understood that
the semiconductor switch according to the present example is the
one which has realized high isolation of around 80 dB, maintaining
low insertion loss, which was conventionally hardly successful in
realizing in high frequencies not less than 60 GHz.
[0080] FIG. 11 is a graph showing frequency characteristics on
insertion loss as well as isolation of the semiconductor switch
according to the other example in correspondence with the third
embodiment. In the present example, the area of the anode electrode
7 was set to 10.times.400 .mu.m, and the distance between the
cathode electrode 8 and the anode electrode 7 was set to 2.5 .mu.m.
In addition, the first input-output terminal 1 and the second
input-output terminal 2 are respectively connected with both the
ends of the anode electrode 7, and further, 50 .OMEGA. loads are
respectively connected with the first input-output terminal 1 and
the second input-output terminal 2. Capacitance with zero bias
between the cathode and the anode is 20 fF per 100 .mu.m, and on
the other hand, resistance with forward bias is 3.3 .OMEGA. per 100
.mu.m. In addition, entire length of the coplanar line is 400
.mu.m.
[0081] In the semiconductor switch according to the present example
comprising such configuration, unlike the foregoing example, the
case where alternation of ON and OFF of the switch is conducted by
way of applying both positive and negative electric power to the
anode is examined. For example, the switch enters the OFF state
with application of 2 V, and the switch enters the ON state with
application of -5 V. As understandable with reference to FIG. 11,
both of insertion loss and isolation show the same wide band width
characteristics as in the above-described three examples. In
addition, insertion loss at 134.0 GHz is 1.5 dB, and isolation is
85 dB. That is, it can be easily understood that the semiconductor
switch according to the present example is also the one which has
realized high isolation of not less than 80 dB, maintaining low
insertion loss, which was conventionally hardly successful in
realizing in high frequencies not less than 60 GHz.
[0082] Incidentally, in each of the above-exemplified examples, it
has been explained that entire length of the coplanar line is 400
.mu.m, which is of course a mere example, and it goes without
saying that the length is not limited to the 400 .mu.m. This length
is one of design parameters to attain necessary insertion loss as
well as isolation. In addition, it goes without saying that the
present invention is applicable to transmission lines in general
without being limited to coplanar lines.
[0083] As explained above, according to the present invention, high
isolation of not less than 80 dB is attainable, maintaining low
insertion loss also in high frequencies not less than 60 GHz. This
effect is originated in usage of low-value resistance in the amount
of, for example, approximately a half of that for switches using
the resistance between the source and the drain in a conventional
FET having distributed parameter effect. Perhaps, that is because
the distances between the anode and cathode in a diode, and between
the gate and the drain as well as between the gate and the source
in an FET can be set shorter than the distance between the source
and the drain in the FET.
[0084] Moreover, the above-described first and third embodiments
use only positive electric power to control the switch and do not
need to comprise negative power supply circuits, which point can be
referred to as effective.
* * * * *