U.S. patent application number 11/406031 was filed with the patent office on 2006-08-31 for computer instruction value field having an embedded sign.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Mark A. Check, Brian B. Moore, Timothy J. Slegel.
Application Number | 20060195680 11/406031 |
Document ID | / |
Family ID | 35461862 |
Filed Date | 2006-08-31 |
United States Patent
Application |
20060195680 |
Kind Code |
A1 |
Check; Mark A. ; et
al. |
August 31, 2006 |
Computer instruction value field having an embedded sign
Abstract
A computer machine instruction is fetched and executed, the
machine instruction having a signed field value wherein the signed
field value comprises contiguous bit positions 1-N consisting of a
contiguous most significant value contiguous with a contiguous
embedded sign field, the embedded sign field contiguous with a
contiguous least significant value. Preferably, the sign field is
one bit, the contiguous most significant value comprises bit
position N and the least significant value comprises bit position 1
wherein N is the least significant bit of the most significant
value.
Inventors: |
Check; Mark A.; (Hopewell
Junction, NY) ; Moore; Brian B.; (Poughkeepsie,
NY) ; Slegel; Timothy J.; (Staatsburg, NY) |
Correspondence
Address: |
INTERNATIONAL BUSINESS MACHINES CORPORATION
IPLAW DEPARTMENT
2455 SOUTH ROAD - MS P386
POUGHKEEPSIE
NY
12601
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
35461862 |
Appl. No.: |
11/406031 |
Filed: |
April 18, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10403417 |
Mar 28, 2003 |
|
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11406031 |
Apr 18, 2006 |
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Current U.S.
Class: |
712/221 ;
712/E9.028 |
Current CPC
Class: |
G06F 9/30167 20130101;
G06F 9/30145 20130101 |
Class at
Publication: |
712/221 |
International
Class: |
G06F 9/44 20060101
G06F009/44 |
Claims
1. A method comprising: fetching a first machine instruction for
execution, the machine instruction defined for computer execution
according to a computer architecture, the first machine instruction
comprising an opcode field, the first machine instruction
associated with a signed field, the signed field consisting of a
contiguous signed value, the contiguous signed value consisting of
a contiguous first magnitude field adjacent to a sign field, the
sign field adjacent to a contiguous second magnitude field;
extracting a magnitude value from the signed value; extracting a
sign indicator from the sign field; and using the extracted sign
indicator and the extracted magnitude value to perform a first
function defined by the opcode field.
2. The method according to claim 1, wherein the first machine
instruction is a signed displacement machine instruction, the
signed displacement machine instruction comprising a signed
displacement field, the signed displacement field consisting of the
contiguous signed value.
3. The method according to claim 1, wherein the sign field consists
of bit position S consisting of said sign indicator wherein the
first magnitude field consists of contiguous bit positions 1
through S-1 and the second magnitude field consists of bit
positions S+1 through N, wherein the first magnitude field consists
of a first magnitude value, wherein the second magnitude field
consists of a second magnitude value.
4. The method according to claim 1, wherein the extracting step
comprises concatenating the first magnitude value with the second
magnitude value to form the magnitude value the second magnitude
value consisting of least significant bits of the magnitude value
the first magnitude value consisting of most significant bits of
the magnitude value.
5. The method according to claim 4, comprising the further steps
of: concatenating the sign indicator with the most significant bit
position of the magnitude value to form a signed magnitude value;
and using the signed magnitude value in the using step to perform a
function defined by the opcode field.
6. The method according to claim 5, comprising the further steps
of: obtaining an operand base address from a location specified by
an operand base address field of the signed displacement machine
instruction; if the sign indicator is negative, arithmetically
subtracting the magnitude value from the operand base address to
determine an address of an operand; if the sign indicator is
positive, arithmetically adding the magnitude value to the operand
base address to determine the address of the operand; and
performing the function defined by the opcode field, wherein the
function uses the operand at the determined address.
7. The method according to claim 1, further comprising the steps
of: fetching a second machine instruction for execution, the second
machine instruction defined for computer execution according to the
computer architecture, the second machine instruction comprising an
associated opcode field, the second machine instruction associated
with an unsigned field, the unsigned field consisting of a
contiguous unsigned value, the contiguous unsigned value consisting
of a contiguous third magnitude field; extracting a third magnitude
value from the unsigned displacement value; and using the extracted
third magnitude value to perform a second function defined by the
associated opcode field.
8. The method according to claim 7, wherein the first function is
the same function as the second function.
9. The method according to claim 1, wherein the first machine
instruction defined for the computer architecture is fetched and
executed by a central processing unit of an alternate computer
architecture, the method comprising the further steps of:
interpreting the first machine instruction to identify a
predetermined software subroutine for emulating the operation of
the first machine instruction, the predetermined software
subroutine comprising a plurality of instructions; and executing
the predetermined software subroutine to perform steps of the
method for executing the first machine instruction.
10. A computer program product, the computer program product
comprising: a storage medium readable by a processing circuit and
storing instructions for execution by the processing circuit for
performing a method comprising: fetching a first machine
instruction for execution, the machine instruction defined for
computer execution according to a computer architecture, the first
machine instruction comprising an opcode field, the first machine
instruction associated with a signed field, the signed field
consisting of a contiguous signed value, the contiguous signed
value consisting of a contiguous first magnitude field adjacent to
a sign field, the sign field adjacent to a contiguous second
magnitude field; extracting a magnitude value from the signed
value; extracting a sign indicator from the sign field; and using
the extracted sign indicator and the extracted magnitude value to
perform a first function defined by the opcode field.
11. The computer program product according to claim 10, wherein the
first machine instruction is a signed displacement machine
instruction, the signed displacement machine instruction comprising
a signed displacement field, the signed displacement field
consisting of the contiguous signed value.
12. The computer program product according to claim 10, wherein the
sign field consists of bit position S consisting of said sign
indicator wherein the first magnitude field consists of contiguous
bit positions 1 through S-1 and the second magnitude field consists
of bit positions S+1 through N, wherein the first magnitude field
consists of a first magnitude value, wherein the second magnitude
field consists of a second magnitude value.
13. The computer program product according to claim 10, wherein the
extracting step comprises concatenating the first magnitude value
with the second magnitude value to form the magnitude value the
second magnitude value consisting of least significant bits of the
magnitude value the first magnitude value consisting of most
significant bits of the magnitude value.
14. The computer program product according to claim 13, comprising
the further steps of: concatenating the sign indicator with the
most significant bit position of the magnitude value to form a
signed magnitude value; and using the signed magnitude value in the
using step to perform a function defined by the opcode field.
15. The computer program product according to claim 14, comprising
the further steps of: obtaining an operand base address from a
location specified by an operand base address field of the signed
displacement machine instruction; if the sign indicator is
negative, arithmetically subtracting the magnitude value from the
operand base address to determine an address of an operand; if the
sign indicator is positive, arithmetically adding the magnitude
value to the operand base address to determine the address of the
operand; and performing the function defined by the opcode field,
wherein the function uses the operand at the determined
address.
16. The computer program product according to claim 10, further
comprising the steps of: fetching a second machine instruction for
execution, the second machine instruction defined for computer
execution according to the computer architecture, the second
machine instruction comprising an associated opcode field, the
second machine instruction associated with an unsigned field, the
unsigned field consisting of a contiguous unsigned value, the
contiguous unsigned value consisting of a contiguous third
magnitude field; extracting a third magnitude value from the
unsigned displacement value; and using the extracted third
magnitude value to perform a second function defined by the
associated opcode field.
17. The computer program product according to claim 16, wherein the
first function is the same function as the second function.
18. The computer program product according to claim 10, wherein the
first machine instruction defined for the computer architecture is
fetched and executed by a central processing unit of an alternate
computer architecture, the computer program product comprising the
further steps of: interpreting the first machine instruction to
identify a predetermined software subroutine for emulating the
operation of the first machine instruction, the predetermined
software subroutine comprising a plurality of instructions; and
executing the predetermined software subroutine to perform steps of
the method for executing the first machine instruction.
19. A system, the system comprising: a memory; a computer system in
communication with the memory, the computer system comprising an
instruction fetching unit for fetching instructions from memory and
one or more execution units for executing fetched instructions;
wherein the computer system includes instructions to execute a
method comprising: fetching a first machine instruction for
execution, the machine instruction defined for computer execution
according to a computer architecture, the first machine instruction
comprising an opcode field, the first machine instruction
associated with a signed field, the signed field consisting of a
contiguous signed value, the contiguous signed value consisting of
a contiguous first magnitude field adjacent to a sign field, the
sign field adjacent to a contiguous second magnitude field;
extracting a magnitude value from the signed value; extracting a
sign indicator from the sign field; and using the extracted sign
indicator and the extracted magnitude value to perform a first
function defined by the opcode field.
20. The system according to claim 19, wherein the first machine
instruction is a signed displacement machine instruction, the
signed displacement machine instruction comprising a signed
displacement field, the signed displacement field consisting of the
contiguous signed value.
21. The system according to claim 19, wherein the sign field
consists of bit position S consisting of said sign indicator
wherein the first magnitude field consists of contiguous bit
positions 1 through S-1 and the second magnitude field consists of
bit positions S+1 through N, wherein the first magnitude field
consists of a first magnitude value, wherein the second magnitude
field consists of a second magnitude value.
22. The system according to claim 19, wherein the extracting step
comprises concatenating the first magnitude value with the second
magnitude value to form the magnitude value the second magnitude
value consisting of least significant bits of the magnitude value
the first magnitude value consisting of most significant bits of
the magnitude value.
23. The system according to claim 22, comprising the further steps
of: concatenating the sign indicator with the most significant bit
position of the magnitude value to form a signed magnitude value;
and using the signed magnitude value in the using step to perform a
function defined by the opcode field.
24. The system according to claim 23, comprising the further steps
of: obtaining an operand base address from a location specified by
an operand base address field of the signed displacement machine
instruction; if the sign indicator is negative, arithmetically
subtracting the magnitude value from the operand base address to
determine an address of an operand; if the sign indicator is
positive, arithmetically adding the magnitude value to the operand
base address to determine the address of the operand; and
performing the function defined by the opcode field, wherein the
function uses the operand at the determined address.
25. The system according to claim 19, further comprising the steps
of: fetching a second machine instruction for execution, the second
machine instruction defined for computer execution according to the
computer architecture, the second machine instruction comprising an
associated opcode field, the second machine instruction associated
with an unsigned field, the unsigned field consisting of a
contiguous unsigned value, the contiguous unsigned value consisting
of a contiguous third magnitude field; extracting a third magnitude
value from the unsigned displacement value; and using the extracted
third magnitude value to perform a second function defined by the
associated opcode field.
26. The system according to claim 25, wherein the first function is
the same function as the second function.
27. The system according to claim 19, wherein the first machine
instruction defined for the computer architecture is fetched and
executed by a central processing unit of an alternate computer
architecture, the system comprising the further steps of:
interpreting the first machine instruction to identify a
predetermined software subroutine for emulating the operation of
the first machine instruction, the predetermined software
subroutine comprising a plurality of instructions; and executing
the predetermined software subroutine to perform steps of the
method for executing the first machine instruction.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This is a divisional application of Ser. No. 10/403,417
"Long Displacement Instruction Formats" filed on Mar. 28, 2003 and
assigned to IBM. The disclosure of the forgoing application is
incorporated herein by reference.
FIELD OF THE INVENTION
[0002] This invention relates to computer systems, and particularly
to a computer architecture having signed values wherein the sign is
embedded between magnitude value portions.
BACKGROUND
[0003] Trademarks: IBM.RTM. is a registered trademark of
International Business Machines Corporation, Armonk, N.Y., U.S.A.
S/390, Z900 and z990 and other product names may be registered
trademarks or product names of International Business Machines
Corporation or other companies.
[0004] Before our invention there existed in the IBM Z/Architecture
(and its predecessor architectures) the existence of instruction
formats having storage addressing in the form of base register plus
12 bit unsigned displacement or the form of base register plus
index register plus 12 bit unsigned displacement, as incorporated
in IBM's z900 mainframe servers. Generally, the computer
architecture of the z900 was described in the IBM Z/Architecture
Principles of Operation, Publication SA22-7832-00 (incorporated
herein by reference), where section 5-2 to 5-7 describes the
Instructions consisting of two major parts: an op code and the
designation of the operands that participate. The instruction
formats of these currently available machines are described
beginning at 5-3. It will be noted that the basic instruction
formats described at 5-4 and 5-5 include the RXE format described
in detail also in our prior U.S. Pat. No. 6,105,126, granted Aug.
15, 2000, and entitled "Address Bit Decoding for same Adder
Circuitry for RXE Instruction Format with SAME XBD location as RX
Format and Disjointed Extended Operation Code."
SUMMARY OF THE INVENTION
[0005] In accordance with our preferred embodiment of our invention
for use on both the prior IBM z900 Servers, but also on new
processors which we name the z990 Servers, as well as on other
computer systems which can emulate our new IBM Z/Architecture
comprising of the existing Z/Architecture instructions and
instruction formats and new instructions using several new long
displacement instruction formats that provide for a new storage
addressing that consists of either base register plus 20 bit signed
displacement or base register plus index register plus 20 bit
signed displacement. These new formats can be used to provide new
instructions or can modify the operation of a subset of existing
instructions that were created with only the prior 12 bit unsigned
displacements for calculation of the storage address. The
advantages achieved by the new computer architecture instruction
formats is that they provide for a long displacement facility which
can be achieved within an existing machine or a new machine which
implements the new Z/Architecture with our new instruction
formats.
[0006] It is therefore an object of the invention to execute a
machine instruction in a central processing unit by fetching a
signed displacement machine instruction for execution, the signed
displacement machine instruction defined for computer execution
according to a computer architecture, the signed displacement
machine instruction comprising an opcode field and an signed
displacement field having N contiguous bits consisting of a signed
displacement value, the signed displacement value consisting of a
magnitude and a sign S, the signed displacement value consisting of
N contiguous bit positions 1 through N wherein the magnitude
consists of a first value consisting of contiguous bit positions 1
through S-1 and a second value consisting of bit positions S+1
through N wherein bit position S is greater than 1 and less than N.
Then extracting a magnitude value from the signed displacement
value magnitude and extracting the sign S from the signed
displacement value whereby the extracted sign S and magnitude value
is used to perform a function defined by the opcode field.
[0007] It is another object of the invention to perform the
extracting step by concatenating the first value with the second
value to form the magnitude value the second value consists of
least significant bits of the magnitude value the first value
consists of most significant bits of the magnitude value.
[0008] It is yet another object of the invention to concatenate the
sign S with the most significant bit position of the magnitude
value to form a signed magnitude value, then using the signed
magnitude value in the using step to perform a function defined by
the opcode field, wherein the function.
[0009] It is still another object of the invention to obtain an
operand base address from a location specified by an operand base
address field of the signed displacement machine instruction and if
the sign S is negative, arithmetically subtracting the magnitude
value from the operand base address to determine an address of an
operand but if the sign S is positive, arithmetically adding the
magnitude value to the operand base address to determine the
address of the operand and finally, to perform the function defined
by the opcode field, wherein the function uses the operand at the
determined address.
[0010] It is another object of the invention to further fetch an
unsigned displacement machine instruction for execution, the
unsigned displacement machine instruction defined for computer
execution according to the computer architecture, the unsigned
displacement machine instruction comprising an opcode field and an
unsigned displacement field having S-1 contiguous bits consisting
of an unsigned displacement value, the unsigned displacement value
consisting of an unsigned magnitude consisting of contiguous bit
positions 1 through S-1, wherein bit positions 1 through S-1
consist of the same bit positions as bit positions 1 through S-1 of
the signed displacement machine instruction and extract an unsigned
magnitude value from the unsigned displacement value and to use the
unsigned magnitude value to perform a the function defined by the
opcode field.
DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 illustrates the existing Z/Architecture RXE
instruction format;
[0012] FIG. 2 illustrates the existing Z/Architecture RSE
instruction format;
[0013] FIG. 3 illustrates the new Z/Architecture RXY instruction
format;
[0014] FIG. 4 illustrates the new Z/Architecture RSY instruction
format;
[0015] FIG. 5 illustrates the new Z/Architecture SIY instruction
format; and
[0016] FIG. 6, shows the preferred embodiment of a computer memory
storage containing instructions in accordance with the preferred
embodiment and data, as well as the mechanism for fetching,
decoding and executing these instructions, either on a computer
system employing these architected instructions or as used in
emulation of our architected instructions.
[0017] Our detailed description explains the preferred embodiments
of our invention, together with advantages and features, by way of
example with reference to the drawings.
DETAILED DESCRIPTION OF THE INVENTION
[0018] In the current Z/Architecture there exist the RXE format as
described in U.S. Pat. No. 6,105,126 (incorporated fully by
reference) shown here and in that patent as FIG. 1, and also RSE,
shown here as FIG. 2, instruction formats. There are existing
instructions in the Z/Architecture which use the base register plus
12 unsigned displacement or base register plus index register plus
12 bit unsigned displacement to form the operand storage
address.
[0019] In accordance with our preferred embodiment the invention
creates three new formats RXY, FIG. 3, RSY, FIG. 4, and SIY, FIG.
5. These new formats are used to provide a 20 bit signed
displacement field that can be used to form the operand storage
address base register plus 20 bit signed displacement or base
register plus index register plus 20 bit signed displacement. This
new 20 bit signed displacement field can be used for support of new
instructions or can allow prior instructions that only had a 12 bit
unsigned displacement to now have access to a signed 20 bit signed
displacement. It is a feature of our invention that any software
code created under the prior instruction formats will operate as
they were originally defined, with a 12 bit unsigned displacement,
while especially, any new software code created under the new
instruction formats can operate with the new 20 bit signed
displacement (chosen as comprising signed long displacement bits
numbering, in the preferred embodiment 20). The new 20 bit signed
displacement is done as two parts that are adjacent to each other.
The two parts of the displacement value while being located in
adjacent fields in the instruction text are not sequentially
numbered bit ranges. The DL1 or DL2 field in the instruction
formats is the least significant 12 bits of the 20 bit signed
displacement and are in the same location in the RXY, RSY, and SIY
instruction formats as the 12 bit unsigned D2 field in the existing
RXE and RSE formats. The DH1 or DH2 field in the RXY, RSY, or SIY
instruction formats are defined as the 8 most significant bits of
the 20 bit signed displacement field and is located in an undefined
area of the RXE and RSE instruction formats. By reference to the
Figures it will be appreciated that D1 and D2 refers to the
displacement field for operand one and the displacement field for
operand two of an instruction while, as DL is an acronym for
"Displacement Low" while DH is an acronym for "Displacement High"
for which it will be appreciated that DL1 and DH1 will refer to the
displacement fields for operand one and DL2 and DH2 will refer to
the displacement fields for operand two.
[0020] In FIG. 6, #501 shows a computer memory storage containing
instructions and data. The long displacement instructions described
in this invention would initially stored in this computer. #502
shows a mechanism for fetching instructions from a computer memory
and may also contain local buffering of these instructions it has
fetched. Then the raw instructions are transferred to an
instruction decoder, #503, where it determines what type of
instruction has been fetched. #504, shows a mechanism for executing
instructions. This may include loading data into a register from
memory, #501, storing data back to memory from a register, or
performing some type of arithmetic or logical operation. This exact
type of operation to be performed has been previously determined by
the instruction decoder. The long displacement instructions
described in this invention would be executed here. If the long
displacement instructions are being executed natively on a computer
system, then this diagram is complete as described above. However,
if an instruction set architecture, containing long displacement
instructions, is being emulated on another computer, the above
process would be implemented in software on a host computer, #505.
In this case, the above stated mechanisms would typically be
implemented as one or more software subroutines within the emulator
software. In both cases an instruction is fetched, decoded and
executed.
[0021] More particularly, these architected instructions can be
used with a computer architecture with existing instruction formats
with a 12 bit unsigned displacement used to form the operand
storage address and also one having additional instruction formats
that provide a additional displacement bits, preferably 20 bits,
which comprise an extended signed displacement used to form the
operand storage address. These computer architected instructions
comprise computer software, stored in a computer storage medium,
for producing the code running of the processor utilizing the
computer software, and comprising the instruction code for use by a
compiler or emulator/interpreter which is stored in a computer
storage medium 501, and wherein the first part of the instruction
code comprises an operation code which specified the operation to
be performed and a second part which designates the operands for
that participate. The long displacement instructions permit
additional addresses to be directly addressed with the use of the
long displacement facility instruction.
[0022] In a commercial implementation of the long displacement
facility computer architected instruction format the instructions
are used by programmers, usually today "C" programmers. These
instruction formats stored in the storage medium may be executed
natively in a Z/Architecture IBM Server, or alternatively in
machines executing other architectures. They can be emulated in the
existing and in future IBM mainframe servers and on other machines
of IBM (e.g. pSeries Servers and xSeries Servers). They can be
executed in machines running Linux on a wide variety of machines
using hardware manufactured by IBM, Intel, AMD, Sun Microsystems
and others. Besides execution on that hardware under a
Z/Architecture, Linux can be used as well as machines which use
emulation by Hercules, UMX, FXI or Platform Solutions, where
generally execution is in an emulation mode. In emulation mode the
specific instruction being emulated is decoded, and a subroutine
built to implement the individual instruction, as in a "C"
subroutine or driver, or some other method of providing a driver
for the specific hardware as is within the skill of those in the
art after understanding the description of the preferred
embodiment. Various software and hardware emulation patents
including, but not limited to U.S. Pat. No. 5,551,013 for a
"Multiprocessor for hardware emulation" of Beausoleil et al., and
U.S. Pat. No. 6,009,261: Preprocessing of stored target routines
for emulating incompatible instructions on a target processor" of
Scalzi et al; and U.S. Pat. No. 5,574,873: Decoding guest
instruction to directly access emulation routines that emulate the
guest instructions, of Davidian et al; U.S. Pat. No. 6,308,255:
Symmetrical multiprocessing bus and chipset used for coprocessor
support allowing non-native code to run in a system, of Gorishek et
al; and U.S. Pat. No. 6,463,582: Dynamic optimizing object code
translator for architecture emulation and dynamic optimizing object
code translation method of Lethin et al; and U.S. Pat. No.
5,790,825: Method for emulating guest instructions on a host
computer through dynamic recompilation of host instructions of Eric
Traut; and many others, illustrate the a variety of known ways to
achieve emulation of an instruction format architected for a
different machine for a target machine available to those skilled
in the art, as well as those commercial software techniques used by
those referenced above.
[0023] In the preferred embodiment the existing instruction formats
form the operand storage address by the summing of the base
register and 12 bit unsigned displacement or the base register, the
index register, and the 12 bit unsigned displacement and the new
instruction formats form the operand storage address by the summing
of the base register and the 20 bit signed displacement or the base
register, the index register, and the 20 bit signed
displacement.
[0024] As illustrated by FIG. 6, these instructions are executed in
hardware by a processor or by emulation of said instruction set by
software executing on a computer having a different native
instruction set.
[0025] In accordance with the computer architecture of the
preferred embodiment the displacement field is defined as being in
two parts, the least significant part being 12 bits called the DL,
DL1 for operand 1 or DL2 for operand 2, and the most significant
part being 8 bits called the DH, DH1 for operand 1 or DH2 for
operand 2.
[0026] Furthermore, the preferred computer architecture has an
instruction format such that the opcode is in bit positions 0
through 7 and 40 through 47, a target register called R1 in bit
positions 8 through 11, an index register called X2 in bit
positions 12 through 15, a base register called B2 in bit positions
16 through 19, a displacement composed of two parts with the first
part called DL2 in bit positions 20 through 31 and the second part
called DH2 in bit positions 32 through 39.
[0027] This computer architecture has an instruction format such
that the opcode is in bit positions 0 through 7 and 40 through 47,
a target register called R1 in bit positions 8 through 11, an
source register called R3 in bit positions 12 through 15, a base
register called B2 in bit positions 16 through 19, a displacement
composed of two parts with the first part called DL2 in bit
positions 20 through 31 and the second part called DH2 in bit
positions 32 through 39.
[0028] Furthermore, our computer architecture instructions having a
long displacement facility has an instruction format such that the
opcode is in bit positions 0 through 7 and 40 through 47, a target
register called R1 in bit positions 8 through 11, a mask value
called M3 in bit positions 12 through 15, a base register called B2
in bit positions 16 through 19, a displacement composed of two
parts with the first part called DL2 in bit positions 20 through 31
and the second part called DH2 in bit positions 32 through 39.
[0029] AS illustrated, our preferred computer architecture with its
long displacement facility has an instruction format such that the
opcode is in bit positions 0 through 7 and 40 through 47, an
immediate value called 12 in bit positions 8 through 15, a base
register called B2 in bit positions 16 through 19, a displacement
composed of two parts with the first part called DL1 in bit
positions 20 through 31 and the second part called DH1 in bit
positions 32 through 39.
[0030] Our long displacement facility computer architecture
operates effectively when using new instructions which are created
that only use the instruction format with the new 20 bit unsigned
displacement.
[0031] A specific embodiment of our computer architecture utilizes
existing instructions which have the instruction formats that only
have the 12 bit unsigned displacement and are now defined to be in
the new instruction formats to have either the existing 12 bit
unsigned displacement value when the high order 8 bits of the
displacement, field DH, are all zero, or a 20 bit signed value when
the high order 8 bits of the displacement, field DH, is
non-zero.
[0032] While the preferred embodiment to the invention has been
described, it will be understood that those skilled in the art,
both now and in the future, may make various improvements and
enhancements which fall within the scope of the claims which
follow. These claims should be construed to maintain the proper
protection for the invention first described.
* * * * *