U.S. patent application number 11/325631 was filed with the patent office on 2006-08-31 for method and system for fabricating and cleaning free-standing nanostructures.
Invention is credited to Audrey Dupont, Ronald Hoyer.
Application Number | 20060194404 11/325631 |
Document ID | / |
Family ID | 35966215 |
Filed Date | 2006-08-31 |
United States Patent
Application |
20060194404 |
Kind Code |
A1 |
Dupont; Audrey ; et
al. |
August 31, 2006 |
Method and system for fabricating and cleaning free-standing
nanostructures
Abstract
Systems and methods include introducing a semiconductor wafer
into a process chamber. An etching chemistry is injected into the
process chamber to etch a patterned layer and to release
free-standing nanostructures on the semiconductor wafer. The
etching chemistry includes a supercritical or liquid carbon dioxide
fluid and an etching solution. The semiconductor wafer is rinsed by
flooding a supercritical or liquid carbon dioxide fluid into the
process chamber. The semiconductor wafer is dried by venting out
supercritical or liquid carbon dioxide fluid from the process
chamber.
Inventors: |
Dupont; Audrey; (Dresden,
DE) ; Hoyer; Ronald; (Dresden, DE) |
Correspondence
Address: |
EDELL, SHAPIRO & FINNAN, LLC
1901 RESEARCH BOULEVARD
SUITE 400
ROCKVILLE
MD
20850
US
|
Family ID: |
35966215 |
Appl. No.: |
11/325631 |
Filed: |
January 5, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11066320 |
Feb 25, 2005 |
7008853 |
|
|
11325631 |
Jan 5, 2006 |
|
|
|
Current U.S.
Class: |
438/397 ;
257/E21.251 |
Current CPC
Class: |
H01L 27/10852 20130101;
H01L 21/31111 20130101; H01L 28/91 20130101 |
Class at
Publication: |
438/397 |
International
Class: |
H01L 21/20 20060101
H01L021/20 |
Claims
1. A method for fabricating and cleaning free-standing
nanostructures, comprising the steps of: providing a semiconductor
wafer comprising a substrate and a patterned layer above the
substrate, the patterned layer comprising a plurality of openings
extending from an upper surface of the patterned layer to an upper
surface of the substrate, and structural elements being arranged
within the openings; providing a process chamber, the process
chamber being configured to receive the semiconductor wafer;
introducing the semiconductor wafer into the process chamber;
injecting an etching chemistry into the process chamber to etch the
patterned layer and to release the structural elements as
free-standing nanostructures on the semiconductor wafer, the
etching chemistry comprising a carbon dioxide fluid and an etching
solution; injecting a cleaning chemistry into the process chamber
in order to remove particles from the surface of structural
elements being free-standing nanostructures on the semiconductor
wafer, the cleaning chemistry comprising a supercritical
carbon-dioxide fluid and cleaning solution; rinsing the
semiconductor wafer by flooding a carbon dioxide fluid into the
process chamber; and drying the semiconductor wafer by injecting a
supercritical carbon dioxide fluid into the process chamber and by
venting out the supercritical carbon dioxide fluid from the process
chamber.
2. The method of claim 1, wherein the carbon dioxide fluid is in a
liquid state in the etching chemistry injected into the process
chamber.
3. The method of claim 1, wherein the carbon dioxide fluid is in a
supercritical state in the etching chemistry injected into the
process chamber.
4. The method of claim 3, wherein the injection of the
supercritical carbon dioxide fluid containing etching chemistry
into the process chamber is performed at a single transparent phase
of the supercritical carbon dioxide fluid.
5. The method of claim 4, wherein the step of injecting the etching
chemistry into the process chamber is performed at a pressure of
the supercritical carbon dioxide fluid within the process chamber
being above 1000 psi.
6. The method of claim 5, wherein the step of injecting the etching
chemistry into the process chamber is performed at a temperature of
the supercritical carbon dioxide fluid within the process chamber
being above 40.degree. C.
7. The method of claim 1, wherein the carbon dioxide fluid is in a
liquid state during the rinsing of the semiconductor wafer.
8. The method of claim 1, wherein the carbon dioxide fluid is in a
supercritical state during the rinsing of the semiconductor
wafer.
9. The method of claim 8, wherein the rinsing of the semiconductor
wafer is performed at constant pressure and constant temperature of
the supercritical carbon dioxide fluid within the process
chamber.
10. The method of claim 1, wherein the step of drying the
semiconductor wafer further includes releasing the pressure created
by the venting supercritical carbon dioxide fluid within the
process chamber.
11. The method of claim 1, wherein, prior to the step of drying the
semiconductor wafer, the method further comprises: flushing the
free-standing nanostructures with a supercritical carbon dioxide
fluid at flow ranging from about 0.1 L/min to about 5 L/min.
12. The method of claim 1, wherein adjacent openings of the
plurality of openings of the semiconductor wafer are spaced at a
distance of about 200 nm or less.
13. The method of claim 12, wherein the patterned layer of the
semiconductor wafer has a thickness in the range of about 1 .mu.m
to about 20 .mu.m.
14. The method of claim 13, wherein openings of the plurality of
openings of the semiconductor wafer have a width of about 200 nm or
less.
15. The method of claim 1, wherein the cleaning solution of the
cleaning chemistry changes the zeta-potential of the surface of the
free-standing nanostructures to promote the separation of the
particles from the surface of the free-standing nanostructures.
16. The method of claim 1, wherein the cleaning solution of the
cleaning chemistry etches the surface of the free-standing
nanostructures up to a thickness between 5 .ANG. and 100 .ANG. so
as to promote the separation of the particles from the surface of
the free-standing nanostructures.
17. The method of claim 16, wherein the cleaning solution of the
cleaning chemistry comprises an etchant being selected from the
group consisting of HF, H.sub.2SO.sub.4, HCl, H.sub.2O.sub.2, and
NH.sub.3.
18. The method of claim 16, wherein the cleaning solution comprises
one of an anionic surfactant and a non-ionic surfactant that allows
for etch residues and particles to be transported away from the
semiconductor in micellar structures.
19. The method of claim 18, wherein the anionic surfactant
comprises one of a sodium dioctyl sulfosuccinate and a sodium
dioctyl sulfosuccinate derivative.
20. The method of claim 18, wherein the non-ionic surfactant is
selected from the group consisting of ethylene oxide, octylphenol
ethoxylates, alkyl polyglucosides, acetylenic diols, alkoxylated
acetylenic diols, derivatives of each, and combinations
thereof.
21. The method of claim 15, further comprising: applying a
mechanical force to the particles in order to fully remove the
particle from the surface of the free-standing nanostructures.
22. The method of claim 21, wherein the mechanical force comprises
application of megasonics.
23. The method of claim 21, wherein the mechanical force comprises
periodical increasing and decreasing of the chamber pressure.
24. The method of claim 21, wherein the mechanical force comprises
agitation of the cleaning chemistry.
25. A method for cleaning free-standing nanostructures, comprising
the steps of: providing a semiconductor wafer having a substrate
and a patterned layer above the substrate, the patterned layer
comprising structural elements as free-standing nanostructures;
providing a process chamber, the process chamber being configured
to receive the semiconductor wafer; introducing the semiconductor
wafer into the process chamber; injecting a cleaning chemistry into
the process chamber in order to remove particles from the surface
of structural elements being free-standing nanostructures on the
semiconductor wafer, the cleaning chemistry comprising a
supercritical carbon-dioxide fluid and a cleaning solution; rinsing
the semiconductor wafer by flooding a supercritical carbon-dioxide
fluid into the process chamber; and drying the semiconductor wafer
by venting out the supercritical carbon-dioxide fluid from the
process chamber.
26. The method of claim 25, wherein at least part of the
free-standing nanostructures have a height-to-width-ratio of 20 or
larger.
27. The method of claim 26, wherein the free-standing
nanostructures are aligned with respect to each other and the
substrate to facilitate forming of bottom electrodes of a stacked
capacitor memory cell.
28. The method of claim 26, wherein the free-standing
nanostructures are aligned with respect to each other and the
substrate to facilitate forming of active transistors of a
surrounding gate transistor.
29. The method of claim 25, wherein the cleaning solution of the
cleaning chemistry changes the zeta-potential of the surface of the
free-standing nanostructures to promote the separation of the
particles from the surface of the free-standing nanostructures.
30. The method of claim 25, wherein the cleaning solution etches
the surface of the free-standing nanostructures up to a thickness
between 5 .ANG. and 100 .ANG. so as to promote the separation of
the particles from the surface of the free-standing
nanostructures.
31. The method of claim 29 further comprising: applying a
mechanical force to the particles in order to fully remove the
particles from the surface of the free-standing nanostructures.
32. The method of claim 31, wherein the mechanical force comprises
application of megasonics.
33. The method of claim 31, wherein the mechanical force comprises
periodical increasing and decreasing of the chamber pressure.
34. The method of claim 31, wherein the mechanical force comprises
agitation of the cleaning chemistry.
35. A system for fabricating and cleaning free-standing
nanostructures, comprising: a semiconductor wafer comprising a
substrate and a patterned layer disposed above the substrate, the
patterned layer comprising a plurality of openings extending from
the surface of the patterned layer to the surface of the substrate
and structural elements being arranged within the openings; a
process chamber, the process chamber being configured to receive
the semiconductor wafer; means for introducing the semiconductor
wafer into the process chamber; means for injecting an etching
chemistry into the process chamber to etch the patterned layer and
to release the structural elements as free-standing nanostructures
on the semiconductor wafer, the etching chemistry comprising a
liquid or supercritical carbon dioxide fluid and an etching
solution; means for injecting a cleaning chemistry into the process
chamber in order to remove particles from the surface of structural
elements being free-standing nanostructures on the semiconductor
wafer, the cleaning chemistry comprising a supercritical
carbon-dioxide fluid and cleaning solution; means for rinsing the
semiconductor wafer by flooding supercritical carbon dioxide fluid
into the process chamber; and means for drying the semiconductor
wafer by venting out supercritical carbon dioxide fluid from the
process chamber.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This is a continuation-in-part application of U.S.
application Ser. No. 11/066,320, entitled "Method and System for
Fabricating Free-Standing Nanostructures" and filed Feb. 25, 2005
which is incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
[0002] The invention relates to systems and corresponding methods
for fabricating and cleaning free-standing nanostructures on a
semiconductor wafer. In particular, the invention relates to the
field of etching, cleaning, and drying a semiconductor wafer with a
patterned layer to fabricate bottom electrode structures on a
semiconductor wafer and to cleaning and/or drying the bottom
electrode structures.
BACKGROUND
[0003] One goal in the manufacture of integrated circuits is to
continuously decrease feature sizes of the fabricated components.
For certain components, like capacitors, shrinking adversely
affects the properties of the component. In order to achieve a
desired value of capacitance, it is therefore necessary to keep the
surface area of the capacitor above a threshold value. This is
particularly important for dynamic random access memory cells
(DRAM) which call for high integration densities.
[0004] As the surface area for a single memory cell decreases, the
capacity of the storage capacitor also decreases. For proper
operation of the memory cell, a certain minimum capacity (typically
on the order of about 30 femto farad) is mandatory for the storage
capacitor. If the capacity of the storage capacitor is too small,
the charge stored in the storage capacitor is not sufficient to
produce a detectable signal. In such a case, the information stored
in the memory cell is lost and the memory cell is not operating in
a desired manner.
[0005] Several methods have been developed to overcome the problems
associated with shrinking feature sizes by integrating capacitors
of DRAM cells in a three dimensional manner. For example, one
method introduces deep trench capacitors which are formed in the
substrate of a semiconductor wafer to maintain a large capacitor
area with a high capacity while using only a small amount of the
surface of the substrate. The selection or access transistor is
usually formed on the planar surface of the substrate in this
method.
[0006] In another example, stacked capacitors are used which are
formed on top of a planar surface on the substrate. The selection
transistors are formed below the planar surface in this method. The
stacked capacitor includes a first electrode and a second electrode
with a dielectric layer between the two electrodes. The first
electrode (also called bottom electrode) is usually formed as a
cylindrical structure on the surface of the substrate by lining
trenches of a patterned sacrificial mold layer with the electrode
material. Afterwards, the bottom electrodes are released by etching
the sacrificial mold layer. Subsequently, the surface of the bottom
electrodes are cleaned to be prepared for further processing,
including deposition of the dielectric layer and the second or top
electrode.
[0007] However, with the ever decreasing feature sizes of
structures, etching and/or cleaning steps become increasingly
difficult. Etching and/or cleaning steps are usually performed by
wet processing. Standard wet processing, e.g. rinsing the wafer
with ultra pure de-ionized water for cleaning purposes, introduces
capillary forces between neighboring structures (e.g., between
adjacent bottom electrodes). With reduced feature sizes, this may
lead to adhesion of neighboring structures. This is described in
Legtenberg et al., "Stiction of surface macromachined structures
after rinsing and drying: model and investigation of adhesion
mechanisms", Sensors and Actuators A, 43 (1994), pages 230-238.
Adhesion of neighboring structures is mediated by the cleaning
liquid, usually referred to as "stiction".
[0008] For semiconductor processing, stiction is primarily
important during drying steps which usually follow the etching and
cleaning steps in semiconductor wafer processing. There, capillary
forces induced by the liquid lead to adhesion of adjacent bottom
electrodes. The adjacent bottom electrodes remain stuck to each
other even after being completely dried, particularly when the
adhesion force between the contacting adjacent bottom electrodes is
larger than the elastic restoring force of the deformed bottom
electrodes.
[0009] Exposing wafers to an air-liquid interface during transfer
between etching, cleaning and drying process modules is detrimental
to obtaining stiction free process performance. Failing to achieve
stiction free process performance ultimately results in a low yield
of the produced circuits. One potential solution to this problem is
to completely avoid wet processing and perform etching steps using
gas phase processing, e.g. in a hydrogen fluoride vapor. However,
such gas phase processing leads to etching residues and to silicon
surface termination states which in turn hinders further
processing.
SUMMARY OF THE INVENTION
[0010] It is an object of the invention to provide a system and
corresponding method for fabricating free-standing nanostructures
on a semiconductor wafer which overcomes the above mentioned
problems associated with stiction.
[0011] It is another object of the invention to provide such a
system and method that includes etching, cleaning, and drying of a
semiconductor wafer with a patterned hard mask layer for
fabrication of bottom electrode structures.
[0012] The aforesaid objects are achieved individually and in
combination in accordance with the present invention, and it is not
intended that the present invention be construed as requiring two
or more of the objects to be combined unless expressly required by
the claims attached hereto.
[0013] In accordance with the invention, a method for fabricating
and cleaning free-standing nanostructures includes providing a
semiconductor wafer comprising a substrate and a patterned layer
above the substrate, the patterned layer comprising a plurality of
openings extending from an upper surface of the patterned layer to
an upper surface of the substrate, and structural elements being
arranged within the openings, providing a process chamber, the
process chamber being configured to receive the semiconductor
wafer, introducing the semiconductor wafer into the process
chamber, injecting an etching chemistry into the process chamber to
etch the patterned layer and to release the structural elements as
free-standing nanostructures on the semiconductor wafer, the
etching chemistry comprising a carbon dioxide fluid and an etching
solution, injecting a cleaning chemistry into the process chamber
in order to remove particles from the surface of structural
elements being free-standing nanostructures on the semiconductor
wafer, the cleaning chemistry comprising a supercritical
carbon-dioxide fluid and cleaning solution, rinsing the
semiconductor wafer by flooding a carbon dioxide fluid into the
process chamber, and drying the semiconductor wafer by injecting a
supercritical carbon dioxide fluid into the process chamber and by
venting out the supercritical carbon dioxide fluid from the process
chamber.
[0014] Accordingly, stiction free processing is achieved by
employing unique properties of carbon dioxide in the supercritical
or liquid state. The supercritical state is a high density phase
characterized by a low viscosity and a zero surface tension, thus
enabling better solubility and efficiency of the etching chemistry.
On the other hand, properties similar to a gas phase presents high
diffusion capabilities, allowing for easy solvent removal and
greater drying efficiency. Another feature of the invention is that
all process steps are performed in the same process chamber. This
ensures that no air-liquid interfaces during transfer between
etching, cleaning and drying process modules can occur.
Accordingly, capillary forces are eliminated. This is achieved by
employing carbon dioxide in its various states, i.e. supercritical,
liquid and gas. Furthermore, a cleaning step is applied which
removes residues on the surface of the free-standing
nanostructures. The cleaning step is performed in the same process
chamber thus utilizing a supercritical process sequence which
allows for adding a cleaning solution. As a result, contaminants on
the surface of the free-standing nanostructures are largely
eliminated.
[0015] In accordance with another embodiment of the invention, a
method for fabricating and cleaning free-standing nanostructures
includes providing a semiconductor wafer having a substrate and a
patterned layer above the substrate, the patterned layer comprising
structural elements as free-standing nanostructures, providing a
process chamber, the process chamber being configured to receive
the semiconductor wafer, introducing the semiconductor wafer into
the process chamber, injecting a cleaning chemistry into the
process chamber in order to remove particles from the surface of
structural elements being free-standing nanostructures on the
semiconductor wafer, the cleaning chemistry comprising a
supercritical carbon-dioxide fluid and a cleaning solution, rinsing
the semiconductor wafer by flooding a supercritical carbon-dioxide
fluid into the process chamber, and drying the semiconductor wafer
by venting out the supercritical carbon-dioxide fluid from the
process chamber.
[0016] In accordance with another embodiment of the invention, a
system for fabricating and cleaning free-standing nanostructures
comprises: a semiconductor wafer comprising a substrate and a
patterned layer disposed above the substrate, the patterned layer
comprising a plurality of openings extending from the surface of
the patterned layer to the surface of the substrate and structural
elements being arranged within the openings; a process chamber, the
process chamber being configured to receive the semiconductor
wafer; means for introducing the semiconductor wafer into the
process chamber; means for injecting an etching chemistry into the
process chamber to etch the patterned layer and to release the
structural elements as free-standing nanostructures on the
semiconductor wafer, the etching chemistry comprising a liquid or
supercritical carbon dioxide fluid and an etching solution; means
for injecting a cleaning chemistry into the process chamber in
order to remove particles from the surface of structural elements
being free-standing nanostructures on the semiconductor wafer, the
cleaning chemistry comprising a supercritical carbon-dioxide fluid
and cleaning solution; means for rinsing the semiconductor wafer by
flooding supercritical carbon dioxide fluid into the process
chamber; and means for drying the semiconductor wafer by venting
out supercritical carbon dioxide fluid from the process
chamber.
[0017] The above and still further objects, features and advantages
of the present invention will become apparent upon consideration of
the following definitions, descriptions and descriptive figures of
specific embodiments thereof wherein like reference numerals in the
various figures are utilized to designate like components. While
these descriptions go into specific details of the invention, it
should be understood that variations may and do exist and would be
apparent to those skilled in the art based on the descriptions
herein.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 depicts a side view in partial cross-section of a
semiconductor wafer including a plurality of stacked capacitor
DRAM-cells.
[0019] FIG. 2 depicts a side view in partial cross-section of a
semiconductor wafer including a plurality of surrounding gate
transistors.
[0020] FIGS. 3A-3D depict a side view in partial cross-section of
parts of a stacked capacitor DRAM-cell formed in accordance with an
exemplary method of the invention.
[0021] FIGS. 4A-4B depict a side view in partial cross-section of
free-standing nano-structures formed in accordance with another
exemplary method of the invention.
[0022] FIG. 5 depicts a side view in partial cross-section of a
wafer drying, rinsing and cleaning system in accordance with the
invention.
[0023] FIGS. 6A-6B are images showing a plurality of bottom
electrodes of stacked capacitor DRAM-cells formed according to
conventional wet etching techniques.
[0024] FIG. 7 is an image showing parts of a plurality of
surrounding gate transistors formed according to conventional wet
etching techniques.
[0025] FIG. 8 is a flow chart of method steps for a further
embodiment of the invention.
[0026] FIG. 9 is a flow chart of method steps for a further
embodiment of the invention.
DETAILED DESCRIPTION
[0027] Exemplary embodiments of methods and systems according to
the invention are discussed in detail below. It is appreciated,
however, that the present invention provides many applicable
inventive concepts that can be embodied in a wide variety of
specific contexts. The specific embodiments discussed are merely
illustrative of specific ways to apply the method and the system of
the invention, and do not limit the scope of the invention.
[0028] In particular, the following embodiments are described in
the context of fabricating bottom electrode structures for stacked
capacitor DRAM cells and surrounding gate transistors for a
vertical cell technology. In both technologies, free-standing
nanostructures are formed as protruding elements on the surface of
a semiconductor wafer having, in accordance with present
technologies, a height to width ratio in excess of 20. It should be
noted, however, that the inventive methods and systems can be
applied for other high aspect ratio nanostructures as well.
[0029] Referring to FIG. 1, stacked capacitor DRAM-cells are shown
in a side view. It should be appreciated that FIG. 1 merely serves
as an illustration of fabricating stacked capacitor DRAM-cells, and
the individual components shown in FIG. 1 are not true to
scale.
[0030] In FIG. 1, a semiconductor wafer 2 is shown including a
substrate 4 of semi-conductive material (e.g., silicon). The
semiconductor wafer 2 is used for fabricating a plurality of
stacked capacitor DRAM cells 6. Each DRAM cell 6 includes a
selection transistor 10 and a stacked capacitor 12. The stacked
capacitor 12 is located above the substrate surface 8.
[0031] The transistor 10 is located in the substrate 4. The
transistor 10 is formed by a first junction 14 and a second
junction 16. Between the first junction 14 and the second junction
16 a gate 20 is disposed above a gate dielectric layer 18. The gate
20 can include a stack of several layers (e.g., silicon and
tungsten). The stack of several layers reduces the resistance of
the gate 20. The gate 20 also serves as a word line for addressing
a specific DRAM cell 6 of the plurality of DRAM cells during
operation.
[0032] The first junction 14 is connected to a bit-line contact 22.
The bit-line contact 22 is disposed above the first junction 14.
The bit-line contact 22 is connected to a bit-line 24 which is
located above the bit-line contact 22. The bit-line 24 serves as a
write or read line during operation.
[0033] The second junction 16 is connected to a contact plug 26.
The contact plug 26 is disposed above the second junction 16. The
contact plug 26 serves as a connection to a bottom electrode 28 of
the capacitor 12. The bottom electrode 28 of the capacitor 12 is
located above the substrate surface 8.
[0034] In FIG. 1, the bottom electrodes 28 are shown in a cross
sectional side view. For the three dimensional shape of the bottom
electrode 28, many different geometries can be used including
cylindrical, elliptical or rectangular.
[0035] As shown in FIG. 1, the bottom electrode 28 is formed with
vertical side walls above the contact plug 26. However,
non-vertical side walls or side walls being laterally recessed are
also conceivable.
[0036] The bottom electrode 28 of the capacitor 12 is covered by a
dielectric layer 30 which serves as the dielectric of capacitor 12.
Above the dielectric layer 30 a top electrode 32 is disposed. The
top electrode 32 of the capacitor 12 is usually common to all DRAM
cells 6 thus providing a connection between adjacent DRAM cells
6.
[0037] To a person skilled in the art, it is known that other
elements might be necessary to fabricate working DRAM cells 6. For
example, an insulation between adjacent transistors 10 might be
necessary to avoid electrical shorts to adjacent junction regions.
In addition, a barrier layer between the contact plug 26 and the
bottom electrode 28 can be provided, if necessary, to eliminate
diffusion of different materials.
[0038] Furthermore, an isolation material can be disposed around
the contact plugs 26 to avoid shorts to adjacent DRAM cells 6. It
is also possible to dispose the bit-line 24 on top of the top
electrode 32 of the capacitor 12 by using a modified bit-line
contact 22.
[0039] Referring now to FIG. 2, a second semiconductor wafer 2 is
shown including a substrate 4 of semi-conductive material (e.g.,
silicon). The semiconductor wafer 2 is used for fabricating a
plurality of surrounding gate transistors 10.
[0040] Each transistor 10 is located on pillars 21 formed on the
substrate 4, where the transistor is formed by a first junction 14
on the lower side of the pillar 21 and a second junction 16 on the
top side of the pillar 21. A gate dielectric layer 18 and a gate 20
are disposed on the side walls of the pillar 21 between the first
junction 14 and the second junction 16.
[0041] In an exemplary method of the invention for forming DRAM
cells 6 of FIG. 1, a semiconductor wafer 2 is first provided as
shown in FIG. 3A. The semiconductor wafer 2 has the substrate 4,
with transistors 10 in the substrate (not shown) that have been
formed for each DRAM cell 6.
[0042] In FIG. 3A, contact plugs 26 are shown on the surface 8 of
the substrate 4. As described above, the contact plugs 26 are used
to contact the bottom electrodes with the junction regions of the
transistors. The contact plugs 26 usually have a low resistance and
are made of, e.g., arsenic doped amorphous silicon. As an example,
in a technology providing 70 nm minimal feature size, adjacent
contact plugs 26 are spaced from each other at a distance ranging
from 50 nm to 200 nm.
[0043] On the surface 8 of substrate 4, a hard mask 40 as is
deposited a mold layer. The hard mask 40 may be composed of, e.g.
silicon oxide. The hard mask 40 serves later as a mold for the
bottom electrode 28 of the stacked capacitor DRAM cell 6.
Accordingly, the thickness 41 of the hard mask directly affects the
height of the bottom electrode 28 to be formed and, as a
consequence, the capacitance of stacked capacitor 12. Accordingly,
the hard mask 40 must have a certain thickness which can be about 2
.mu.m, e.g., for the 70 nm technology. However, other values for
the thickness 41 might also be used, e.g., thicknesses in the range
of 1 .mu.m to 20 .mu.m.
[0044] After the hard mask 40 has been deposited, a plurality of
openings or trenches 48 are formed in the mask layer 40, as shown
in FIG. 3B. A photo lithographic patterned resist can be applied,
e.g., to define the regions of the trenches 48. Each trench 48 is
arranged above a respective contact plug 26, as shown in FIG. 3B.
The trenches 48 are formed using a reactive ion etching step.
[0045] During the etching step, material of the mask layer 40 is
removed, thus forming the trench 48 from the top surface of the
contact plugs 26. As a result, the bottom of the trenches 48 are
formed by the contact plugs 26 while the side walls 49 of the
trench are formed within hard mask 40. Etching of trenches 48
preferably leads to side walls 49 which have a width in the range
of 50 nm to 200 nm as measured at the center of the trench 48.
[0046] Subsequently, a conductive layer 50 is conformably deposited
on the semiconductor wafer 2. The conductive layer 50 covers the
top side of the hard mask 40, the trench side walls 49, and the
bottom part of the trench 48, (including the contact plugs 26). A
suitable material for forming the conductive layer 50 by deposition
can be, e.g., doped amorphous silicon. The conductive layer 50
serves later as the bottom electrode 28 of the stacked capacitor 12
of DRAM cell 6 once the hard mask 40 has been removed and the
bottom electrodes are released. Therefore, the thickness of the
conductive layer 50 affects the stability of the free-standing
bottom electrodes 28.
[0047] In the next process step, a portion of the conductive layer
50 is removed from the surface of the hard mask 40, as shown in
FIG. 3C. This portion of the conductive layer 50 can be removed,
e.g., by etching using a plasma etcher. Alternatively, the trenches
48 can be filled with a fill material, followed by removing the
portion of the conductive layer 50 from the top surface of the hard
mask 40 by chemical mechanical polishing, and then removing the
fill material from within the trenches 48. According to these
process steps, the fill material protects the inner sides of the
trenches 48 from residues which could be a problem during later
process steps (e.g., deposition of the dielectric layer 30).
[0048] Referring to FIG. 3D, the next process step includes
removing the hard mask layer 40 in order to release the remaining
part of conductive layer 50 as free-standing nanostructures. The
free-standing nanostructures form bottom electrodes of a stacked
capacitor DRAM-cell 6, as described above and depicted in FIG.
1.
[0049] In FIGS. 4A and 4B, another process sequence of fabricating
free-standing nanostructures in accordance with the invention is
shown. Referring to FIG. 4A, the surface 8 of semiconductor wafer 2
is covered with a patterned resist layer or any other suitable hard
mask layer which has been structured by, e.g., a photo lithographic
process step. Referring to FIG. 4B, the next process step includes
releasing free-standing nanostructures 52 by etching. For example,
the free-standing nanostructures 52 of FIG. 4B are used as silicon
pillars for surrounding gate transistors, such as the gate
transistors described above and depicted in FIG. 2.
[0050] According to an embodiment of the invention, both releasing
of the free-standing pillars and the bottom electrodes, as
described in above methods and depicted in FIGS. 3A-3D and 4A-B,
are performed by an etching step. In a first exemplary embodiment,
the etching step employs an etching chemistry with a carbon dioxide
fluid being in the liquid phase and an etching solution. The carbon
dioxide fluid acts as a carrier for an etching solution which is
chosen with respect to the material to be removed during the
etching step. Referring to the embodiment shown in FIG. 3C, the
mold layer can be composed of silicon-dioxide, such that a fluorine
based etching chemistry (e.g., a formulation of a hydrofluoric
acid) can be used to etch the mold layer.
[0051] In addition, the etching chemistry is a mixture of carbon
dioxide, the etching solution and a co-solvent. For the co-solvent,
an alcohol/de-ionized water-mixture can be chosen, but alcohol,
alkane, ketone, amine or fluorine containing mixtures can be used
as well. Suitable substances are specified below.
[0052] Furthermore, a surfactant can be incorporated in the etching
chemistry in order to enhance water incorporation. The surfactant
should be compatible with the carbon dioxide fluid. Again, suitable
substances are specified below.
[0053] In a second exemplary embodiment, the process steps to
release the free-standing structures are performed by an etching
step mediated by a supercritical carbon dioxide fluid. In general,
a supercritical fluid are compounds above the so-called critical
point in the pressure/temperature phase diagram at a certain
critical temperature and critical pressure. The supercritical state
is often called the fourth state of matter. Supercritical fluids
exhibit properties of both liquids and fluids. For example,
transport properties like viscosity are similar to gases while
solvating properties like density are similar to those of
liquids.
[0054] According to an embodiment of the invention, a system is
provided, as shown in FIG. 5, that includes a process chamber 60.
The process chamber 60 is configured (e.g., suitably dimensioned)
to accommodate the semiconductor wafer 2. As shown in FIG. 5, the
process chamber 60 is connected to a reservoir 62 capable of
delivering carbon dioxide in the supercritical phase. In addition,
the system shown in FIG. 5 allows for adding extra substances with
controlled concentrations, such as etching agents and/or
co-solvents, as described below. Furthermore, the process chamber
60 can be pressurized and is operated with a controlled
temperature. This is achieved by a control unit 64, which is
schematically connected to reservoir 62 and process chamber 60.
[0055] For the supercritical fluid system shown in FIG. 5 many
commercially available systems can be used. As an example, TELSSI,
Inc. and SC Fluids Inc. provide supercritical fluid tools. Tools
from other vendors might be used as well.
[0056] Before processing is started, the semiconductor wafer 2 is
introduced into the process chamber 60. In the next step, an
etching chemistry is injected into the process chamber 60. The
etching chemistry is used to etch the hard mask layer 40 and to
release the structural elements 52 as free-standing nanostructures
on the semiconductor wafer 2. The etching chemistry includes the
supercritical or liquid carbon dioxide fluid and an etching
solution. The etching solution is chosen with respect to the
material to be removed during the etching step. According to the
embodiment shown in FIG. 3C, the hard mask layer 40 or mold layer
is composed of silicon-dioxide. Accordingly, a fluorine based
etching chemistry might be used.
[0057] The etching chemistry can be a formulation of a hydrofluoric
acid in mixture of carbon dioxide and a co-solvent. Preferably, the
hydrofluoric acid is added to the etching chemistry on the level of
a few micro-liter per liter of the etching chemistry.
[0058] For the co-solvent, an alcohol/de-ionized water-mixture can
be chosen, but alcohol, alkane (e.g., hexane), ketone (e.g.,
acetone), amine and/or fluorine containing mixtures can be used as
well. Suitable alcohol substances include methanol, ethanol,
propanol, iso-propanol, butanol and/or pentanol. Suitable amine
substances include n-methylpyrrolidone, di-glycol amine,
di-isopropyl amine and/or tri-isopropyl amine. Suitable fluorine
containing substances include ammonium fluoride and/or 1,1,1-fluoro
methane.
[0059] In addition, one or more surfactants can be incorporated in
the etching chemistry in order to enhance water incorporation. The
surfactant should be compatible with the supercritical carbon
dioxide fluid. For example, an anionic surfactant such as sodium
dioctyl sulfosuccinate and its derivatives (e.g., AEROSOL-OT and
its derivatives, available from Cytec Industries, West Paterson,
NJ, www.cytec.com) and/or a nonionic surfactant can be used.
Suitable non-ionic surfactants include ethylene oxide; octylphenol
ethoxylates, alkyl polyglucosides, and derivatives of each (e.g.,
TRITON series of nonionic surfactants, available from Dow Chemical,
Midland, Mich., www.dow.com); and/or acetylenic diols, alkoxylated
acetylenic diols, and derivatives of each (e.g., SURFYNOL and DYNOL
surfactants available from Air Products and Chemicals, Allentown,
Pa., www.airproducts.com).
[0060] The etching chemistry containing the supercritical carbon
dioxide fluid and the etching solution is injected at a temperature
and pressure above the critical point of carbon dioxide, which is
located above about 34.degree. C. and about 1050 psi in the phase
diagram.
[0061] Preferably, the etching chemistry is injected into the
process chamber 60 at a single transparent phase in a temperature
and pressure range selected between 50.degree. C. and 100.degree.
C. and at about 1100 psi. In this temperature and pressure range,
the density of the supercritical carbon dioxide fluid is in the
range between 0.4 and 0.8 g/mL (g/mL=gram/milliliter). The
supercritical state is further characterized by a low viscosity and
negligible zero surface tension.
[0062] When injecting the etching chemistry in the process chamber,
the semiconductor wafer 2 is etched. As a result, the mold layer 40
is completely removed from the surface 8 of the semiconductor wafer
2. The bottom electrodes 28 are released as free-standing
nanostructures 52 on the surface 8 of the semiconductor wafer
2.
[0063] It should be noted, that the same process chamber can be
used for processing the non-supercritical liquid carbon dioxide
fluid as described above by selecting proper processing conditions,
i.e. a temperature and pressure below the critical point of carbon
dioxide.
[0064] After etching the free-standing nanostructures, contaminants
may be present on the surface of the free-standing nanostructures.
As an example, particles from the mold layer 40 or particles from
other materials present on semiconductor wafer 2 aggregate on the
surface of the free-standing nanostructures. In order to remove
these particles from the surface of the free-standing
nanostructures 52, a cleaning chemistry or composition is injected
into the process chamber 60. As a result, particles aggregated to
the surface of the structural elements of the free-standing
nanostructures 52 on the semiconductor wafer 2 are removed.
[0065] The cleaning chemistry can be a mixture of a supercritical
carbon-dioxide fluid and a cleaning solution. As described
previously with respect to the etching step, the cleaning chemistry
containing the supercritical carbon dioxide fluid and the etching
solution is injected at a temperature and pressure above the
critical point of carbon dioxide, which is located above about
34.degree. C. and about 1050 psi in the phase diagram.
[0066] According to a first exemplary embodiment, a further etching
solution similar to the previously described etching solution is
used for the cleaning solution. The etching solution is chosen with
respect to the material to be removed during the cleaning step.
According to the embodiment shown in FIG. 3B, the free-standing
nanostructures 52 are composed of silicon. Accordingly, an acid
based etching chemistry (for instance HF, H.sub.2SO.sub.4 or HCl
based chemistries) or a dilute basic chemistry such as ammonia
based chemistry might be used. An etching chemistry combining the
use of surfactants can also be used. Various classes of surfactants
may be used in SCCO.sub.2, such as anionic surfactants like
AEROSOL-OT (AOT, "branched" AOTs with methylated groups,
fluorinated AOTs), nonionic surfactants such as TRITON and all its
derivates.
[0067] In this case, etch residues are removed by the surfactants
via transport in micelle structures. Micelle structures can exist
in different shapes including spherical, cylindrical and the like.
Generally, surfactants have a hydrophilic and a hydrophobic part of
the molecules. The hydrophilic part forms in case of non-polar
solvents the core of the micelle while the hydrophobic part remain
on the surface of the micelle. Micelles assist in cleaning by
incorporating the contaminants into their core.
[0068] As a result, the cleaning solution etches the surface of the
free-standing nanostructures 52 up to a thickness between 5 .ANG.
and 100 .ANG. in order to facilitate the separation of particles
from the surface of the free-standing nanostructures 52.
[0069] In a second exemplary embodiment, a cleaning solution being
capable of reducing the aggregation of particles to the
free-standing nanostructures 52 is used. Aggregation of particles
is generally described by the so-called zeta-potential.
[0070] In D. J. Shaw, Introduction to Colloid and Surface
Chemistry, Butterworth-Heinemann Oxford (1993), page 183, which is
incorporated herein by reference, the concept of the zeta potential
is described more detailed. As particles dispersed in a solution,
in this case the cleaning solution, are surrounded by oppositely
charged ions. The layer of opposite charge ions is called the fixed
layer and is accompanied by a cloud-like area being formed of a
ions having opposite polarities so that the whole area appears
electrically neutral. The zeta-potential is considered to be the
electrical potential within the cloud-like area. When this
potential is overcome by the Van-der-Waals binding force, particles
tend to aggregate. Accordingly, the cleaning solution should have a
zeta-potential leading to a sufficient repulsive force between
particle and wafer surface. As a consequence, the cleaning solution
changes the zeta-potential of the surface of the free-standing
nanostructures to promote the separation of the particles from the
surface of the free-standing nanostructures 52.
[0071] To further enhance the removal of particles, it is also
conceivable to apply a mechanical force to the particles. The
mechanical force promotes to fully remove the particles from the
surface of the free-standing nanostructures 52.
[0072] In a first exemplary embodiment, the mechanical force is
applied as a megasonic sound wave. Accordingly, a megasonic source
(or transducer) is provided which is preferably arranged inside the
process chamber 60 with an electrical power feed through. The
transducer is immersed into the fluid for an effective transfer of
the megasonic energy to the wafer surface. Optionally, the
megasonics may also be directed to the wafer surface by a quartz
rod acoustically coupled to a transducer, as disclosed in U.S. Pat.
No. 6,684,890, incorporated herein by reference in its
entirety.
[0073] In a second exemplary embodiment, the mechanical force is
applied by periodically increasing and decreasing of the pressure
of process chamber 60. It is conceivable to operate the process
chamber 60 in a range between 1000 and 7000 psi for 1 to 20 cycles,
for example. In order to increase the efficiency of the cycles, the
pressure may be increased and especially decreased within less than
2 seconds, but the speed of pressure increase or decrease may be
limited by the mechanical force applied to the components in the
process chamber, especially the wafer substrate. Other increase and
decrease sequences of the pressure in process chamber 60 might be
used as well.
[0074] In a third exemplary embodiment, the mechanical force is
applied by agitation of the cleaning chemistry. The agitation
device may be operated in a rotational movement and may be formed
by metallic wings being located within the process chamber 60 above
the semiconductor wafer 2. For reducing metal contamination, the
agitation device might be coated with a polymer (e.g., polyether
ether ketone (PEEK)) so that it remains resistant to chemical
attack under high pressure and temperature conditions. The shape of
the wings as well as distance of the wings to the surface of
semiconductor wafer 2 might be adjusted to generate a optimized
fluid streaming profile so as to achieve most efficient removal of
particle and reduced damage to the structures on the surface of
semiconductor wafer 2.
[0075] In order to remove etching residues during the etching step
or cleaning residues during the cleaning step, the semiconductor
wafer 2 is rinsed in the next step. This is achieved by flooding a
supercritical carbon dioxide fluid into the process chamber 60.
Flooding is performed with a controlled gradient of flow of the
supercritical carbon dioxide fluid which ensures that the etching
chemistry is progressively removed from the reaction mixture.
[0076] After the rinse step, an optional flushing of the
free-standing nanostructures is performed within the process
chamber 60. Again, a supercritical carbon dioxide fluid is used.
The flow of the supercritical carbon dioxide fluid is selected in
the range from 0.1 L/min to 5 L/min, preferably between 0.5 L/min
and 2 L/min (L/min=liters per minute). Again, both the rinse step
and the flushing step can also be performed with non-supercritical
liquid carbon dioxide fluid. Preferably, the same process chamber
60 is used for performing the etching, rinse and flushing steps by
selecting proper processing conditions, i.e. a temperature and
pressure above or below the critical point of the carbon dioxide
fluid.
[0077] Afterwards a drying step of the semiconductor wafer is
performed. This is achieved by venting out supercritical or liquid
carbon dioxide fluid from the process chamber 60. During this step
the pressure created by the venting supercritical carbon dioxide
fluid within the process chamber is released. Since the
supercritical carbon dioxide fluid has negligible surface tension
properties, capillary forces do not occur during drying.
Accordingly, the process sequence according to this embodiment of
the invention is free of stiction.
[0078] According to the embodiment of the invention, stiction free
processing is achieved by employing unique properties of carbon
dioxide in the supercritical state and/or liquid state. The
supercritical state is a high density phase characterized by a low
viscosity and a zero surface tension, thus enabling better
solubility and efficiency of the etching chemistry. On the other
hand, the gas phase presents high diffusion capabilities, allowing
for easy solvent removal and greater drying efficiency. Another
feature of the embodiment of the invention is that the process is
run entirely in the same process chamber 60, ensuring that the
nanostructures remain permanently wetted, and thus eliminating all
together capillary forces. This is possible by making good use of
the carbon dioxide various states, i.e. supercritical, liquid and
gas. The process sequence according to the invention also offers
additional advantages as carbon dioxide is a non-flammable and
non-toxic substance and can easily be recycled.
[0079] Still another feature of the embodiment of the invention is
that a cleaning step is performed after etching the free-standing
nanostructures. Again, the cleaning step runs in the same process
chamber 60 and ensures that the nanostructures are essentially
particle free before further processing continues.
[0080] Accordingly, problems encountered in the prior art with
respect to high aspect ratio nanostructures are circumvented, as
shown below.
[0081] Referring now to FIGS. 6A and 6B, bottom electrodes 28 of
stacked capacitor DRAM-cells are shown which are fabricated by
applying prior art wet etching and drying techniques. In FIG. 6A, a
first SEM-picture 80 shows bottom electrodes 28 of stacked
capacitor DRAM-cells in a side view. In FIG. 6B, a second
SEM-picture 82 shows bottom electrodes 28 of stacked capacitor
DRAM-cells in a top view. Stiction between the neighboring
cylinders of bottom electrodes 28 is clearly visible in the first
SEM-picture 80 and in the second SEM-picture 82.
[0082] Referring now to FIG. 7, free-standing nanostructures 52 of
surrounding gate transistors are shown which are fabricated by
applying prior art wet etching and drying techniques. In FIG. 7, a
third SEM-picture 84 shows nanostructures 52 in a side view.
Stiction between the neighboring nanostructures 52 is clearly
visible in the third SEM-picture 84.
[0083] Referring now to FIG. 8, a flowchart of method steps is
provided for utilizing the system of FIG. 5. Referring to the
flowchart, a semiconductor wafer 2 is provided in step 100. In step
102, a process chamber 60 is provided, which is configured to
accommodate the semiconductor wafer 2. In step 104, the
semiconductor wafer 2 is introduced into the process chamber 60. In
step 106, an etching chemistry is injected into the process chamber
60 to etch the patterned layer 40 and to release free-standing
nanostructures on the semiconductor wafer 2. The etching chemistry
includes a supercritical or liquid carbon dioxide fluid and an
etching solution. In step 108, the semiconductor wafer is rinsed by
flooding a supercritical or liquid carbon dioxide fluid into the
process chamber 60. In step 110, the semiconductor wafer 2 is dried
by injecting a supercritical carbon dioxide fluid into the process
chamber 60 and by venting out the supercritical carbon dioxide
fluid from the process chamber 60.
[0084] Referring now to FIG. 9, a flowchart of method steps is
provided for utilizing the system of FIG. 5 to perform cleaning of
free-standing nanostructures. Referring to the flowchart, a
semiconductor wafer 2 is provided in step 200. The semiconductor
wafer 2 has a substrate and a patterned layer above the substrate.
The patterned layer includes structural elements as free-standing
nanostructures 52 on the substrate of semiconductor wafer 2. In
step 202, a process chamber 60 is provided, which is configured to
accommodate the semiconductor wafer 2. In step 204, the
semiconductor wafer 2 is introduced into the process chamber 60. In
step 206, a cleaning chemistry/composition is injected into the
process chamber 60 to remove particles from the surface of
free-standing nanostructures 52 on the semiconductor wafer 2. The
cleaning chemistry includes a supercritical carbon-dioxide fluid
and a cleaning solution. In step 208, the semiconductor wafer is
rinsed by flooding a supercritical dioxide fluid into the process
chamber 60. In step 210, the semiconductor wafer 2 is dried by
venting out the supercritical carbon dioxide fluid from the process
chamber 60.
[0085] Having described embodiments for a method and a system for
fabricating free-standing semiconductor structures, it is believed
that other modifications, variations and changes will be suggested
to those skilled in the art in view of the teachings set forth
herein. It is therefore to be understood that all such variations,
modifications and changes are believed to fall within the scope of
the present invention as defined by the appended claims and their
equivalents.
REFERENCE NUMERALS
[0086] 2 wafer [0087] 4 substrate [0088] 6 DRAM cell [0089] 8
substrate surface [0090] 10 transistor [0091] 12 capacitor [0092]
14 first junction [0093] 16 second junction [0094] 18 gate
dielectric layer [0095] 19 pillar [0096] 20 gate [0097] 22 bitline
contact [0098] 24 bitline [0099] 26 contact plug [0100] 28 bottom
electrode [0101] 30 dielectric layer [0102] 32 top electrode [0103]
40 hard mask [0104] 41 width of hard mask [0105] 48 trench [0106]
49 trench sidewall [0107] 50 conductive layer [0108] 52
free-standing nanostructures [0109] 60 process chamber [0110] 62
reservoir [0111] 64 control unit [0112] 80 first SEM picture [0113]
82 second SEM picture [0114] 84 third SEM picture [0115] 100-110
process steps [0116] 200-210 process steps
* * * * *
References