U.S. patent application number 11/341578 was filed with the patent office on 2006-07-27 for semiconductor layer and forming method thereof, and semiconductor device and manufacturing method thereof technical field.
Invention is credited to Takeyoshi Koumoto, Hideo Yamagata.
Application Number | 20060163625 11/341578 |
Document ID | / |
Family ID | 19011940 |
Filed Date | 2006-07-27 |
United States Patent
Application |
20060163625 |
Kind Code |
A1 |
Koumoto; Takeyoshi ; et
al. |
July 27, 2006 |
Semiconductor layer and forming method thereof, and semiconductor
device and manufacturing method thereof technical field
Abstract
The present invention relates to a semiconductor layer
applicable to a hetero-junction bipolar transistor, a forming
method thereof, and a semiconductor device and a manufacturing
method thereof, for example. The semiconductor layer and the
forming method thereof according to the present invention includes
a first SiGe film or SiGeC film containing Ge of which the
concentration become equal to a thermal expansion coefficient of
silicon oxide and a second SiGe film or SiGeC film formed on the
first film. In a semiconductor device according to the present
invention and a manufacturing method thereof, first and second
layers are laminated on an oxide film having an opening, and the
first layer has the substantially same thermal expansion
coefficient as that of the oxide film and has a thermal expansion
coefficient different from that of the second layer. Thus, a stress
that is caused by a difference between the thermal expansion
coefficients becomes difficult to occur in the laminated film, and
hence the occurrence of misfit dislocation can be suppressed. Thus,
the present invention is suitable as the application to a
hetero-junction bipolar transistor.
Inventors: |
Koumoto; Takeyoshi; (Tokyo,
JP) ; Yamagata; Hideo; (Kanagawa, JP) |
Correspondence
Address: |
SONNENSCHEIN NATH & ROSENTHAL LLP
P.O. BOX 061080
WACKER DRIVE STATION, SEARS TOWER
CHICAGO
IL
60606-1080
US
|
Family ID: |
19011940 |
Appl. No.: |
11/341578 |
Filed: |
January 26, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10480061 |
Dec 5, 2003 |
|
|
|
PCT/JP02/05512 |
Jun 4, 2002 |
|
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11341578 |
Jan 26, 2006 |
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Current U.S.
Class: |
257/288 ;
257/E21.371; 257/E29.193; 438/309 |
Current CPC
Class: |
H01L 29/7378 20130101;
H01L 29/66242 20130101; Y10S 438/933 20130101; Y10S 438/938
20130101 |
Class at
Publication: |
257/288 ;
438/309 |
International
Class: |
H01L 29/76 20060101
H01L029/76; H01L 21/331 20060101 H01L021/331 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 5, 2001 |
JP |
JP 2001-169927 |
Claims
1-12. (canceled)
13. A semiconductor device comprising an insulating film provided
on a substrate, a first layer interconnected to said substrate
through an opening formed on said insulating film and a second
layer formed on said first layer, wherein said first layer is
formed so as to contact with said insulating film and said
substrate, said first layer has a thermal expansion coefficient
substantially the same as that of said insulating film and said
second layer has a thermal expansion coefficient different from
that of said first layer.
14. A semiconductor device according to claim 13, wherein said
first layer includes at least Ge and said second layer includes Ge
and C.
15. A semiconductor device according to claim 13, wherein said
first layer is made of SiGe and said second layer is made of
SiGeC.
16. A semiconductor device according to claim 13, wherein said
first layer is made of SiGeC and said second layer is made of SiGeC
of which the Ge concentration is different from that of said
SiGeC.
17. A semiconductor device according to claim 13, wherein said
first layer is made of SiGe and said second layer is made of SiGe
of which the Ge concentration is different from that of said
SiGe.
18. A semiconductor device according to claim 13, wherein said
second layer contains N-type or P-type impurities.
19. A semiconductor device according to claim 14, wherein said Ge
concentration in said first layer is made constant in the layer
thickness direction in a range of from 4 to 10 atomic %.
20. A semiconductor device according to claim 15, wherein said Ge
concentration in said first layer is made constant in the layer
thickness direction in a range of from 4 to 10 atomic %.
21. A semiconductor device according to claim 16, wherein said Ge
concentration in said first layer is made constant in the layer
thickness direction in a range of from 4 to 10 atomic %.
22. A semiconductor device according to claim 17, wherein said Ge
concentration in said first layer is made constant in the layer
thickness direction in a range of from 4 to 10 atomic %.
23. A semiconductor device manufacturing method comprising: forming
an insulating film on a substrate; forming an opening on said
insulating film; forming a first semiconductor film with
substantially the same thermal expansion coefficient as that of
said insulating film on said opening and a process for forming a
second semiconductor film with a thermal expansion coefficient
different from that of said first semiconductor film on said first
semiconductor film.
24. A semiconductor device manufacturing method according to claim
23, wherein said first semiconductor film includes at least Ge and
said second semiconductor film includes Ge and C.
25. A semiconductor device manufacturing method according to claim
23, wherein said first semiconductor film is made of SiGe and said
second semiconductor film is made of SiGeC.
26. A semiconductor device manufacturing method according to claim
23, wherein said first semiconductor film is made of SiGeC and said
second semiconductor film is made of SiGeC of which the Ge
concentration is different from that of said SiGeC.
27. A semiconductor device manufacturing method according to claim
23, wherein said first semiconductor film is made of SiGe and said
second semiconductor film is made of SiGe of which the Ge
concentration is different from that of said SiGe.
28. A semiconductor device manufacturing method according to claim
24, wherein said Ge concentration in said first semiconductor film
is made constant in the film thickness direction in a range of from
4 to 10 atomic %.
29. A semiconductor device manufacturing method according to claim
25, wherein said Ge concentration in said first semiconductor film
is made constant in the film thickness direction in a range of from
4 to 10 atomic %.
30. A semiconductor device manufacturing method according to claim
26, wherein said Ge concentration in said first semiconductor film
is made constant in the film thickness direction in a range of from
4 to 10 atomic %.
31. A semiconductor device manufacturing method according to claim
27, wherein said Ge concentration in said first semiconductor film
is made constant in the film thickness direction in a range of from
4 to 10 atomic %.
32. A semiconductor device manufacturing method according to claim
23, further comprising a process for forming a base layer by
patterning a laminated film including said first and second
semiconductor films and into which base impurities are introduced
and a process for forming an emitter region within said base
layer.
33-42. (canceled)
Description
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor layer
containing a silicon germanium (SiGe) film or a silicon germanium
carbon (SiGeC) film and a forming method thereof and a
semiconductor device and a manufacturing method thereof.
BACKGROUND ART
[0002] In recent years, in accordance with the arrival of a
multimedia era in which information, services, entertainment,
communications and the like are united, need for transmitting data
of a large data amount at a high speed is progressively increasing,
and it is also requested that bipolar transistors can operate at a
higher speed. In order to enable the bipolar transistor to operate
at a higher speed, a width of a base layer has to decrease and its
carrier concentration has to increase. However, when a base layer
is formed by implanting ions of impurities, due to channeling of
impurities caused when ions of impurities are implanted, it is
difficult to realize the base width of less than 40 nm. Therefore,
it has been considered to deposit a base layer on a silicon (Si)
substrate by an epitaxial growth method.
[0003] However, even when the homogeneous-junction base layer is
deposited on the substrate by an epitaxial growth method, if a
carrier concentration of the base layer increases, then holes that
are to be implanted into the emitter from the base increases so
that a current gain decreases. For this reason, there is considered
a hetero-junction bipolar transistor in which abase layer
containing a silicon germanium (Si.sub.1-xGe.sub.x, hereinafter
referred to as a "SiGe") film having a band gap width narrower than
that of the Si film is deposited on a single crystal Si substrate
by an epitaxial growth method, injections of holes into the emitter
being considerably decreased by utilizing a fact that a potential
barrier relative to holes is higher than a potential barrier
relative to electrons.
[0004] In the hetero-junction bipolar transistor, a base resistance
can be decreased by increasing a carrier concentration of the base,
and a sufficiently large current amplification width (hFE) can be
obtained. As a result, while a sufficiently large withstand voltage
is being maintained, a high frequency characteristic can be
realized.
[0005] However, since Si and Ge have different lattice constants
and thermal expansion coefficients, a stress occurs in the base
layer containing SiGe. As a consequence, during a manufacturing
process of heterojunction bipolar transistor after the base layer
has been formed, a crystal defect which is referred to as a "misfit
dislocation" occurs in the base layer so that a yield of the
hetero-junction bipolar transistor is lowered. Because the misfit
dislocation strongly depends on the Ge concentration in the SiGe,
if the Ge concentraton is lowered, then it is possible to suppress
the occurrence of the misfit dislocation. However, according to the
above-mentioned proposal, effects for narrowing the width of the
band gap of the base layer also decrease so that a hetero-junction
bipolar transistor having desired performance cannot be
obtained.
[0006] As another countermeasure for suppressing the occurrence of
such misfit dislocation, it has been reported that the use of
silicon germanium carbon (Si.sub.1-x-yGe.sub.xCy, hereinafter
referred to as a "SiGeC") in which a very small amount of carbon
(C) is added to SiGe is effective ("CVDSi.sub.1-x-y-l
Ge.sub.xC.sub.y epitaxial growth and doping control", pp. 32-37,
Subcommittee of The Society of Applied Physics, Silicon Technology
No. 18, 23.sup.rd June, 2000) This technique is based on the fact
that a distortion caused by a difference between lattice constants
of Si and Ge can be alleviated by adding C to SiGe.
[0007] Moreover, since SiGeC has a considerably high diffusion
control effect for impurities such as boron (B) as compared with
SiGe, SiGeC has another advantage that the hetero-junction bipolar
transistor can obtain a steep B doping profile having a high
concentration as compared with SiGe. This is effective for
decreasing a base resistance (R.sub.b) and reducing a base running
time (.tau..sub.B) and which is advantageous for improving a high
frequency characteristic of the hetero-junction bipolar
transistor.
[0008] However, when the base forming region is prescribed by a
silicon oxide film formed on a substrate, if an SiGeC film that
serves as a base layer communicating with a single crystal Si
substrate exposed through an opening of this silicon oxide
(SiO.sub.2) film and the SiO.sub.2 film is formed, then a stress
that is caused by a difference between thermal expansion
coefficients of the SiGeC film and the SiO.sub.2 film occurs so
that the misfit dislocation tends to occur.
[0009] Therefore, it is difficult to provide a semiconductor device
containing a hetero-junction bipolar transistor at a high
yield.
DISCLOSURE OF THE INVENTION
[0010] An object of the present invention is to provide a
hetero-junction layer with excellent crystal quality and its
deriving electrode, and it is another object of the present
invention to provide a semiconductor device containing a
hetero-junction bipolar transistor at a high yield.
[0011] A semiconductor layer according to the first invention
comprises a first SiGe film or a first SiGeC film communicated with
each other on a single crystal silicon substrate exposed through an
opening of an insulating film formed on the single crystal silicon
substrate and the insulating film, the first film being of single
crystal and polycrystal on the exposed single crystal silicon
substrate and the insulating film and the first film containing Ge
having a concentration of which the thermal expansion coefficient
is equal to or becomes close to that of the insulating film and a
second SiGe film or a second SiGeC film communicated with each
other on the first SiGe film or the first SiGeC film, the second
film being of single -crystal and polycrystal above the exposed
single crystal silicon substrate and the insulating film and the
second film having a Ge concentration different from that of the
first SiGe film or the first SiGeC film.
[0012] A semiconductor layer forming method according to the first
invention comprises a process for forming a first SiGe film or a
first SiGeC film communicated with each other on a single crystal
silicon substrate exposed through an opening of an insulating film
formed on the single crystal silicon substrate and the insulating
film, the first film being of single crystal and polycrystal on the
exposed single crystal silicon substrate and the insulating film
and the first film containing Ge having a concentration in which a
thermal expansion coefficient is equal to or becomes close to that
of the insulating film and a process for forming a second SiGe film
or a second SiGeC film communicated with each other on the first
SiGe film or the first SiGeC film, the second film being of single
crystal and polycrystal above the exposed single crystal silicon
substrate and the insulating film and the second film having the Ge
concentration different from that of the first SiGe film or the
first SiGeC film.
[0013] A semiconductor device according to the second invention
comprises an insulating film provided on a substrate, a first layer
interconnected to the substrate through an opening formed on this
insulating film and a second layer formed on this first layer,
wherein the first layer is formed so as to contact with the
insulating film and the substrate, the first layer having a thermal
expansion coefficient that is substantially the same as that of the
insulating film and the second layer having a thermal expansion
coefficient different from that of the first layer.
[0014] A semiconductor device manufacturing method according to the
second invention comprises a process for forming an insulating film
on a substrate, a process for forming an opening on the insulating
film, a process for forming a first semiconductor film with a
thermal expansion coefficient substantially equal to that of the
insulating film on the opening and a process for forming a second
semiconductor film with a thermal expansion coefficient different
from that of the first semiconductor film on the first
semiconductor film.
[0015] A semiconductor device according to the third invention
comprises a first SiGe film or a first SiGeC film communicated with
each other in a single crystal silicon substrate exposed through an
opening of an insulating film that prescribes a base forming region
of a bipolar transistor, the first film being of single crystal and
polycrystal on the exposed single crystal silicon substrate and the
insulating film and the first film containing Ge of which the
concentration becomes equal to a thermal expansion coefficient of
the insulating film and a second SiGe film or a second SiGeC film
being communicated with each other on the first SiGe film or the
first SiGeC film, the second film being of single crystal or
polycrystal above the exposed single crystal silicon substrate and
the insulating film.
[0016] A semiconductor device manufacturing method according to the
third invention comprises a process for forming a first SiGe film
or a first SiGeC film communicated with each other on a single
crystal silicon substrate exposed through an opening of an
insulating film provided on the single crystal silicon substrate
and which prescribes a base forming region of a bipolar transistor
and the insulating film, the first film being of single crystal and
polycrystal on the exposed single crystal silicon substrate and the
insulating film and the first film containing Ge of which the
concentration is equal to or becomes close to a thermal expansion
coefficient of the insulating film and a process for forming a
second SiGe film or a second SiGeC film communicated with each
other on the first SiGe film or the first SiGeC film, the second
film being of single crystal and polycrystal above the exposed
single crystal silicon substrate and the insulating film and the
second film having a Ge concentration different from that of the
first SiGe film or the first SiGeC film.
[0017] The first layer or the first semiconductor film may contain
at least Ge and the second layer or the second semiconductor layer
may contain Ge and C. The first layer or the first semiconductor
film may be made of SiGe, and the second layer or the second
semiconductor film may be made of SiGeC. The first layer or the
first semiconductor film may be made of SiGeC, and the second layer
or the second semiconductor film may be made of SiGeC of which the
Ge concentration is different from that of the SiGeC. The first
layer or the first semiconductor film may be made of SiGe, and the
second layer or the second semiconductor film may be made of SiGe
of which the Ge concentration is different from that of the SiGe.
The insulating film may be formed as the oxide film.
[0018] The Ge concentration in the first SiGe film or the first
SiGeC film, the first film or the first semiconductor film should
preferably be made constant in the film or layer thickness
direction in a range of from 4 to 10 atomic %.
[0019] In the above-described manufacturing method, monosilane
(SiH.sub.4) gas may be used as a raw material of silicon, germanium
(GeH.sub.4) gas may be used as a raw material of germanium and
methyl silane (SiCH.sub.6) gas may be used as a raw material of
carbon, respectively. When the present invention is applied to a
bipolar transistor, the bipolar transistor may be manufactured in
such a manner that a base layer may be formed by patterning a
laminated film including the above-described first and second
semiconductor films and into which impurities have been introduced,
an emitter region being formed within this base layer.
[0020] Since the semiconductor layer and the forming method thereof
according to the first invention uses the first SiGe film or the
first SiGeC film containing the Ge having the concentration in
which the thermal expansion coefficient is equal to or becomes
close to that of the insulating film, the stress that causes the
misfit dislocation can be decreased. Not only the thermal expansion
coefficients become equal to each other between this insulating
film and the first SiGe film or the first SiGeC film but also the
sudden change of the thermal expansion coefficient between the
first SiGe film or the first SiGeC film and the second SiGe film or
the second SiGeC film having the different Ge concentration can be
alleviated. Accordingly, the single crystal semiconductor layer can
be formed as the hetero-junction layer, the polycrystal
semiconductor layer can be formed as the deriving electrode for the
heterojunction layer, and the stress that has been caused by the
difference between the thermal expansion coefficients can be made
difficult to occur in the semiconductor layer. Therefore, the
occurrence of the misfit dislocation can be suppressed in the
hetero-junction layer during the manufacturing process of the
semiconductor device after the semiconductor layer has been formed,
and hence there can be provided the hetero-junction layer with the
excellent crystal quality and its deriving electrode.
[0021] Since the semiconductor device according to the second
invention and the manufacturing method thereof use the first layer
of which the thermal expansion coefficient is substantially the
same as that of the insulating film, it impossible to decrease the
stress that causes the misfit dislocation. Not only this insulating
film and the first layer have substantially the same thermal
expansion coefficients but also the sudden change of the thermal
expansion coefficient between the first layer and the second layer
can be alleviated. Accordingly, the single crystal semiconductor
layer can be formed as the hetero-junction base layer, the
polycrystal semiconductor layer can be formed as the base deriving
electrode, and the stress that is caused by the difference between
the coefficients of thermal expansion can be made difficult to
occur in the semiconductor layer. Therefore, the occurrence of the
misfit dislocation can be suppressed in the hetero-junction base
layer during the manufacturing process of the semiconductor device
after the semiconductor layer has been formed, and hence the
semiconductor device containing the hetero-junction bipolar
transistor can be provide at a high yield.
[0022] Since the semiconductor device according to the third
invention and the manufacturing method thereof use the first SiGe
film or the first SiGeC film containing the Ge having the
concentration in which the thermal expansion coefficient is equal
to or becomes close to that of the insulating film, the stress that
causes the misfit dislocation can be decreased. Not only the
thermal expansion coefficients become equal to each other between
this insulating film and the first SiGe film or the first SiGeC
film but also the sudden change of the thermal expansion
coefficient between the first SiGe film or the first SiGeC film and
the second SiGe film or the second SiGeC film having the different
Ge concentration can be alleviated. Accordingly, the single crystal
semiconductor layer can be formed as the hetero-junction base
layer, the polycrystal semiconductor layer can be formed as the
base deriving electrode, and the stress that is caused by the
difference between the coefficients of thermal expansion can be
made difficult to occur in the semiconductor layer. Therefore, the
occurrence of the misfit dislocation can be suppressed in the
heterojunction base layer in the manufacturing process of the
semiconductor device after the semiconductor layer has been formed,
and hence the semiconductor device that contains the
hetero-junction bipolar transistor can be provided at a high
yield.
BRIEF DESCRIPTION OF DRAWINGS
[0023] FIG. 1 is a cross-sectional view of a semiconductor device
according to a second reference example;
[0024] FIG. 2 is a partial cross-sectional view in a manufacturing
process of the semiconductor device according to the second
reference example;
[0025] FIG. 3 is a partial cross-sectional view in a manufacturing
process of the semiconductor device according to the second
reference example;
[0026] FIG. 4A is a time chart showing a forming method of a
semiconductor layer according to a second reference example;
[0027] FIG. 4B is a graph showing a Ge concentration distribution
in the height direction of the semiconductor layer according to the
second reference example;
[0028] FIG. 5 is a graph showing concentration distributions of
various kinds of impurities and Ge in the depth direction of the
semiconductor device according to the second reference example;
[0029] FIG. 6 is a partial cross-sectional view showing the
situation in which a stress occurs in a semiconductor device
according to a third reference example;
[0030] FIG. 7A is a graph to which reference will be made in
explaining a principle of the present invention and illustrates a
relationship between temperatures of various kinds of substances
and thermal expansion coefficients;
[0031] FIG. 7B is a graph to which reference will be made in
explaining a principle of the present invention and illustrates a
relationship between temperatures and thermal expansion
coefficients obtained when a Ge concentration in SiGe is
changed;
[0032] FIG. 8 is a manufacturing process diagram showing a
manufacturing method of a semiconductor device according to an
embodiment of the present invention (No. 1);
[0033] FIG. 9 is a manufacturing process diagram showing a
manufacturing method of a semiconductor device according to an
embodiment of the present invention (No. 2);
[0034] FIG. 10 is a manufacturing process diagram showing a
manufacturing method of a semiconductor device according to an
embodiment of the present invention (No. 3);
[0035] FIG. 11 is a manufacturing process diagram showing a
manufacturing method of a semiconductor device according to an
embodiment of the present invention (No. 4);
[0036] FIG. 12 is a manufacturing process diagram showing a
manufacturing method of a semiconductor device according to an
embodiment of the present invention (No. 5);
[0037] FIG. 13 is a manufacturing process diagram showing a
manufacturing method of a semiconductor device according to an
embodiment of the present invention (No. 6);
[0038] FIG. 14 is a manufacturing process diagram showing a
manufacturing method of a semiconductor device according to an
embodiment of the present invention (No. 7);
[0039] FIG. 15 is a manufacturing process diagram showing a
manufacturing method of a semiconductor device according to an
embodiment of the present invention (No. 8);
[0040] FIG. 16 is a manufacturing process diagram showing a
manufacturing method of a semiconductor .device according to an
embodiment of the present invention (No. 9);
[0041] FIG. 17 is a manufacturing process diagram showing a
manufacturing method of a semiconductor device according to an
embodiment of the present invention (No. 10);
[0042] FIG. 18A is a time chart showing a semiconductor layer
forming method according to an embodiment of the present
invention;
[0043] FIG. 18B is a graph of a Ge concentration distribution in
the height direction of a semiconductor layer according to an
embodiment of the present invention;
[0044] FIG. 19 is a partial cross-sectional view in a manufacturing
process of a semiconductor device according to an embodiment of the
present invention;
[0045] FIG. 20 is a partial cross-sectional view in a manufacturing
process of a semiconductor device according to an embodiment of the
present invention;
[0046] FIG. 21 is a graph showing concentration distributions of
various kinds of impurities and Ge in the depth direction of a
semiconductor device according to an embodiment of the present
invention;
[0047] FIG. 22 is a cross-sectional view of a main portion showing
a semiconductor device according to another embodiment of the
present invention;
[0048] FIG. 23A is a graph of stresses occurred at the positions
extending along the channels of the semiconductor devices according
to the embodiments of the present invention and the reference
examples;
[0049] FIG. 23B is a partial cross-sectional view of the
semiconductor device and illustrates the channels in FIG. 23A;
and
[0050] FIG. 24 is a cross-sectional view of a main portion showing
a semiconductor device according to other embodiment of the present
invention.
BEST NODE FOR CARRYING OUT THE INVENTION
[0051] Embodiments of the present invention will be described below
with reference to the drawings.
[0052] In order to facilitate the understanding of a
hetero-junction bipolar transistor according to this embodiment,
reference examples will be described.
[0053] A first example refers to a manufacturing process of an SiGe
hetero-junction bipolar transistor in which SiGe films that are
communicating with each other are simultaneously formed on a single
crystal Si substrate exposed through an opening of a siliconoxide
(SiO.sub.2) film which prescribes a base forming region and the
SiO.sub.2 film to form a single crystal SiGe film on the Si
substrate as a base layer, a polycrystal SiGe film on the SiO.sub.2
film being formed as a base deriving electrode. In this case, since
a stress caused by a difference among thermal expansion
coefficients of Si, Ge and SiO.sub.2 also occurs in addition to a
stress caused by a difference between the above-mentioned physical
properties of Si and Ge, a misfit dislocation tends to occur more
easily.
[0054] FIGS. 1 to 5 show an NPN type SiGe hetero-junction bipolar
transistor according to a second reference example and a
manufacturing method thereof. As shown in FIG. 1, in order to
manufacture this hetero-junction bipolar transistor, an SiO.sub.2
film (not shown) is deposited on the surface of a P-type Si
substrate 11 by thermal oxidation and an opening that prescribes a
collector forming region is formed on the SiO.sub.2 film. Then, an
antimony oxide (Sb.sub.2O.sub.3) film is formed on the Si substrate
exposed through the opening of the SiO.sub.2 film and the SiO.sub.2
film and Sb is diffused to the Si substrate 11 from the
Sb.sub.2O.sub.3 film through the opening of the SiO.sub.2 film by a
solid-phase technique to form an N.sup.+ region 12 as a collector.
Thereafter, the Sb.sub.2O.sub.3 impurities of the base is formed
under the opening 27 by implanting ions of phosphor. Then, the
resist is removed from the SiO.sub.2 26.
[0055] Next, a polycrystal Si film 31 that functions as a
conductive film and the impurity diffusing source is deposited by a
CVD method, and ions of arsenic are implanted into this polycrystal
Si film 31. Then, by the lithography and the RIE, the polycrystal
Si film 31 and the SiO.sub.2 film 26 are successively processed so
as to have emitter electrode patterns, and the laminated film 25 is
exposed. Thereafter, while the resist on the polycrystal Si film 31
is being used as a mask, ions of B for reducing resistance at the
portion of the base deriving electrode are implanted into the
laminated film 25. Then the resist is removed from the polycrystal
Si film 31.
[0056] Next, ions of impurities implanted into the SIC region 28,
the polycrystal Si film 31 and the laminated film 25 are activated
by a heat treatment, and an N.sup.+ region 32 is formed as an
emitter by diffusing ions of arsenic into the Si film 24 of the
laminated film 25 from the polycrystal Si film 31 through the
opening 27. Then, an SiO.sub.2 film 33 is deposited as an
interlayer insulator and an interconnection hole 34 that reaches
the polycrystal Si film 31, the laminated film 25 and the N.sup.+
region 17 is bored through the SiO.sub.2 film 33: by the
lithography and the RIE.
[0057] Next, the interconnection hole 34 is filled with a plug 35
made of tungsten by a combination of a blanket CVD method and
etching or a selective CVD method. Then, an Al alloy film 36, for
example, is deposited by a sputtering method, for example, and the
Al alloy film 36 is processed so as to have an emitter electrode
interconnection pattern, a base electrode interconnection pattern
and a collector electrode interconnection pattern by the
lithography and the RIE. FIG. 5 shows concentration distributions
of various kinds of impurities and Ge in the depth direction from
the polycrystal Si film 31 to the N.sup.+ region 12 of the
hetero-junction bipolar transistor thus manufactured, i.e.
concentration distributions taken along the line A-A in FIG. 1.
[0058] FIG. 6 shows a third reference example. This hetero-junction
bipolar transistor comprises an SiGe film 37 instead of the SiGeC
film 23 in the second reference example shown in FIGS. 1 and 2 and
a laminated film 38 composed of the Si film 22, the SiGe film 27
and the Si film 24. A rest of arrangement is similar to that of
FIG. 1. FIG. 5 shows the situation in which a stress occurs in the
hetero-junction bipolar transistor of the third reference example.
The SiGe film 37 is formed by omitting the addition of SiCH.sub.6
gas from the raw material gas of the SiGeC film 23. As shown in
FIG. 6, stresses occur near the boundary between the Si film 22 and
the SiGe film 37 above the SiO.sub.2 film 18 and near the interface
between the SiO.sub.2 film 18 and the Si film 22. In particular,
stresses tend to concentrate near the end edge of the opening 21
that prescribes the base forming region. Then, these stresses cause
the misfit dislocation to occur.
[0059] Although the lattice constants and the thermal expansion
coefficients of Si and Ge are different from each other in the SiGe
film 37 as already described, a lattice distortion may be
alleviated in the SiGeC film 23 for use with the laminated film 25
by the addition of C. However, since both of the laminated films 25
and 38 have the Si film 22 deposited on the SiO.sub.2 film 18, it
may be considered that stresses of distribution similar to those of
FIG. 6 to a certain extent occur in the hetero-junction bipolar
transistor according to the second reference example having the
laminated film 25.
[0060] Prior to the description of the embodiments of the present
invention, the principle of the present invention will be described
first.
[0061] In the laminated film 25 of the above-mentioned
hetero-junction bipolar transistor according to the second
reference example, since the SiGeC film 23 is laminated on the Si
film 22, as shown in FIG. 5, the Ge concentration suddenly
increases from 0 atomic % to 15 atomic % at the interface between
these Si film 22 and SiGeC film 23.
[0062] Therefore, as is clear from FIG. 7B, the thermal expansion
coefficient near a room temperature, for example, suddenly changes
from about +2.5.times.10.sup.-6 [1/K] (Ge concentration=0 atomic %,
i.e.,) to about -6.0.times.10.sup.-6 [1/K] (Ge concentration=14.4
atomic %) along the negative direction at the interface between
these Si film 22 and SiGeC film 23. In addition, as shown in FIG.
7A, since the value of the thermal expansion coefficient of
SiO.sub.2 is approximately zero, in particular, on the SiO.sub.2
film 18 on which the opening 21 should be formed, the sudden change
of the thermal expansion coefficient at the interface between the
SiO.sub.2 film 18 and the Si film 22 in the positive direction is
added to the above-mentioned change of the thermal expansion
coefficient in the negative direction.
[0063] Then, it may be considered that the stress caused by the
difference between the thermal expansion coefficients is a factor
that causes the misfit dislocation to occur in the laminated film
25 during the manufacturing process of the hetero-junction bipolar
transistor after the laminated film 25 has been formed. However, as
is clear from FIG. 7B, in the SiGe in which the Ge concentration
falls within a range of from 4 to 10 atomic %, e.g. 7.75 atomic %,
the value of the thermal expansion coefficient is approximately
zero. Accordingly, in the embodiment that will be described later
on, instead of the Si film 22 in the laminated film 25 of the
hetero-junction bipolar transistor of the second reference example,
there is used the SiGe film of which the Ge concentration falls
within a range of from 4 to 10 atomic %, e.g. 7.75 atomic %.
[0064] As described above, if the SiGe film whose Ge concentration
is 7.75 atomic % is used instead of the Si film 22, then the change
of the thermal expansion coefficient at the interface between the
SiO.sub.2 film 18 and the SiGe film reaches a value close to zero,
and the sudden change of the thermal expansion coefficient at the
interface between the SiGe film and the SiGeC film 23 can be
alleviated. As a result, the stress that is caused by the
difference between the coefficients of thermal expansion is
difficult to occur in the laminated film that functions as the base
layer and the base deriving electrode, and the occurrence of misfit
dislocation can be suppressed.
[0065] Next, an embodiment of the present invention that is applied
to an NPN type SiGeC hetero-junction bipolar transistor and a
manufacturing method thereof will be described with reference to
manufacturing process diagrams of FIGS. 8 to 17.
[0066] First, as shown in FIG. 8, an insulating film, in this
embodiment, an SiO.sub.2 film 19 is formed on the surface of a
P-type Si substrate 11 by thermal oxidation, and an opening 19A
that prescribes a collector forming region is formed on the
SiO.sub.2 film 19. Then, an N-type impurity containing film, in
this embodiment, an antimony oxide (Sb.sub.2O.sub.3) film 20 is
formed on the Si substrate 11 exposed through the opening 19A of
the SiO.sub.2 film 19 and the SiO.sub.2 film 19, and an N.sup.+
region 12 is formed as a collector by solid-phase-diffusing Sb into
the Si substrate 11 through the opening 19A of the SiO.sub.2 film
19 from the Sb.sub.2O.sub.3 film 20. Thereafter, the
Sb.sub.2O.sub.3 film and the SiO.sub.2 film are removed.
[0067] Then, as shown in FIG. 9, an N-type epitaxial layer 13 is
formed on the Si substrate 11, and the Si substrate 11 and the
epitaxial layer 13 constitute the Si substrate 14. Then, an
SiO.sub.2 film 15 is formed as an element separation insulating
film by a LOCOS method, and a P.sup.+ region 16 is formed as an
element separation region by an ion implantation method. An N.sup.+
region 17 that functions as a plug to be interconnected to the
N.sup.+ region 12 is formed in the epitaxial layer 13 at its
predetermined portion. Then, an SiO.sub.2 film 18 is deposited by a
CVD (chemical vapor deposition) method using tetraethoxy silane
(TEOS) as raw material gas, and the SiO.sub.2 film 18 is made dense
by a heat treatment.
[0068] Next, as shown in FIG. 10, a resist (not shown) is coated on
the SiO.sub.2 film 18 and the resist is processed so as to have a
pattern with an opening corresponding to a base forming region by
the lithography. Then, an opening 21 is formed on the SiO.sub.2
film 18 by the RIE (reactive ion etching) using this resist as a
mask and the following wet etching. At that time, the RIE is
carried out in order to increase dimension accuracy of the opening
21 and the lie by its anisotropy. The wet etching following the RIE
is carried out to in order to suppress the surface of the Si
substrate 14 exposed through the opening 21 from being damaged.
Thereafter, the resist is removed from the SiO.sub.2 film 18.
[0069] Next, in order to remove an organic matter that is a residue
of the resist attached to the surface of the Si substrate 14, the
Si substrate 14 is rinsed by mixed solution of sulfuric acid and
hydrogen peroxide heated at a predetermined temperature, for
example. Moreover, in order to remove particles from the Si
substrate 14, the Si substrate 14 is rinsed by mixed solution of
ammonia water and hydrogen peroxide heated at a predetermined
temperature, for example. Further, in order to remove a metal
pollutant and a natural oxide film from the surface of the Si
substrate 14, the Si substrate 14 is rinsed by dilute hydrofluoric
acid. When the Si substrate 1 is rinsed by dilute hydrofluoric
acid, the hydrogen passivation treatment also is carried out and
the exposed surface of the Si substrate 14 is ended by
hydrogen.
[0070] Next, in order to carry out low-temperature epitaxial
growth, the Si substrate 14 is carried into the low pressure CVD
system. At that time, first, the Si substrate 14 is carried into
the load-lock chamber having vacuum evacuation function, and the
load-lock chamber has been evacuated for a predetermined time
period. Thereafter, while the Si substrate 14 is being protected
from being exposed to the air, the Si substrate 14 is carried into
the reaction chamber connected the load-lock chamber. Then, while
hydrogen gas is being introduced into the reaction chamber, the
temperature of the Si substrate 14 is caused to rise up to about
900.degree. C. and baked under atmosphere of hydrogen gas for about
5 minutes. Thereafter, while the introduction of hydrogen gas into
the reaction chamber is being continued, the temperature within the
reaction chamber drops into about 680.degree. C. and the following
CVD is carried out.
[0071] Specifically, as shown in FIG. 18A, first, the temperature
within the reaction chamber is set to about 710.degree. C. Then,
while the pressure within the reaction chamber is being held at
about 10666 Pa (80 Torr) and the flow rate of hydrogen gas is being
held at the constant state of 20SLM, an SiGe film 41 having a
thickness ranging from 5 to 30 nm, e.g. about 15 nm is deposited on
the Si substrate 14 and the SiO.sub.2 film 18 by supplying
SiH.sub.4 gas of 20 sccm and GeH.sub.4 of the amount whose Ge
concentration in the film falls within a range of 4 to 10 atomic %,
e.g. 7.75 atomic % into the reaction chamber as shown in FIGS. 11
and 19. The temperature obtained within the reaction chamber at
that time may be the same temperature as that used when the next
SiGeC film 23 is deposited (680.degree. C. in this embodiment).
[0072] Subsequently, the temperature within the reaction chamber is
caused to drop into about 680.degree. C. and the SiGeC film 23 is
deposited on the SiGe film 41 by supplying SiH.sub.4 gas germanium
(GeH.sub.4) gas and methyl silane (SiCH.sub.6). gas into the
reaction chamber while their flow rates are being controlled such
that a desired Ge concentration, a desired C concentration and a
desired film thickness may be obtained. At that time, diborane
(B.sub.2H.sub.6) gas is supplied to the reaction chamber while its
flow rate is being controlled such that B (boron) may have a
desired concentration profile in the SiGeC film 23. Subsequently,
while the temperature within the reaction chamber is being held at
approximately 680.degree. C., the Si film 24 having a desired
thickness with B added thereto is deposited on the SiGeC film 23 by
supplying the SiH.sub.4 gas and the B.sub.2H.sub.6 gas into the
reaction chamber. As shown in FIGS. 12 and 19, the SiGeC film 23
and the Si film 24 are sequentially laminated on this SiGe film 41
and thereby a laminated film 42 composed of these films is
formed.
[0073] FIG. 18B shows a Ge concentration distribution shape in the
height direction of this laminated film 42. As shown in FIG. 20,
this laminated film 42 also has a single crystal film 42a formed at
its portion on the Si substrate 14 exposed through the opening 21
and a polycrystal film 42b at its portion on the SiO.sub.2 film
18.
[0074] The SiGe film 41 in the laminated film 42 is used in order
to smooth miniscule concavities and convexities on the surface of
the Si substrate 14 exposed from the opening 21. The SiGe film 41
in the laminated film 42 also is used as the seed film required
when the polycrystal film 42b is formed on the SiO.sub.2 film 18.
After the insulating film 42 has been formed as described above, as
shown in FIG. 13, the laminated film 42 and the SiO.sub.2 film 18
are successively processed so as to have a base layer pattern and a
base deriving electrode pattern by the lithography and the RIE.
[0075] Next, as shown in FIG. 14, an SiO.sub.2 film 26 is deposited
as an insulating film by a CVD method and the SiO.sub.2 film 26 is
made dense by a heat treatment. Then, an opening 27 corresponding
to the emitter forming region is formed on the SiO.sub.2 film 26 by
the lithography and the RIE. Thereafter, while the resist on the
SiO.sub.2 film 26 is being used as the mask, a region 28 that is
used to cancel impurities on the collector side out from impurities
of the base is formed under the opening 27 by implanting ions of
phosphor into the epitaxial layer 13. Then, the resist is removed
from the SiO.sub.2 film 26.
[0076] Next, as shown in FIG. 15, a polycrystal Si film 31 that may
function as a conductive film and an impurity diffusion source is
deposited by the CVD method, and ions of arsenic are implanted into
this polycrystal Si film 31. Then, by the lithography and the RIE,
the polycrystal Si film 31 and the SiO.sub.2 film 26 are
successively processed so as to have emitter electrode patterns,
and a laminated film 42 is exposed. Thereafter, while the resist on
the polycrystal Si film 31 is being used as a mask, ions of B that
is used to decrease a resistance on the part of the base deriving
electrode are implanted into the laminated film 42. Then, the
resist is removed from the polycrystal Si film 31.
[0077] Next, as shown in FIG. 16, ions of impurities that have been
implanted into the SIC region 28, the polycrystal Si film 31 and
the laminated film 42a reactivated by a heat treatment, and an
N.sup.+ region 32 is formed as an emitter by diffusing arsenic into
the Si film 24 of the laminated film 42 from the polycrystal Si
film 31 through the opening 27. Then, an SiO.sub.2 film 33 is
deposited as an interlayer insulator by the CVD method, and a
interconnection hole 34 that reaches the polycrystal Si film 31,
the laminated film 42 and the N.sup.+ region 17 is formed on the
SiO.sub.2 film 33 by the lithography and the RIE.
[0078] Next, as shown in FIG. 17, the interconnection hole 34 is
filled with a plug 35 made of tungsten, for example, by a
combination of a blanket CVD method and etching or a selective CVD
method. Then, an Al alloy film 36, for example is deposited by a
sputtering method, for example, and the Al alloy film 36 is
processed so as to have an emitter electrode interconnection
pattern, a base electrode interconnection pattern and a collector
electrode interconnection pattern by the lithography and the RIE.
In this manner, a desired NPN type hetero-junction bipolar
transistor shown in FIG. 17 is manufactured. FIG. 21 shows
concentration distributions of various kinds of impurities and Ge
in the depth direction from the polycrystal Si film 31 to the
N.sup.+ region 12 of this hetero-junction bipolar transistor, i.e.,
concentration distributions taken along the line B-B in FIG. 17. A
portion 50 that is shown on the right-hand side of the peak of the
Ge concentration distribution curve in FIG. 21 corresponds to the
SiGe film 41.
[0079] FIG. 22 is a cross-sectional view of a main portion of a
hetero-junction bipolar transistor according to another embodiment
of the present invention. This hetero-junction bipolar transistor
comprises an SiGe film 44 instead of the SiGeC film 23 in the
aforementioned embodiment shown in FIGS. 17 and 19 and a laminated
film 43 composed of an SiGe film 41, an SiGe film 44 and the Si
film 24. A rest of arrangement is similar to that of FIGS. 17 and
19.
[0080] FIG. 23 shows stresses occurred in the hetero-junction
bipolar transistor according to the third reference example shown
in FIG. 6 and stresses occurred in the hetero-junction bipolar
transistor according to this embodiment of FIG. 22. The SiGe film
44 in the laminated film 43 is formed by omitting the addition of
SiCH.sub.6 gas from the raw material gas of the SiGeC film 23.
[0081] A portion extending from a point A to a point H in FIG. 23B
show a channel along which stresses were obtained. FIG. 23A shows
stresses that have been obtained along this channel. As shown in
FIG. 23A, a stress has a positive peak near the boundary between
the points F and G that are near the end edges of the opening 21 in
the SiO.sub.2 film 18. However, while a stress in the third
reference example is approximately 0.65.times.10.sup.-4
[N/.mu.m.sup.2], a stress in this embodiment is approximately
0.58.times.10.sup.-4 [N/.mu.m.sup.2], and hence a stress of about
11% can be decreased.
[0082] Also at the points B, C in the portion of the polycrystal
film on the SiO.sub.2 film 18 in the laminated films 38, 43,
stresses are decreased in this embodiment as compared with the
third reference example. On the other hand, from data from the
points D to F, it is to be understood that stress at the interface
between the Si substrate 14 and the laminated films. 38, 43 is
almost zero. As described above, FIG. 23 shows stresses in the
laminated film 43. However, since the stresses occurred in the
laminated films 42, 43 are considerably affected by the polycrystal
SiGe film 41 that adjoins the SiO.sub.2 film 18, it may be
considered that similar results to those of the laminated film 43
are obtained in the laminated film 42.
[0083] Accordingly, in the above-mentioned hetero-junction bipolar
transistor that uses the laminated films 42, 43 as the
hetero-junction base layer and the base deriving electrode, the
occurrence of the misfit dislocation in the hetero-junction base
layer can be suppressed, and hence the hetero-junction bipolar
transistor can be manufactured at a high yield. While the SiGe film
41 is used in the laminated film in the above-mentioned embodiment
shown in FIGS. 17 and 19, the present invention is not limited
thereto, and as shown in FIG. 24, an SiGeC film 45 may be used
instead of the SiGe film 41 and a laminated film 46 can be composed
of the SiGeC film 45, the SiGeC film 23 and the Si film 24 to form
the hetero-junction bipolar transistor. A rest of arrangement is
similar to that of FIGS. 17 and 19. This embodiment of FIG. 24 can
achieve similar effects to those of the above-mentioned
embodiment.
[0084] While the present invention is applied to the NPN type
hetero-junction bipolar transistor and the manufacturing method
thereof as set forth above, the present invention is not limited
thereto and can also be applied to a PNP type hetero-junction
bipolar transistor and a manufacturing method thereof. In that
case, N-type-impurities are introduced into the SiGeC film 23 and
the Si film 24, the SiGeC film 44 and the Si film 24. Moreover, the
present invention can also be applied to semiconductor devices
containing the hetero-junction bipolar transistor and other
semiconductor elements and manufacturing methods thereof.
[0085] While the laminated films 42, 43, 46 are used as the base
layer and the deriving electrodes of the hetero-junction bipolar
transistor as set forth above, the laminated films 42, 43, 46 may
be applied to other use, and the Si film 24 may not always be
contained in the laminated films 42, 43, 46 depending upon the use.
Furthermore, while the laminated films 42, 43, are formed by the
CVD method as described above, they may formed by other vapor phase
growth method than the CVD method other forming method than the
vapor phase growth method, example, a liquid phase growth
method.
* * * * *