U.S. patent application number 11/036463 was filed with the patent office on 2006-07-13 for gate oxide protected i/o circuit.
This patent application is currently assigned to Elite Semiconductor Memory Technology Inc.. Invention is credited to Yi-Heng Liu, Dar-Woei Wang.
Application Number | 20060152255 11/036463 |
Document ID | / |
Family ID | 36652659 |
Filed Date | 2006-07-13 |
United States Patent
Application |
20060152255 |
Kind Code |
A1 |
Wang; Dar-Woei ; et
al. |
July 13, 2006 |
Gate oxide protected I/O circuit
Abstract
An integrated circuit comprises a first input node and a second
input node, an output node; a first output transistor of a first
type and a second output transistor of a second type, and a first
clamping transistor of the second type and a second clamping
transistor of the second type. The first clamping transistor, the
first output transistor, the second clamping transistor, and the
second output transistor are coupled in series across a first power
supply terminal and a second power supply terminal. The first input
node is coupled to a gate of the first output transistor. The
second input node is coupled to a gate of the second output
transistor. The output node is coupled to a common node of the
first output transistor and the second clamping transistor. A gate
of the first clamping transistor is coupled to a first reference
voltage. A gate of the second clamping transistor is coupled to a
second reference voltage.
Inventors: |
Wang; Dar-Woei; (Hsinchu
County, TW) ; Liu; Yi-Heng; (Taipei City,
TW) |
Correspondence
Address: |
HOGAN & HARTSON L.L.P.
500 S. GRAND AVENUE
SUITE 1900
LOS ANGELES
CA
90071-2611
US
|
Assignee: |
Elite Semiconductor Memory
Technology Inc.
|
Family ID: |
36652659 |
Appl. No.: |
11/036463 |
Filed: |
January 13, 2005 |
Current U.S.
Class: |
327/112 |
Current CPC
Class: |
H03K 17/22 20130101;
H03K 19/00315 20130101 |
Class at
Publication: |
327/112 |
International
Class: |
H03B 1/00 20060101
H03B001/00 |
Claims
1. An integrated circuit comprising: a first input node and a
second input node; an output node; a first output transistor of a
first type and a second output transistor of a second type; and a
first clamping transistor of the second type and a second clamping
transistor of the second type, wherein the first type can be a PMOS
or an NMOS and the second type can respectively be an NMOS or a
PMOS, the first clamping transistor, the first output transistor,
the second clamping transistor, and the second output transistor
are coupled in series across a first power supply terminal and a
second power supply terminal, the first input node is coupled to a
gate of the first output transistor, the second input node is
coupled to a gate of the second output transistor, the output node
is coupled to a common node of the first output transistor and the
second clamping transistor, a gate of the first clamping transistor
is coupled to a first reference voltage, and a gate of the second
clamping transistor is coupled to a second reference voltage.
2. The circuit of claim 1, wherein the first input node and the
second input node provide the same logic signal.
3. The circuit of claim 1, wherein the first output transistor is a
PMOS transistor and the second output transistor, the first
clamping transistor, and the second clamping transistor are NMOS
transistors.
4. The circuit of claim 3, wherein the first reference voltage and
the second reference voltage are lower than a voltage provided by
the first power supply terminal and higher than a voltage provided
by the second power supply terminal, the first reference voltage
and the second reference voltage respectively remain substantially
the same voltage values.
5. The circuit of claim 4, wherein the first reference voltage is
higher than the second reference voltage.
6. The circuit of claim 3, wherein a substrate of the first
clamping transistor is coupled to a common node of the first
clamping transistor and the first output transistor.
7. The circuit of claim 3, wherein a voltage at the common node of
the first clamping transistor and the first output transistor is
not higher than the first reference voltage minus a threshold
voltage of the first clamping transistor; and a voltage at the
common node of the second clamping transistor and the second output
transistor is not higher than the second reference voltage minus a
threshold voltage of the second clamping transistor.
8. The circuit of claim 3, wherein the first power supply terminal
provides approximately 5V and the second power supply terminal
provides approximately 0V.
9. The circuit of claim 1, further comprising: a level shifter
coupled to output signals to the first input node and the second
input node, the level shifter coupled to a third power supply
terminal and a fourth power supply terminal.
10. The circuit of claim 9, further comprising: an internal circuit
coupled to output signals to the level shifter, the internal
circuit coupled to a fifth power supply terminal and a sixth power
supply terminal.
11. The circuit of claim 9, further comprising: a power-up circuit
to provide a voltage to the third power supply terminal; and a
detection circuit to detect a completion of a power-up stage.
12. The circuit of claim 11, wherein the power-up circuit comprises
a resister, a power-up stage transistor, an active stage
transistor, a switch transistor, a first protection circuit, and a
third power supply node; the resistor, the switch transistor, and
the first protection circuit are coupled in series across the first
power supply terminal and the second power supply terminal, a gate
of the switch transistor coupled to the detection circuit to
receive a switch signal; a first end of the power-up stage
transistor is coupled to the first power supply terminal, a second
end of the power-up stage transistor is coupled to the third power
supply node, a gate of the power-up stage transistor is coupled to
a common node of the resistor and the switch transistor; and a
first end of the active stage transistor is coupled to the first
power supply terminal, a second end of the active stage transistor
is coupled to the third power supply node and the second end of the
power-up transistor, a gate of the active stage transistor is
coupled to the first reference voltage.
13. The circuit of claim 12, wherein the power-up transistor and
the active stage transistor are NMOS transistors; a substrate and
the second end of the power-up stage transistor are coupled to each
other; and a substrate of the active stage transistor is coupled to
the second power supply terminal.
14. The circuit of claim 12, wherein the first protection circuit
comprises a first protection transistor and a second protection
transistor coupled in series.
15. The circuit of claim 14, wherein the first protection
transistor comprises an NMOS transistor and the second protection
transistor comprises a PMOS transistor; a drain of the first
protection transistor is coupled to the switch transistor, a gate
and the drain of the first protection transistor are coupled to
each other, a source of the first protection transistor is coupled
to a source of the second protection transistor, a substrate of the
first protection transistor is coupled to the second power supply
terminal; and the source and a substrate of the second protection
transistor are coupled to each other, a gate and a drain of the
second protection transistor are coupled to each other, the drain
of the second protection transistor is coupled to the second power
supply terminal.
16. The circuit of claim 12, further comprising: a second
protection circuit coupled to a common node of the resistor and the
switch transistor.
17. The circuit of claim 16, wherein the second protection circuit
comprises a third protection transistor and a fourth protection
transistor coupled in series; and a first end of the third
protection transistor is coupled to a first power supply terminal,
a second end of the third protection transistor is coupled to a
first end of the fourth protection transistor, gates of the third
protection transistor and the fourth protection transistor are
coupled to the first reference voltage, a second end of the fourth
protection transistor is coupled to the common node of the resistor
and the switch transistor.
18. The circuit of claim 9, wherein a voltage of the third power
supply terminal is provided by coupling to the common node of the
first clamping transistor and the first output transistor.
19. The circuit of claim 18, further comprising: a power-up circuit
to provide an intermediate voltage; a detection circuit to detect a
completion of a power-up stage; and a regulator to receive the
intermediate voltage and to generate the first reference voltage
and the second reference voltage; wherein the power-up circuit
comprises a resister, a power-up stage transistor, an active stage
transistor, a switch transistor, and a first protection circuit;
the resistor, the switch transistor, and the first protection
circuit are coupled in series across the first power supply
terminal and the second power supply terminal, a gate of the switch
transistor coupled to the detection circuit to receive a switch
signal; a first end of the power-up stage transistor is coupled to
the first power supply terminal, a second end of the power-up stage
transistor is coupled to the regulator, a gate of the power-up
stage transistor is coupled to a common node of the resistor and
the switch transistor; and a first end of the active stage
transistor is coupled to the first power supply terminal, a second
end of the active stage transistor is coupled to the regulator and
the second end of the power-up transistor, a gate of the active
stage transistor is coupled to the first reference voltage.
20. The circuit of claim 19, further comprising: a second
protection circuit coupled to a common node of the resistor and the
switch transistor, the second protection circuit comprising a third
protection transistor and a fourth protection transistor coupled in
series; wherein a first end of the third protection transistor is
coupled to a first power supply terminal, a second end of the third
protection transistor is coupled to a first end of the fourth
protection transistor, gates of the third protection transistor and
the fourth protection transistor are coupled to the first reference
voltage, a second end of the fourth protection transistor is
coupled to the common node of the resistor and the switch
transistor.
21. An integrated circuit comprising: a first input node and a
second input node; an output node; a first PMOS transistor; and a
first NMOS transistor, a second NMOS transistor, and a third NMOS
transistor, wherein the first NMOS transistor, the first PMOS
transistor, the second NMOS transistor, and the third NMOS
transistor are coupled in series across a first power supply
terminal and a second power supply terminal, the first input node
is coupled to a gate of the first PMOS transistor, the second input
node is coupled to a gate of the third NMOS transistor, the output
node is coupled to a common node of the first PMOS transistor and
the second NMOS transistor, a gate of the first NMOS transistor is
coupled to a first reference voltage, a gate of the second NMOS
transistor is coupled to a second reference voltage.
22. The circuit of claim 21, wherein a substrate of the first NMOS
transistor is coupled to a source of the first PMOS transistor; and
the first reference voltage and the second reference voltage are
lower than a voltage provided by the first power supply terminal
and higher than a voltage provided by the second power supply
terminal.
23. The circuit of claim 22, wherein the first reference voltage is
higher than the second reference voltage.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to an integrated circuit, and
more particularly to a gate oxide protected I/O circuit.
BACKGROUND
[0002] In order to save power, the core circuitry of a device, for
example a microprocessor, usually operates on a predetermined lower
voltage level, even though the device must communicate externally
using an input/output (I/O) voltage level which is higher than the
predetermined voltage used by the core of the device. For example,
a microprocessor chip may operate on logic levels of high (H) and
low (L) having voltage levels of 3.3 volts (V) and 0 V,
respectively, although the device may be connected to a 5 V power
rail for use in external communications. Typically, in such a
device, a level shifter converts the inner voltage levels of 0 V
and 3.3 V used by a microprocessor chip to the output voltage
levels of 0 V and 5 V. However, a voltage difference of 5V between
gates and drains/sources of output transistors may easily break
down the gate oxide and fail the device. As the technology is
advanced, the voltage levels will be lowered.
[0003] As shown in FIG. 1 using the above voltage system, a
conventional output buffer 100 comprises a PMOS transistor 130 and
an NMOS transistor 140 connected in series to drive an input/output
circuit. A source of the PMOS transistor 130 is connected to an
external power supply terminal 150 of 5V while a source of the NMOS
transistor 140 is connected to an external ground voltage 160 of
0V. The drains of PMOS transistor 130 and NMOS transistor 140 are
connected to an output node 120 to transmit an output signal. The
gates of PMOS transistor 130 is connected to a first input node 110
to receive a first input signal. The gate of NMOS transistor 140 is
connected to a second input node 115 to receive a second input
signal. When both the first input signal and the second input
signal of 0V (logic low) are applied, the PMOS transistor 130 turns
on and the NMOS transistor 140 turns off. The output buffer 100
outputs a signal of 5V (logic high). The voltage difference between
the gate and the drain/source of the PMOS transistor 130 is 5V.
When both the first input signal and the second input signal of 5V
(logic high) are applied, the PMOS transistor 130 turns off and the
NMOS transistor 140 turns on. The output buffer 100 outputs a
signal of 0V (logic low). The voltage difference between the gate
and the drain/source of the NMOS transistor 140 is 5V.
[0004] Physically, the electric field across the gate oxide is
required to be smaller than 5 MV/cm to avoid a gate oxide
breakdown. Assuming that gate oxide is 88.5 angstroms in a modem
semiconductor manufacturing process, a voltage difference of 5V
results in an electric field of 5.65 MV/cm across the gate oxide,
which exceeds the oxide breakdown voltage, resulting to a
destructive gate oxide breakdown.
[0005] One way to address this problem is to lower the voltage used
as the logic high value of the input signal high which in turns
lowers a voltage difference between the gate and the drain/source
of output transistors. Using this lower voltage logic high that
also lowers the voltage difference between the external power
supply connected to the source of the PMOS transistor 130 and the
logic high input signal provided to the gate of the PMOS transistor
130 prevents the PMOS transistor 130 from turning completely off.
Such a static current flowing from the external power terminal to
the external ground represents a constant leakage current and is
undesirable.
[0006] Another commonly used method to address this problem is to
use a "dual oxide" process. The internal logic uses thinner oxide
to operate at lower voltage, while the I/O circuitry uses thicker
oxide to operate at higher voltage. Such a method, however, will
add extra cost in production.
SUMMARY OF THE PREFERRED EMBODIMENTS
[0007] In the present invention, a circuit is designed to protect
I/O circuitry which operates at a relatively high voltage compared
to internal circuitry while still using a "single thin oxide"
technology to keep production costs low.
[0008] According to one embodiment of the present invention, an
integrated circuit comprises a first input node and a second input
node, an output node, a first output transistor of a first type and
a second output transistor of a second type, and a first clamping
transistor of the second type and a second clamping transistor of
the second type. The first clamping transistor, the first output
transistor, the second clamping transistor, and the second output
transistor are coupled in series across a first power supply
terminal and a second power supply terminal. The first input node
is coupled to a gate of the first output transistor. The second
input node is coupled to a gate of the second output transistor.
The output node is coupled to a common node of the first output
transistor and the second clamping transistor. A gate of the first
clamping transistor is coupled to a first reference voltage. A gate
of the second clamping transistor is coupled to a second reference
voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] A more complete understanding of the present invention can
be obtained by reference to the detailed description of embodiments
in conjunction with the accompanying drawings, which form part of
the disclosure. These drawings depict only a typical embodiment of
the invention and do not therefore limit its scope. They serve to
add specificity and details, in which:
[0010] FIG. 1 is a schematic diagram of a conventional output
circuit;
[0011] FIG. 2 is a schematic diagram of an embodiment of a gate
oxide protected I/O circuit;
[0012] FIG. 3A is a schematic diagram of another embodiment of the
gate oxide protected I/O circuit shown in FIG. 2, which further
includes a level shifter and an internal circuit;
[0013] FIG. 3B is a schematic diagram of another embodiment of the
gate oxide protected I/O circuit shown in FIG. 3A, where a power
supply of a level shifter is connected to point A;
[0014] FIG. 4A is a schematic diagram of an embodiment of a
power-up circuit and a detection circuit for generating a power
supply of the level shifter in FIG. 3A;
[0015] FIG. 4B is a schematic diagram of an embodiment of a
power-up circuit, a detection circuit, and a regulator for
generating a first reference voltage and a second reference voltage
in FIG. 3B;
[0016] FIG. 5A is a schematic diagram of another embodiment of the
power-up circuit shown in FIG. 4A, which includes a second
protection circuit;
[0017] FIG. 5B is a schematic diagram of another embodiment of the
power-up circuit shown in FIG. 4B, which includes a second
protection circuit.
DETAILED DESCRIPTION
[0018] Particularly preferred embodiments protect the gate oxide of
an I/O circuit by providing a lower voltage difference between the
gate and the drain or source. This is preferably accomplished in a
way that avoids persistent current flow in any of the transistors
of the I/O circuit.
[0019] As shown in FIG. 2, an exemplary embodiment of an output
circuit 200 includes a first input node 210, a second input node
220, an output node 230, a first output transistor 250, a second
output transistor 270, a first clamping transistor 240, and a
second clamping transistor 260. P-type transistors and N-type
transistors are available as possible first or second type
transistors in the output circuit. One or the other type of
transistor can be defined as the first type so long as the
definition is maintained throughout the example. The first output
transistor 250 is a first type transistor. The second output
transistor 270, the first clamping transistor 240, and the second
clamping transistor 260 are a second type transistor. The first
clamping transistor 240, the first output transistor 250, the
second clamping transistor 260, and the second output transistor
270 are connected in series across a first power supply terminal
290 and a second power supply terminal 295. The first input node
210 is connected to a gate of the first output transistor 250. The
second input node 220 is connected to a gate of the second output
transistor 270. The output node 230 is connected to a common node
of the first output transistor 250 and the second clamping
transistor 260. A gate of the first clamping transistor 240 is
connected to receive a first reference voltage (V.sub.REF1) from a
first reference voltage node 280. A gate of the second clamping
transistor 260 is connected to receive a second reference voltage
(V.sub.REF2) from a second reference voltage node 285.
[0020] A voltage of point A (V.sub.A), a common node of the first
output transistor 250 and the first clamping transistor 240, is
maintained approximately less than the difference between the first
reference voltage (V.sub.REF1) and a threshold voltage (V.sub.TH1)
of the first clamping transistor 240. That is to say,
V.sub.A.ltoreq.V.sub.REF1-V.sub.TH1. The first reference voltage is
preferably lower than a voltage of the first power supply terminal
290, which holds the first clamping transistor 240 in an ON state.
The voltage of point A is lower than the first reference voltage
which in turn is preferably lower than the voltage of the first
power supply terminal. As a result, the maximum voltage difference
across a gate oxide of the first output transistor 250 is
reduced.
[0021] Similarly, a voltage of point B (V.sub.B), a common node of
the second output transistor 270 and the second clamping transistor
260, is maintained approximately less than the difference between
the second reference voltage (V.sub.REF2) and a threshold voltage
(V.sub.TH2) of the second clamping transistor 260. That is to say,
V.sub.B.ltoreq.V.sub.REF2-V.sub.TH2. In a preferred embodiment, the
second reference voltage is lower than the maximum voltage of the
outside circuit which may be connected to the output node 230. The
maximum voltage of the outside circuit is usually the same as the
voltage of the first power supply terminal 290. Accordingly, the
voltage of point B is preferably lower than the maximum voltage
that the second clamping transistor 260 may receive from the output
node 230. As a result, the voltage difference across a gate oxide
of the second output transistor 270 is reduced.
[0022] In a preferred embodiment, the first output transistor 250
is a PMOS transistor (P1). The first clamping transistor 240, the
second clamping transistor 260, and the second output transistor
270 are NMOS transistors (N1, N2, and N3 respectively). The voltage
of the first power supply terminal 290 is approximately 5 Volts
(V). The voltage of the second power supply terminal 295 is
approximately 0V, ground voltage. The first reference voltage is
approximately 4.5V. The second reference voltage is approximately
3.3V. A voltage of a logic high and logic low signal for the first
input node 210 and the second input node 220 is approximately 4.2V
and 0V respectively. The threshold voltage of the NMOS transistors
240 and 260 is approximately 0.3V. Accordingly, the voltage of the
point A is maintained not to exceed approximately 4.2V which is
substantially the same as the voltage of logic high input. The
voltage of the point B is maintained not to exceed approximately
3.0V.
[0023] When the input signal is at logic high, the first input node
210 and the second input node 220 are connected to approximately
4.2V. Because the voltage of point A is maintained substantially
the same as the voltage of a logic high input signal, the source of
the first output transistor P1 is connected to approximately 4.2V.
The first output transistor P1 turns off. The source of the second
output transistor N3 is connected to ground. The gate of the second
output transistor 270 is connected to approximately 4.2V. The
second output transistor N3 turns on. The voltage of the output
signal is approximately 0V. The voltage difference across the gate
oxide of the second output transistor N3 is about 4.2V.
[0024] When the input signal is at logic low, the first input node
210 and the second input node 220 are connected to approximately
0V. Because the voltage of point A is maintained to be
substantially the same as the voltage of a logic high input signal,
the source of the first output transistor P1 is connected to
approximately 4.2V. The first output transistor P1 turns on. The
source of the second output transistor N3 is connected to ground.
The second output transistor N3 turns off. The voltage of the
output signal is approximately 4.2V. The voltage difference across
the gate oxide of the first output transistor P1 is about 4.2V.
[0025] Because of the first clamping transistor N1 and the value of
the first reference voltage, a stress on the gate oxide of the
first output transistor P1 is reduced and the gate oxide of
transistor P1 does not break down when the output is connected to a
high external voltage. Typically, to avoid a gate oxide breakdown,
an electronic field across the gate oxide is required to be smaller
than 5 MV/cm. Assuming a gate oxide thickness of 88.5 angstroms in
a present day semiconductor manufacturing process, a voltage
difference of 4.2V results in an electric field of 4.75 MV/cm
across the gate oxide, which is generally too low to cause gate
oxide breakdown.
[0026] The second clamping transistor N2 and the second reference
voltage maintain the voltage of point B below approximately 3V when
the output node 230 is connected to 5V. As a result, a stress on
the gate oxide of the second output transistor N3 is reduced to
avoid the gate oxide breakdown when transistor N3 is connected to a
high external voltage. A voltage difference of 3V results in an
electric field of 3.39 MV/cm across the gate oxide, which is
generally too low to cause gate oxide breakdown.
[0027] In one embodiment, substrates of the first output transistor
250, the second output transistor 270, the first clamping
transistor 240, and the second clamping transistor 260 are
connected to their respective default voltages. The default voltage
for the substrate of a PMOS transistor is the voltage of the first
power supply terminal 290 while the default voltage for the
substrate of an NMOS transistor is the voltage of the second power
supply terminal 295.
[0028] In another embodiment, a substrate of the first clamping
transistor 240 is connected to a common node (point A) of the first
clamping transistor 240 and the first output transistor 250 rather
than the substrate of the transistor 240 being connected to a
default voltage. Accordingly, the threshold voltage of the first
clamping transistor 240 is smaller than that of the first clamping
transistor 240 in the above embodiment. The voltage at point A
consequently increases which may facilitate the output signal to be
recognized as logic high.
[0029] FIG. 3A shows another embodiment of an integrated circuit
300 which includes a level shifter 310 and an internal circuit 340.
The internal circuit 340 outputs signals to a level shifter 310
which in turn outputs signals to the first input node 210 and the
second input node 220. The level shifter 310 is connected to a
third and a fourth power supply terminal 320 and 330. The internal
circuit 340 is connected to a fifth and a sixth power supply
terminal 350 and 360 (V.sub.SS2).
[0030] In one embodiment, the voltage provided by the first power
supply terminal (V.sub.DD1) to the output circuit is preferably
larger than the voltage provided by the third power supply terminal
(V.sub.DD2) to the level shifter 310, which in turn is preferably
larger than the voltage provided by the fifth power supply terminal
(V.sub.CC) to the internal circuit 340. The second power supply
terminal (V.sub.SS1), the third power supply terminal (V.sub.SS2),
and the fifth power supply terminal (V.sub.SS2) are connected to
ground. The first reference voltage (V.sub.REF1) is arranged to
make the voltage of point A (V.sub.A) substantially the same as the
voltage provided by the third power supply terminal (V.sub.DD2).
For example, the first reference voltage is approximately 4.5V.
Both the voltage provided by the third power supply and the voltage
of point A (V.sub.A) are maintained approximately 4.2V. As a
result, the first output transistor 250 can be completely turned
off when the input signal is at logic high. The first reference
voltage (V.sub.REF1) is preferably higher than the voltage provided
by the third power supply terminal (V.sub.DD2) and preferably lower
than the voltage provided by the first power supply terminal
(V.sub.DD1). The second reference voltage (V.sub.REF2) is
preferably lower than the first reference voltage (V.sub.REF1) to
limit hot carriers which may reduce the lifetime of the second
output transistor 270. Because the voltage provided by the fifth
power supply terminal (V.sub.CC) is lower than the first reference
voltage (V.sub.REF1), the fifth power supply terminal 350 can
provide the second reference voltage (V.sub.REF2).
[0031] In another embodiment as shown in FIG. 3B, a voltage of the
third power supply terminal is provided by coupling a power supply
line 325 of the level shifter 310 to point A, the common node of
the first clamping transistor 240 and the first output transistor
250. That is to say, the level shifter is provided with a voltage
substantially the same as the voltage of point A (V.sub.A). As a
result, the first output transistor 250 can be completely turned
off when the input signal is at logic high.
[0032] When an external power supply 290 (V.sub.DD1) is applied,
the related power supply voltages of the integrated circuit will go
through a power-up sequence and then remain stable while the
circuit is active. Taking the embodiment shown in FIG. 3A as an
example, the voltage of the third power supply terminal (V.sub.DD2)
is generated from the voltage of the first power supply terminal
(V.sub.DD1). The voltages of the first power supply terminal
(V.sub.DD1) and the third power supply terminal (V.sub.DD2) are
used to generate the first reference voltage (V.sub.REF1). When the
external power supply is applied, the voltage of the first power
supply terminal (V.sub.DD1), for example, increases from 0V to 5V
and then remains stable. Meanwhile, the voltage of the first power
supply terminal (V.sub.DD1) raises the voltage of the third power
supply terminal (V.sub.DD2), for example, from 0V to 4.2V, which
then remains stable. Similarly, the voltages of the first power
supply terminal (V.sub.DD1) and the third power supply terminal
(V.sub.DD2) raise the first reference voltage (V.sub.REF1), for
example, from 0V to 4.5V, which then remains stable. When the first
reference voltage (V.sub.REF1) reaches a predetermined value, the
integrated circuit switches from power-up to active operation.
While the circuit is active, the first reference voltage
(V.sub.REF1) feeds back to generate the voltage of the third power
supply terminal (V.sub.DD2).
[0033] Taking the embodiment shown in FIG. 3B as an example, an
intermediate voltage is generated from the voltage of the first
power supply terminal (V.sub.DD1). The voltages of the first power
supply terminal (V.sub.DD1) and the intermediate voltage are used
to generate the first reference voltage (V.sub.REF1) and the second
reference voltage (V.sub.REF2).
[0034] In order to generate the voltage of the third power supply
terminal (V.sub.DD2) for the level shifter 320 in FIG. 3A during
the power-up stage and the active stage, another embodiment of an
integrated circuit includes a power-up circuit and a detection
circuit 470 as shown in FIG. 4A and 5A. For the output circuit
shown in FIG. 3B, because the power supply line 325 of the level
shifter 310 is directly connected to the point A, it is not
necessary to generate a separate voltage for the power supply of
the level shifter 310. Nonetheless, in order to generate the first
reference voltage (V.sub.REF1) and the second reference voltage
(V.sub.REF2) for the output circuit in FIG. 3B, another embodiment
of an integrated circuit including a power-up circuit, a detection
circuit 470, and a regulator 480 is shown in FIG. 4B and 5B.
[0035] As shown in FIG. 4A, the power-up circuit contains a
resistor 410, a switch transistor 420, a power-up stage transistor
430, an active stage transistor 440, a first protection circuit
450, and a third power supply node 460. The resistor 410, the
switch transistor 420, and the first protection circuit 450 are
connected in series across the first power supply terminal 290 and
the second power supply terminal 295. A gate of the switch
transistor 420 is connected to the detection circuit 470 to receive
a switch signal.
[0036] A first end of the power-up stage transistor 430 is
connected to the first power supply terminal 290. A second end of
the power-up stage transistor 430 is connected to the third power
supply node 460. A gate of the power-up stage transistor 430 is
connected to a common node of the resistor 410 and the switch
transistor 420. A first end of the active stage transistor 440 is
connected to the first power supply terminal 290. A second end of
the active stage transistor 440 is connected to the third power
supply node 460 and the second end of the power-up stage transistor
430. A gate of the active stage transistor 440 is connected to the
first reference voltage node 280.
[0037] During power-up, the voltage of the third power supply
terminal (V.sub.DD2) is generated from the power-up stage
transistor 430. The voltage of the third power supply terminal
(V.sub.DD2) is approximately the same as the difference between the
voltage of the first power supply terminal (V.sub.DD1) and a
threshold voltage of the power-up stage transistor 430. The voltage
of the third power supply terminal (V.sub.DD2) further contributes
the generation of the first reference voltage (V.sub.REF1). Upon
detecting that the first reference voltage (V.sub.REF1) increases
to a predetermined value, the detection circuit 470 sends a switch
signal to turn on the switch transistor 420. A voltage of point C
(V.sub.C), that is a common node of the resistor 410, the power-up
stage transistor 430 and the switch transistor 420, significantly
drops to turn off the power-up stage transistor 430. The voltage of
the third power supply terminal (V.sub.DD2) is then generated from
the active stage transistor 440 after the first reference voltage
(V.sub.REF1) has reached a predetermined value.
[0038] To protect the gate oxide of the power-up stage transistor
430 from breakdown, the voltage of point C preferably is slightly
higher than the voltage of the second power supply terminal
(V.sub.SS1). The first protection circuit 450 having a first
protection transistor 452 and a second protection transistor 454
can increase the voltage of point C (V.sub.C) to avoid gate oxide
breakdown. In addition, when the switch transistor 420 turns on, a
current may flow from the first power supply terminal (V.sub.DD1)
to the second power supply terminal (V.sub.SS1) through the
resistor 410, the switch transistor 420, and the protection circuit
450. The resistor 410 preferably has a large resistance to limit
current flow and power dissipation.
[0039] In one embodiment, the switch transistor 420, the power-up
stage transistor 430, the active stage transistor 440, and the
first protection transistor 452 are NMOS transistors. The second
protection transistor 454 is a PMOS transistor. Drains of the
power-up stage transistor 430 and the active stage transistor 440
are connected to the first power supply terminal 290 (V.sub.DD1).
Sources of the power-up stage transistor 430 and the active stage
transistor 440 are connected to the third power supply node 460
(V.sub.DD2). The gate of the active stage transistor 440 is
connected to the first reference signal node 280 (V.sub.REF1). A
substrate and the source of the power-up stage transistor 430 are
connected together. The gate of the power-up stage transistor 430
is connected to the resistor 410 and a drain of the switch
transistor 420. A substrate of the switch transistor 420 is
connected to the second power supply terminal (V.sub.SS1). A drain
and a gate of the first protection transistor 452 are connected to
a source of the switch transistor 420. A substrate of the first
protection transistor 452 is connected to the second power supply
terminal (V.sub.SS1). A source of the first protection transistor
452 is connected to a source and a substrate of the second
protection transistor 454. A gate and a drain of the second
protection transistor 454 are connected to the second power supply
terminal (V.sub.SS1).
[0040] FIG. 5A shows another embodiment of a power-up circuit for
the level shifter 320 in FIG. 3A, which further includes a second
protection circuit 510 to protect the gate oxide of the power-up
transistor 430 from breakdown. The second protection circuit 510
has a third protection transistor 520 and a fourth protection
transistor 530 connected in series to increase the voltage of point
C (V.sub.C). A first end of the third protection transistor 520 is
connected to a first power supply terminal. A second end of the
third protection transistor 520 is connected to a first end of the
fourth protection transistor 530. Gates of the third protection
transistor 520 and the fourth protection transistor 530 are
connected to the first reference voltage (V.sub.REF1). A second end
of the fourth protection transistor 530 is connected to the common
node of the resistor 410 and the switch transistor 420.
[0041] In order to generate the first reference voltage
(V.sub.REF1) and the second reference voltage (V.sub.REF2) for the
output circuit in FIG. 3B, another embodiment of the integrated
circuit includes a power-up circuit, a detection circuit 470, and a
regulator 480 as shown in FIG. 4B and 5B. The second ends of the
power-up stage transistor 430 and the active stage transistor 440
are connected to an input end of the regulator 480. The regulator
480 outputs the first reference voltage (V.sub.REF1) and the second
reference voltage (V.sub.REF2). The power-up circuit and the
detection circuit 470 in FIG. 4B and 5B can be respectively the
same as those in FIG. 4A and 5A.
[0042] Although the invention has been described in terms of
exemplary embodiments, it is not limited thereto. The described
embodiment is to be considered in all respects only as illustrative
and not as restrictive. The present invention may be embodied in
other specific forms without departing from its essential
characteristics. The scope of the invention, therefore, is
indicated by the appended claims rather than by the foregoing
description. All changes which come within the meaning and range of
the equivalents of the claims are to be embraced within their
scope.
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