U.S. patent application number 11/364671 was filed with the patent office on 2006-07-06 for flash memory device and method for fabricating the same, and programming and erasing method thereof.
This patent application is currently assigned to Anam Semiconductor. Invention is credited to Sang Bum Lee.
Application Number | 20060146632 11/364671 |
Document ID | / |
Family ID | 36640228 |
Filed Date | 2006-07-06 |
United States Patent
Application |
20060146632 |
Kind Code |
A1 |
Lee; Sang Bum |
July 6, 2006 |
Flash memory device and method for fabricating the same, and
programming and erasing method thereof
Abstract
A flash memory device of SONOS structure and a method for
fabricating the same, and programming and erasing operation
methods, to improve reliability such as endurance and retention,
are disclosed, which includes a first conductive type semiconductor
substrate; an ONO layer on the semiconductor substrate; a first
control gate on the ONO layer; second and third control gates on
the ONO layer at both sides of the first control gate; and source
and drain regions in the surface of the semiconductor substrate at
both sides of the second and third control gates.
Inventors: |
Lee; Sang Bum; (Incheon,
KR) |
Correspondence
Address: |
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER;LLP
901 NEW YORK AVENUE, NW
WASHINGTON
DC
20001-4413
US
|
Assignee: |
Anam Semiconductor
|
Family ID: |
36640228 |
Appl. No.: |
11/364671 |
Filed: |
March 1, 2006 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10879722 |
Jun 30, 2004 |
|
|
|
11364671 |
Mar 1, 2006 |
|
|
|
Current U.S.
Class: |
365/222 ;
257/E21.21; 257/E21.423; 257/E29.309 |
Current CPC
Class: |
G11C 16/0475 20130101;
H01L 29/40117 20190801; H01L 29/7923 20130101; H01L 29/66833
20130101; H01L 29/792 20130101; H01L 29/513 20130101 |
Class at
Publication: |
365/222 |
International
Class: |
G11C 7/00 20060101
G11C007/00 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 23, 2004 |
KR |
P2004-28282 |
Claims
1. A flash memory device comprising: a first conductive type
semiconductor substrate; an ONO layer on the semiconductor
substrate; a first control gate on the ONO layer; second and third
control gates on the ONO layer at both sides of the first control
gate; and source and drain regions in the surface of the
semiconductor substrate at both sides of the second and third
control gates.
2. The flash memory device of claim 1, further comprising an
insulating layer to insulate the first control gate from the second
and third control gates.
3. The flash memory device of claim 1, further comprising: a
planarization insulating layer on an entire surface of the
semiconductor substrate, and having respective contact holes in the
first, second and third control gates and the source and drain
regions; and a word line, first and second control lines, and first
and second bit lines respectively connected with the first, second
and third control gates and the source and drain regions through
the respective contact holes.
4-16. (canceled)
Description
[0001] This application claims the benefit of the Korean
Application No. P2004-28282 filed on Apr. 23, 2004, which is hereby
incorporated by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a flash memory device, and
more particularly, to a flash memory device having an SONOS
(Polysilicon-Oxide-Nitride-Oxide-Semiconductor) structure and a
method for fabricating the same, and programming and erasing
methods thereof, to improve reliability such as endurance and
retention.
[0004] 2. Discussion of the Related Art
[0005] A typical example of a nonvolatile memory device, in which
data is not erased even though a voltage is not applied, is EEPROM
(Electrically Erasable Programmable Read Only Memory). Generally,
the EEPROM takes a scheme using a floating gate-type cell. With
rapid development of high-integration device, it necessarily
requires the decrease in a size of the floating gate-type cell
according to the related art. However, it is impossible to decrease
the cell size since it requires a high voltage on programming and
erasing modes and it is difficult to obtain the margin of process
for defining tunneling. In this reason, various nonvolatile memory
devices such as SONOS, FeRAM, SET and NROM have been studied
actively as the substitute for the floating gate-type cell. Among
them, SONOS cell has attracted great attentions as the next
nonvolatile memory device, which can substitute for the stacked
floating gate-type cell.
[0006] Hereinafter, a related art SONOS-type flash memory device
will be described with reference to the accompanying drawings. FIG.
1 is a cross-sectional view illustrating a unit cell of a related
art SONOS-type flash memory device.
[0007] As shown in FIG. 1, the SONOS-type flash memory device
according to the related art includes a p-type semiconductor
substrate 11, an ONO layer 18, a control gate 15, and source and
drain regions 16 and 17. At this time, the ONO layer 18 is formed
in a method of sequentially stacking a first oxide layer 12, a
nitride layer 13 and a second oxide layer 14. Then, the control
gate 15 is formed on the ONO layer 18, and the source and drain
regions 16 and 17 are formed in a method of implanting highly doped
n-type impurity ions into the surface of the semiconductor
substrate 11 at both sides of the control gate 15. At this time,
the first oxide layer 12 acts as a tunneling oxide layer, and the
nitride layer 13 acts as a memory layer by controlling a threshold
voltage Vth by charging electric charge to a trap site or
discharging the electric charge. Also, the second oxide layer 14
acts as a blocking oxide layer preventing loss of the electric
charge.
[0008] In the aforementioned SONOS-type flash memory device
according to the related art, a programming operation uses a CHEI
(Channel Hot Electron Injection) method, and an erasing operation
uses an HHI (Hot Hole Injection) method to remove injected
electrons.
[0009] On the programming operation, a predetermined positive (+)
voltage is applied to the drain region 17 and the control gate 15,
and the source region 16 and the semiconductor substrate (body) are
ground. Under this condition, according as a bias is applied,
channel electrons are accelerated by a lateral electric field
formed from the source region 16 to the drain region 17, whereby
the channel electrons become hot electrons around the drain region
17. Also, the hot electrons jump over a potential barrier of the
first oxide layer 12, and are locally trapped to a trap level of
the nitride layer 13 around the drain region 17, thereby increasing
the threshold voltage. This programming method is referred to as
CHEI (Channel Hot Electron Injection).
[0010] On the erasing operation, a predetermined positive (+)
voltage is applied to the drain region 17, and a predetermined
negative (-) voltage is applied to the control gate 15. Also, the
source region 16 and the semiconductor substrate (body) 11 are
ground. Under this condition, according as a bias is applied, a
depletion region is formed in the n-type drain region 17 by a high
electric field formed in an overlap area between the drain region.
17 and the control gate 15. In the depletion region, pairs of
electron and hole are generated by band to band tunneling. Then,
the electron escapes to the n-type region, and the hole is
accelerated by a lateral electric field of the depletion region,
whereby the hole is changed to a hot hole. The hot hole jumps over
an energy barrier between the first oxide layer 12 and the
semiconductor substrate 11, injected and trapped to a valance band
of the nitride layer 13, thereby performing the erasing operation
lowing the threshold voltage. This erasing method is referred to as
HHI (Hot Hole Injection).
[0011] Also, the aforementioned SONOS-type flash memory device
records 2-bit data in one cell. That is, the programming operation
of the related art SONOS-type flash memory device uses the CHEI
(Channel Hot Electron Injection) method, and the erasing operation
thereof uses the HHI (Hot Hole Injection) method. By applying the
voltage of the aforementioned condition, the electron is trapped to
the nitride layer 13 around the drain region 17, thereby storing
1-bit data. Then, a predetermined positive (+) voltage is applied
to the source region 16 and the control gate 15, and the drain
region 17 and the semiconductor substrate (body) are ground,
whereby hot electrons are generated around the source region 16.
The hot electrons jump over the potential barrier of the first
oxide layer 12, and are trapped to the nitride layer 13 around the
source region 16, thereby storing 1-bit data.
[0012] In the programming and erasing operations, if the electron
and hole are shallowly trapped to the nitride layer 13, program and
erase cycling becomes low. Accordingly, the technology for
overcoming this problem has been published in IEDM document (Novel
Operation Schemes to Improve Device Reliability in a Localized
Trapping Storage SONOS-Type Flash Memory, 2003).
[0013] On the programming operation, when the hot electrons jump
over the potential barrier of the first oxide layer 12, and are
trapped to the nitride layer 13 around the drain region 17, some of
the hot electrons are deeply trapped to the nitride layer 13, and
the other hot electrons are shallowly trapped to the nitride layer
13. Among them, the hot electrons shallowly trapped to the nitride
layer 13 escape during a storage period due to a damage of the
first oxide layer generated by the program and erase cycling,
thereby generating loss of the electric charge.
[0014] According to IEDM document published in 2003, it is proposed
to carry out an electrical anneal after Hot Electron Injection of
the programming operation or after Hot Hole Injection of the
erasing operation, to improve over-erase in state of the low
threshold voltage, and to prevent loss of the electric charge in
state of the high threshold voltage. On the erasing operation,
after hole injection, the electron and hole are recombined in the
erasing electrical anneal. On the programming operation, after
electron injection, the electron shallowly trapped to the nitride
layer is removed, and the electron deeply trapped to the nitride
layer remains by the programming electrical anneal. In the erasing
electrical anneal, as shown in FIG. 1, the source region 16 and the
drain region 17 are ground, and the pulse (10 ms) of 10V is applied
to the control gate 15. In the programming electrical anneal, the
source region 16 and the drain region 17 are ground (0V), and the
pulse (10 ms) of -4V is applied to the control gate 15.
[0015] However, the aforementioned IEDM document has the following
problems.
[0016] On the programming operation, the electrons shallowly
trapped to the nitride layer are removed by the programming
electrical anneal, thereby decreasing loss of the electric charge.
After programming, it is impossible to remove the hopping electrons
moved (spread) to a lateral side by the programming electrical
anneal. Accordingly, even in case of Hot Hole Injection in a large
amount on the erasing operation, the trapped electrons are not
removed completely, thereby degrading reliability. Especially, when
separately programming data to the nitride layer around the source
region and the drain region, for example, programming 2-bit data in
one cell, the aforementioned problem becomes more serious.
SUMMARY OF THE INVENTION
[0017] Accordingly, the present invention is directed to a flash
memory device and a method for fabricating the same, and
programming and erasing methods that substantially obviates one or
more problems due to limitations and disadvantages of the related
art.
[0018] An object of the present invention is to provide a flash
memory device and a method for fabricating the same, and
programming and erasing methods, to completely remove hopping
electrons moved (spread) to a lateral direction, after
programming.
[0019] Additional advantages, objects, and features of the
invention will be set forth in part in the description which
follows and in part will become apparent to those having ordinary
skill in the art upon examination of the following or may be
learned from practice of the invention. The objectives and other
advantages of the invention may be realized and attained by the
structure particularly pointed out in the written description and
claims hereof as well as the appended drawings.
[0020] To achieve these objects and other advantages and in
accordance with the purpose of the invention, as embodied and
broadly described herein, a flash memory device includes a first
conductive type semiconductor substrate; an ONO layer on the
semiconductor substrate; a first control gate on the ONO layer;
second and third control gates on the ONO layer at both sides of
the first control gate; and source and drain regions in the surface
of the semiconductor substrate at both sides of the second and
third control gates.
[0021] Furthermore, the flash memory device includes an insulating
layer to insulate the first control gate from the second and third
control gates.
[0022] Furthermore, the flash memory device includes a
planarization insulating layer on an entire surface of the
semiconductor substrate, and having respective contact holes in the
first, second and third control gates and the source and drain
regions; and a word line, first and second control lines, and first
and second bit lines respectively connected with the first, second
and third control gates and the source and drain regions through
the respective contact holes.
[0023] In another aspect, a method for fabricating a flash memory
device includes the steps of forming an ONO layer having a stacked
structure of a first oxide layer, a nitride layer and a second
oxide layer on a semiconductor substrate on which an active region
is defined; forming a first control gate on the ONO layer; forming
an insulating layer on the surface of the first control gate;
forming second and third control gates on the ONO layer at both
sides of the first control gate; and forming source and drain
regions on the semiconductor substrate at both sides of the second
and third control gates.
[0024] At this time, the second oxide layer is formed in a method
of oxidizing the nitride layer.
[0025] Also, the insulating layer is formed in a method of
oxidizing the exposed surface of the first control gate.
[0026] Also, the source and drain regions are formed in a method of
implanting highly doped n-type impurity ions by using the first,
second and third control gates as a mask.
[0027] Furthermore, the method includes the steps of forming a
planarization insulating layer on the entire surface of the
semiconductor substrate including the first, second and third
control gates; forming respective contact holes by selectively
removing the planarization insulating layer and the ONO layer to
expose the first, second and third control gates and the source and
drain regions; and forming a word line, first and second control
lines, and first and second bit lines respectively connected with
the first, second and third control gates and the source and drain
regions through the respective contact holes.
[0028] At this time, the planarization insulating layer is formed
of BPSG.
[0029] In another aspect, a programming method of a flash memory
device of SONOS structure, the flash memory device including second
and third control gates at both sides of a first control gate,
source and drain regions in a surface of a semiconductor substrate
at both sides of the second and third control gates, and ONO layers
between the control gates and the semiconductor substrate, includes
a first step of applying a high voltage pulse to the first and
third control gates, and trapping hot electrons to the ONO layer
around the drain region; and a second step of annealing the trapped
electrons by applying a high voltage pulse to the first control
gate.
[0030] In the first step, 0V is applied to the source region, a
voltage over a threshold voltage is applied to the second control
gate, a voltage pulse of 10V or more is applied to the first and
third control gates, and a voltage of 4V or more is applied to the
drain region.
[0031] In the second step, 0V is applied to the source and drain
region, a voltage of -4V is applied to the second and third control
gates, and a voltage pulse of -10V is applied to the first control
gate.
[0032] Furthermore, the method includes a third step of trapping
hot electrons to the ONO layer around the source region by applying
a high voltage pulse to the first and second control gates.
[0033] In another aspect, an erasing method of a flash memory
device of SONOS structure, the flash memory device including second
and third control gates at both sides of a first control gate,
source and drain regions in a surface of a semiconductor substrate
at both sides of the second and third control gates, and ONO layers
between the control gates and the semiconductor substrate, includes
a first step of injecting a hole to the ONO layer around the source
or drain region by applying a negative voltage to the second or
third control gate; and a second step of annealing the injected
hole applying a positive high voltage pulse to the first control
gate, and applying a negative high voltage pulse to the second and
third control gates.
[0034] In the first step, a voltage over 0V or 5V is applied to the
source or drain region, a voltage over a threshold voltage is
applied to the second or third control gate, and a voltage pulse of
-3V or more is applied to the first/third or second control
gate.
[0035] In the second step, 0V is applied to the source and drain
regions, a voltage pulse of 10V is applied to the second and third
control gates, and a voltage pulse (several tens Ms) of -10V is
applied to the first control gate, thereby removing electrons moved
to a lateral side.
[0036] It is to be understood that both the foregoing general
description and the following detailed description of the present
invention are exemplary and explanatory and are intended to provide
further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0037] The accompanying drawings, which are included to provide a
further understanding of the invention and are incorporated in and
constitute a part of this application, illustrate embodiment(s) of
the invention and together with the description serve to explain
the principle of the invention. In the drawings:
[0038] FIG. 1 is a cross-sectional view illustrating a related art
SONOS-type flash memory device;
[0039] FIG. 2 is a cross-sectional view illustrating a flash memory
device according to the present invention; and
[0040] FIG. 3A to FIG. 3H are cross-sectional views illustrating
the fabrication process of a flash memory device according to the
present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0041] Reference will now be made in detail to the preferred
embodiments of the present invention, examples of which are
illustrated in the accompanying drawings. Wherever possible, the
same reference numbers will be used throughout the drawings to
refer to the same or like parts.
[0042] Hereinafter, a flash memory device and a method for
fabricating the same, and programming and erasing methods will be
described with reference to the accompanying drawings.
[0043] FIG. 2 is a cross-sectional view illustrating a flash memory
device according to the present invention. In the flash memory
device according to the present invention, as shown in FIG. 2, an
ONO layer 28 is formed on a p-type semiconductor substrate 21,
wherein the ONO layer 28 is formed by sequentially stacking a first
oxide layer 22, a nitride layer 23, and a second oxide layer 24.
Then, a first control gate 25 is formed on the ONO layer 28, and
second and third control gates 29 and 30 are formed on the ONO
layer 28 at both sides of the first control gate 25. After that,
source and drain regions 26 and 27 are formed in the surface of the
p-type semiconductor substrate 21 at both sides of the second and
third control gates 29 and 30 by implantation of n-type impurity
ions.
[0044] At this time, the first control gate 25 is isolated from the
second and third control gates 29 and 30 by a third oxide layer 31.
Then, a planarization insulating layer 32 is formed on an entire
surface of the semiconductor substrate 21 including the first,
second and third control gates 25, 29 and 30. Also, contact holes
are respectively formed in the first, second and third control
gates 25, 29 and 30 and the source and drain regions 26 and 27. In
this state, a word line W/L and first and second control lines CL1
and CL2 are connected with the first, second and third control
gates 25, 29 and 30 through the respective contact holes. Also, the
source and drain regions 26 and 27 are connected with a first bit
line BL1 and a second bit line BL2.
[0045] Also, the first oxide layer 22 acts as a tunneling oxide
layer. The nitride layer 23 acts as a memory layer to charge the
electric charge in a trap site, or to discharge the electric
charge, whereby the nitride layer 23 has a memory function by
controlling a threshold voltage Vth. Meanwhile, the second oxide
layer 24 acts as a blocking oxide layer to prevent loss of the
electric charge.
[0046] A method for fabricating the aforementioned flash memory
device according to the present invention will be described as
follows. FIG. 3A to FIG. 3H are cross-sectional views illustrating
the fabrication process of the flash memory device according to the
present invention.
[0047] As shown in FIG. 3A, a p-type semiconductor substrate 21 is
defined as a field region and an active region. Then, a field oxide
layer (not shown) is formed in the field region of the p-type
semiconductor substrate 21, and a buffer oxide layer 33 is formed
on the p-type semiconductor substrate 21. Also, the process for ion
implantation is progressed to form a well region (not shown) in the
active region of the semiconductor substrate 21 and to control a
threshold voltage.
[0048] Referring to FIG. 3B, after removing the buffer oxide layer
33, a first oxide layer 22, a nitride layer 23 and a second oxide
layer 24 are sequentially deposited on an entire surface of the
semiconductor substrate 21 to form an ONO layer 28, wherein the
first oxide layer 22 acts as a tunneling insulating layer, the
nitride layer 23 locally traps electrons, and the second oxide
layer 24 acts as a blocking layer. Then, a first polysilicon layer
25a is formed on the ONO layer 28. At this time, the second oxide
layer 24 may be formed in a method of depositing an oxide layer by
CVD, or oxidizing the nitride layer 23.
[0049] As shown in FIG. 3C, a photosensitive layer (not shown) is
formed on the first polysilicon layer 25a, and then the exposure
and development process using a mask is carried out thereto,
whereby the first polysilicon layer 25a is selectively removed to
form a first control gate 25. Thereafter, the photosensitive layer
is removed. After patterning the first control gate 25, the
cleaning process is carried out.
[0050] After that, as shown in FIG. 3D, the exposed surface of the
first control gate 25 is oxidized, thereby forming an oxide layer
31 covering the side portions and the upper surface of the first
control gate 25. Then, as shown in FIG. 3E, a second polysilicon
layer (not shown) is formed on the entire surface of the
semiconductor substrate 21 including the oxide layer 31 and the
first control gate 25, and then the anisotropic etching process
(etch-back process) is carried out, thereby removing the second
polysilicon layer, and forming second and third control gates 29
and 30 on the ONO layer 28 in the side portions of the oxide layer
31 at both sides of the first control gate 25.
[0051] Referring to FIG. 3F, highly doped n-type impurity ions are
implanted into the semiconductor substrate 21 by using the first,
second and third control gates 25, 29 and 30 as a mask, thereby
forming source and drain regions 26 and 27 in the surface of the
semiconductor substrate 21 at the side portions of the second and
third control gates.
[0052] As shown in FIG. 3G, a planarization insulating layer 32 of
BPSG is deposited on the entire surface of the semiconductor
substrate 21 including the first, second and third control gates
25, 29 and 30. Then, as shown in FIG. 3H, the planarization
insulating layer 32 and the ONO layer 28 are selectively removed to
expose the first, second and third control gates 25, 29 and 30 and
the source and drain regions 26 and 27 by photolithography, thereby
forming contact holes. After that, a metal layer is deposited on
the entire surface of the semiconductor substrate, and selectively
removed, whereby a word line WL and first, second control lines CL1
and CL2 and first and second bit lines BL1 and BL2 are respectively
connected with the first, second and third control gates 25, 29 and
30, and the source region 26 and the drain regions 27 through the
respective contact holes.
[0053] Hereinafter, programming/erasing and reading operations of
the aforementioned flash memory device will be described in
detail.
[0054] On the data programming operation in the flash memory
device, programming and programming electrical anneal are
repetitively performed. That is, 0V is applied to the first bit
line BL1, a voltage over the threshold voltage is applied to the
first control line CL1, a voltage pulse (several tens .mu.s) over
10V is applied to the word line W/L and the second control line
CL2, and a voltage over 4V is applied to the second bit line BL2,
whereby channel electrons are accelerated by a lateral electric
field formed from the source region 26 to the drain region 27,
thereby generating hot electrons around the drain region 27. The
hot electrons jump over the potential barrier of the first oxide
layer 22, and then the hot electrons are locally trapped to a trap
level of the nitride layer 23 around the drain region 27.
[0055] Also, the programming electrical anneal is performed to trap
electrons to the nitride layer 23, and to remove the electrons
moved to the lateral side among the trapped electrons. That is, 0V
is applied to the first and second bit lines BL1 and BL2, the
voltage pulse (several tens .mu.s) of -4V is applied to the second
control line CL2, and the voltage pulse (several tens ms) of -10V
is applied to the word line W/L, so that the electrons moved to the
lateral side are removed. At this time, even if the voltage pulse
(several tens ms) of -10V is applied to the word line W/L, it is
possible to remove only the electrons moved to the lateral side
without the effect on the electrons trapped to the nitride layer 23
around the drain region 27, as shown in FIG. 2, since the voltage
pulse of -4V is applied to the third control gate 30.
[0056] As described above, to program 2-bit data in a unit cell, it
is required to trap the electrons to the insulating layer 23 around
the drain region 27, to apply the voltage over 4V to the first bit
line BL1, to apply the voltage over the threshold voltage to the
second control line CL2, to apply the voltage pulse (several tens
.mu.s) over 10V to the word line W/L and the first control line
CL1, and to apply 0V to the second bit line BL2. As a result, the
channel electrons are accelerated by the lateral electric field
formed from the drain region 27 to the source region 26, whereby
the channel electrons around the source region 26 become the hot
electrons. The hot electrons jump over the potential barrier of the
first oxide layer 22, so that the hot electrons are locally trapped
to the trap level of the nitride layer 23 around the source region
26, thereby programming 1-bit data.
[0057] If 2-bit data is programmed, in which the electrons are
separately trapped to the nitride layer 23 around the source and
drain regions 26 and 27, the programming electrical anneal is
performed as follows. That is, 0V is applied to the first and
second bit lines BL1 and BL2, the voltage pulse (several tens
.mu.s) of -4V is applied to the first and second control lines CL1
and CL2, and the voltage pulse (several tens ms) of -10V is applied
to the word line W/L, thereby removing the electrons moved to the
lateral side. At this time, even if the voltage pulse (several tens
ms) of -10V is applied to the word line W/L, it is possible to
remove the electrons (the electrons trapped to the lower side of
the first control gate) moved to the lateral side without the
effect on the electrons trapped to the nitride layer 23 around the
source region 26 and the drain region 27, since the voltage pulse
of -4V is applied to the second and third control gates 29 and
30.
[0058] On the data erasing operation of the flash memory device,
erasing and erasing electrical anneal are repetitively performed.
That is, 0V is applied to the first bit line BL1, the voltage over
the threshold voltage Vth is applied to the first control line CL1,
the voltage pulse (several tens is) over -3V is applied to the word
line W/L and the second control line CL2, and the voltage of SV or
more is applied to the second bit line BL2. As a result, a
depletion region is formed in the drain region 27 highly-doped with
n-type impurity ions by a high electric field formed in an overlap
region between the drain region 27 and the third control gate 30.
In the depletion region, pairs of electron and hole are formed by
band to band tunneling. The electron escapes to the highly doped
n-type impurity region. Also, the hole is accelerated by the
lateral electric field formed in the depletion region, and changed
to the hot hole, whereby the hot hole jumps over an energy barrier
between the first oxide layer 12 and the semiconductor substrate
11, and is injected to a valance band, whereby the erasing
operation is completed.
[0059] To remove the electrons moved to the lateral side, the
erasing electrical anneal is performed. That is, the voltage of 0V
is applied to the first and second bit lines BL1 and BL2, the
voltage pulse (several tens is) of 10V is applied to the first and
second control lines CL1 and CL2, and the voltage pulse (several
tens ms) of -10V is applied to the word line W/L, thereby removing
the electrons moved to the lateral side.
[0060] As mentioned above, the flash memory device and the
programming and erasing methods according to the present invention
have the following advantages.
[0061] The second and third control gates are formed at both sides
of the first control gate. Then, in state of applying the
predetermined voltage to the second and third control gates for
maintaining the programmed electrons, and applying the high voltage
to the first control gate, the electrical annealing is progressed
to remove the trapped electrons moved to the lateral side, thereby
improving reliability of the flash memory device.
[0062] It will be apparent to those skilled in the art that various
modifications and variations can be made in the present invention.
Thus, it is intended that the present invention covers the
modifications and variations of this invention provided they come
within the scope of the appended claims and their equivalents.
* * * * *