U.S. patent application number 11/225341 was filed with the patent office on 2006-06-22 for electronic device and manufacturing method thereof.
This patent application is currently assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.. Invention is credited to Yasutoshi Okuno.
Application Number | 20060131575 11/225341 |
Document ID | / |
Family ID | 36594538 |
Filed Date | 2006-06-22 |
United States Patent
Application |
20060131575 |
Kind Code |
A1 |
Okuno; Yasutoshi |
June 22, 2006 |
Electronic device and manufacturing method thereof
Abstract
An electronic device includes an element group which generates a
specific identification number and is composed of a plurality of
elements. The specific identification number is set based on
irregular deviation in electric characteristic of the elements
which is caused due to a random failure in a manufacturing
process.
Inventors: |
Okuno; Yasutoshi; (Kyoto,
JP) |
Correspondence
Address: |
MCDERMOTT WILL & EMERY LLP
600 13TH STREET, N.W.
WASHINGTON
DC
20005-3096
US
|
Assignee: |
MATSUSHITA ELECTRIC INDUSTRIAL CO.,
LTD.
|
Family ID: |
36594538 |
Appl. No.: |
11/225341 |
Filed: |
September 14, 2005 |
Current U.S.
Class: |
257/48 ;
257/E23.179; 438/275; 438/682; 714/E11.019 |
Current CPC
Class: |
H01L 2924/00 20130101;
H01L 23/544 20130101; H01L 2223/5444 20130101; G09C 1/00 20130101;
H01L 2924/0002 20130101; H04L 9/3278 20130101; H04L 2209/12
20130101; G06F 11/006 20130101; H01L 2924/0002 20130101 |
Class at
Publication: |
257/048 ;
438/682; 438/275 |
International
Class: |
H01L 23/58 20060101
H01L023/58 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 17, 2004 |
JP |
2004-366519 |
Claims
1. An electronic device comprising: an element group which
generates a specific identification number and which is composed a
plurality of elements, wherein the specific identification number
is set based on irregular deviation in electric characteristic of
the elements which is caused due to a random failure in a
manufacturing process.
2. The electronic device of claim 1, wherein each of the elements
outputs binary information as variation in electric characteristic
of the element.
3. The electronic device of claim 1, wherein each of the elements
includes an access transistor.
4. The electronic device of claim 3, wherein each of the elements
includes an active region which is connected to the access
transistor electrically and which has a width smaller than a
minimum width in a design rule, a surface of the active region is
silicided to form a silicided layer, and the specific
identification number is set based on irregular resistance rise by
disconnection of the silicided layer in the active region.
5. The electronic device of claim 3, wherein each of the elements
has a gate wiring which is connected to the access transistor
electrically and which has a width smaller than a minimum width in
a design rule, a surface of the gate wiring is silicided to form a
silicided layer, and the specific identification number is set
based on irregular resistance rise by disconnection of the
silicided layer in the gate wiring.
6. The electronic device of claim 3, wherein on an active region of
the access transistor, a contact having a diameter smaller than a
minimum diameter in a design rule or a contact extending over the
active region and an isolation region surrounding the active region
is formed, and the specific identification number is set based on
irregular resistance rise by connection failure between the contact
and the active region.
7. The electronic device of claim 3, wherein a surface of a gate
electrode of the access transistor is silicided to form a silicided
layer, and the specific identification number is set based on
irregular deviation in threshold value of the access transistor
which is caused by full silicidation in the gate electrode.
8. The electronic device of claim 3, wherein the plurality of
elements includes at least one first element having a first gate
wiring which is connected to the access transistor of the first
element electrically and which has a width equal to or larger than
a minimum width in a design rule, the plurality of elements
includes at least one second element having a second gate wiring
which is connected to the access transistor of the second element
electrically and which has a width smaller than a minimum width in
a design rule, surfaces of the first gate wiring and the second
gate wiring are silicided to form silicided layers, the first gate
wiring composes an electric fuse that invites disconnection of the
silicided layer thereof through writing from outside, the second
gate wiring composes a physical fuse that invites disconnection of
the silicided layer thereof which is caused due to a random
failure, and the specific identification number is set based on
respective states of the electrical fuse and the physical fuse.
9. The electronic device of claim 3, wherein each of the elements
includes an active region which is connected to the access
transistor electrically and which has a width equal to or larger
than a minimum width in a design rule, the active region is
provided in a region subjected to local thermal treatment for
controlling a random failure occurrence rate in the manufacturing
process, a surface of the active region is silicided to form a
silicide layer, and the specific identification number is set based
on irregular resistance rise by disconnection of the silicided
layer in the active region.
10. The electronic device of claim 3, wherein each of the elements
includes a gate wiring which is connected to the access transistor
electrically and which has a width equal to or larger than a
minimum width in a design rule, the gate wiring is provided in a
region subjected to local thermal treatment for controlling a
random failure occurrence rate in the manufacturing process, a
surface of the gate wiring is silicided to form a silicided layer,
and the specific identification number is set based on irregular
resistance rise by disconnection of the silicided layer in the gate
wiring.
11. The electronic device of claim 3, wherein a gate electrode of
the access transistor has a width equal to or larger than a minimum
width in a design rule and is provided in a region subjected to
local thermal treatment for controlling a random failure occurrence
rate in the manufacturing process, a surface of the gate electrode
is silicided to form a silicided layer, and the specific
identification number is set based on irregular deviation in
threshold value of the access transistor which is caused by full
silicidation in the gate electrode.
12. The electronic device of claim 7, wherein the silicided layer
of the gate electrode is made of cobalt silicide or nickel
silicide.
13. The electronic device of claim 11, wherein the silicided layer
of the gate electrode is made of cobalt silicide or nickel
silicide.
14. A method for manufacturing an electronic device which includes
an element group that is composed of a plurality of elements and
generates a specific identification number and of which specific
identification number is set based on irregular deviation in
electric characteristic of an element which is caused due to a
random failure in a manufacturing process, the method comprising
the steps of: forming, on a substrate, an access transistor
electrically connected to an active region or a gate wiring, each
having a silicided surface, or an access transistor including a
gate electrode that is fully silicided at least locally; and
performing local thermal treatment to a region where the active
region, the gate wiring, or the gate electrode is arranged.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This Non-provisional application claims priority under 35
U.S.C. .sctn.119(a) on Patent Application No. 2004-366519 filed in
Japan on Dec. 17, 2004, the entire contents of which are hereby
incorporated by reference.
BACKGROUND ART
[0002] The present invention relates to a technology for providing
means for assigning a specific identification number to an
electronic device.
[0003] Assignment of a specific number to an electronic device
itself such as a semiconductor chip and the like has been examined
in view of manufacturing process management (to record information
on when it is manufactured, which wafer or chip it is, and the
like). Recently, taking application to IC money, IC tags, ID cards,
and the like into consideration, it has been recognized that
assignment of a specific number unchangeable from outside to a chip
itself is an important key and essential to problem solution. In
other words, it is important to provide an artificially unforgeable
semiconductor chip. Also, such a method for assigning a specific
number to a chip or the like which is simple as far as possible is
desired in view of cost reduction.
[0004] Under the circumstances, a conventional method has been
employed in which a fuse element or a programmable element such as
an EEPROM (electrically erasable programmable read-only memory) is
provided in a semiconductor chip composing a semiconductor
integrated circuit and specific identification information is
assigned to the programmable element.
[0005] Other novel methods have been proposed such as a method that
utilizes a flip flop rise pattern formed due to ununiformity in
transistor characteristic which is yield by process variation (see,
for example, International Publication No. 02/45139). In detail, a
plurality of identification elements having the same aspect are
formed in the course of a manufacturing process of a semiconductor
integrated circuit device and identification information specific
to the semiconductor integrated circuit device or a semiconductor
chip is set based on a magnitude relationship in physical quantity
of the plurality of identification elements which corresponds to
the process variation.
SUMMARY OF THE INVENTION
[0006] The former method in which a programmable element is
provided, however, requires artificial assignment of the specific
number, necessitating an additional step to the general
manufacturing process or necessitating an additional step of
writing the identification information after the manufacture.
[0007] Also, the latter method in which the identification
information is set based on the magnitude relationship in physical
quantity of the identification elements which corresponds to the
process variation involves the following problems. Namely, in the
method, the magnitude relationship to be identified in physical
quantity offers a minute difference (on a micro scale)
corresponding to standard variation in physical quantity between
two adjacent elements, rather than a comparatively large difference
in physical quantity which is derived from a characteristic
failure. Further, it is highly probable that variation in, for
example, threshold value of adjacent inverter circuit elements
varies depending on environment (particularly, temperature) where
the elements are situated. Therefore, it is difficult to indicate
an invariable specific number with high reliability over the
temperature range where a semiconductor element or the like to be
the identification element is used. Further, these inverters may
indicate inverse values in the presence of cosmic rays, similar to
the case of SRAMs (static random access memory).
[0008] Thus, indication of numbers specific to devices with high
reliability is difficult through the newly proposed method in the
environment in the wide temperature range where the semiconductor
element and the like to be the identification element is used
actually.
[0009] In view of the above problems, the present invention has its
object of assigning an identification number specific to an
electronic device with high reliability without a new step added to
a general manufacture process.
[0010] To attain the above object, the present inventor has
contemplated utilizing, as a specific identification number of an
electronic device, irregular deviation in electric characteristic
which is caused due to a failure (hereinafter referred to as a
random failure) of an element (for example, a semiconductor element
such as resistor element and the like) which occurs accidentally at
a certain probability in an electronic device manufacturing process
such as a semiconductor manufacturing process. Specifically, a
target element is selected first through, for example, an access
transistor, and then, variation in electric characteristic of the
selected element is detected by an sense amplifier. This enables
setting of a specific identification number based on irregular
deviation in electric characteristic of the element which is caused
due to a random failure in the manufacturing process. Further, the
present inventor has contemplated generating a specific
identification number by utilizing, as the irregular deviation in
electric characteristic of the element, irregular resistance rise
that randomly occurs due to accidental disconnection of, for
example, a silicided layer in a silicide wiring (a thin wiring or
an active region at least a part of which is silicided) of a
semiconductor element.
[0011] Specifically, an electronic device according to the present
invention includes: an element group which generates a specific
identification number and which is composed a plurality of
elements, wherein the specific identification number is set based
on irregular deviation in electric characteristic of the elements
which is caused due to a random failure in a manufacturing
process.
[0012] In the electronic device of the present invention, in the
case where each of the elements outputs binary information as
variation in electric characteristic of the element, an specific
number of 2 raised to power of "an ordinal number of elements" can
be generated.
[0013] In the electronic device of the present invention, if each
of the elements has an access transistor, a target element of which
electric characteristic is to be detected can be selected
reliably.
[0014] In the case where each of the elements of the electronic
device in the present invention has the access transistor, it is
possible that each of the elements includes an active region which
is connected to the access transistor electrically and which has a
width smaller than a minimum width in a design rule, a surface of
the active region is silicided to form a silicided layer, and the
specific identification number is set based on irregular resistance
rise by disconnection of the silicided layer in the active
region.
[0015] In the case where each of the elements of the electronic
device in the present invention has the access transistor, it is
possible that each of the elements has a gate wiring which is
connected to the access transistor electrically and which has a
width smaller than a minimum width in a design rule, a surface of
the gate wiring is silicided to form a silicided layer, and the
specific identification number is set based on irregular resistance
rise by disconnection of the silicided layer in the gate
wiring.
[0016] In the case where each of the elements of the electronic
device in the present invention has the access transistor, it is
possible that a contact having a diameter smaller than a minimum
diameter in a design rule or a contact extending over an active
region of the access transistor and an isolation region surrounding
the active region is formed on the active region, and the specific
identification number is set based on irregular resistance rise by
connection failure between the contact and the active region.
[0017] In the case where each of the elements of the electronic
device in the present invention has the access transistor, it is
possible that a surface of a gate electrode of the access
transistor is silicided to form a silicided layer and the specific
identification number is set based on irregular deviation in
threshold value of the access transistor which is caused by full
silicidation in the gate electrode.
[0018] In the case where each of the elements of the electronic
device in the present invention has the access transistor, it is
possible that the plurality of elements includes at least one first
element having a first gate wiring which is connected to the access
transistor of the first element electrically and which has a width
equal to or larger than a minimum width in a design rule, the
plurality of elements includes at least one second element having a
second gate wiring which is connected to the access transistor of
the second element electrically and which has a width smaller than
a minimum width in a design rule, surfaces of the first gate wiring
and the second gate wiring are silicided to form silicided layers,
the first gate wiring composes an electric fuse that invites
disconnection of the silicided layer thereof through writing from
outside, the second gate wiring composes a physical fuse that
invites disconnection of the silicided layer thereof which is
caused due to a random failure, and the specific identification
number is set based on respective states of the electrical fuse and
the physical fuse.
[0019] In the case where each of the elements of the electronic
device in the present invention has the access transistor, it is
possible that each of the elements includes an active region which
is connected to the access transistor electrically and which has a
width equal to or larger than a minimum width in a design rule, the
active region is provided in a region subjected to local thermal
treatment for controlling a random failure occurrence rate in the
manufacturing process, a surface of the active region is silicided
to form a silicide layer, and the specific identification number is
set based on irregular resistance rise by disconnection of the
silicided layer in the active region.
[0020] In the case where each of the elements of the electronic
device in the present invention has the access transistor, it is
possible that each of the elements includes a gate wiring which is
connected to the access transistor electrically and which has a
width equal to or larger than a minimum width in a design rule, the
gate wiring is provided in a region subjected to local thermal
treatment for controlling a random failure occurrence rate in the
manufacturing process, a surface of the gate wiring is silicided to
form a silicided layer, and the specific identification number is
set based on irregular resistance rise by disconnection of the
silicided layer in the gate wiring.
[0021] In the case where each of the elements of the electronic
device in the present invention has the access transistor, it is
possible that a gate electrode of the access transistor has a width
equal to or larger than a minimum width in a design rule and is
provided in a region subjected to local thermal treatment for
controlling a random failure occurrence rate in the manufacturing
process, a surface of the gate electrode is silicided to form a
silicided layer, and the specific identification number is set
based on irregular deviation in threshold value of the access
transistor which is caused by full silicidation in the gate
electrode.
[0022] In the case where each of the elements of the electronic
device in the present invention has the access transistor of which
the surface of the gate electrode is silicided, the silicided layer
of the gate electrode may be made of cobalt silicide or nickel
silicide.
[0023] An electronic device manufacturing method according to the
present invention is a method for manufacturing an electronic
device which includes an element group that is composed of a
plurality of elements and generates a specific identification
number and of which specific identification number is set based on
irregular deviation in electric characteristic of an element which
is caused due to a random failure in a manufacturing process, the
method including the steps of: forming, on a substrate, an access
transistor electrically connected to an active region or a gate
wiring, each having a silicided surface, or an access transistor
including a gate electrode that is fully silicided at least
locally; and performing local thermal treatment to a region where
the active region, the gate wiring, or the gate electrode is
arranged.
[0024] In the present invention, the irregular deviation in
electric characteristic of an element which is caused due to a
random failure in the manufacturing process is utilized as a
specific identification number, so that the specific identification
number can be set for the device without a new step added to the
general manufacturing process. Further, the conventionally utilized
variation in physical quantity of an identification element which
corresponds to process variation is on a micro scale while the
variation in electric characteristic of an element which is caused
due to a failure is comparatively large variation, in other words,
is irregular deviation. Accordingly, the specific identification
number can be recognized with high reliability independent from
environment where the element is situated (for example, temperature
environment). Further, the specific identification number is
impossible to be changed from outside naturally, and therefore an
artificially unforgeable semiconductor chips and the like
applicable to IC money, IC tags, ID cars, and the like can be
obtained.
[0025] As described above, the electronic device and the
manufacturing method thereof according to the present invention
enable assignment of a specific identification number to an
electronic device with high reliability without a new step added to
the general manufacturing process.
[0026] It is also important to note that all of the structures in
the present invention have a self-protection feature from
intentional destruction to change the specific identification
number. When one tries to change the identification number by
physical means, the bit lines or the wirings that overlap the
element area are easily broken. With the self-protection feature,
it is impossible to make effectual change of the identification
number even with intention by physical means.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] FIG. 1 is a diagram schematically showing a layout of a
semiconductor element array in an electronic device according to
Embodiment 1 of the present invention.
[0028] FIG. 2 is a diagram schematically showing a one-bit circuit
constitution of the semiconductor element array in the electronic
device according to Embodiment 1 of the present invention.
[0029] FIG. 3 is a diagram schematically showing another example of
a layout of a semiconductor element array in an electronic device
according to Embodiment 1 of the present invention.
[0030] FIG. 4 is a diagram schematically showing a layout of a
semiconductor element array in an electronic device according to
Embodiment 2 of the present invention.
[0031] FIG. 5 is a diagram schematically showing a layout of a
semiconductor element array in an electronic device according to
Embodiment 3 of the present invention.
[0032] FIG. 6 is a diagram schematically showing a layout of a
semiconductor element array in an electronic device according to
Embodiment 4 of the present invention.
[0033] FIG. 7 is a diagram schematically showing a layout of a
semiconductor element array in an electronic device according to
Embodiment 5 of the present invention.
[0034] FIG. 8 is a diagram schematically showing a layout of a
semiconductor element array in an electronic device according to
Embodiment 6 of the present invention.
[0035] FIG. 9 is a diagram schematically showing a layout of a
semiconductor element array in an electronic device according to
Embodiments 6 to 8 of the present invention.
[0036] FIG. 10 is a diagram schematically showing a layout of a
semiconductor element array in an electronic device according to
Embodiment 7 of the present invention.
[0037] FIG. 11 is a diagram schematically showing a layout of a
semiconductor element array in an electronic device according to
Embodiment 8 of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1
[0038] An electronic device according to Embodiment 1 of the
present invention, specifically, an electronic device having a
semiconductor element array that generates a specific
identification number will be described below with reference to the
drawings.
[0039] FIG. 1 is a diagram schematically showing a layout of the
semiconductor element array in the electronic device according to
Embodiment 1.
[0040] As shown in FIG. 1, the semiconductor element array in the
present embodiment includes a plurality of access transistors
composed of an active region (OD) 1 to serve as a pair of a source
region and a drain region and a gate electrode 2 formed on the
active region 1 to serve as a word line. Wherein, the active region
1 includes a region which is connected to at least one of the
source region and the drain region and which the plurality of
access transistors share in common and a partially thinned region
lead out from the other one of the source region and the drain
region. In short, the active region 1 has an OD thinned wiring 1a.
Further, the surface of the active region 1 including the OD
thinned wiring 1a is silicided. A via contact 3 is formed on the
end part (a contact region) of the active region 1 which is lead
out from the other one of the source region and the drain region so
that the active region 1 is electrically connected through the via
contact 3 to an upper wiring 4 serving as a bit line.
[0041] In the present embodiment, a necessary number of one-bit
configurations, one of which is enclosed by a dash-and-dot line in
FIG. 1, are arranged in an array to form a memory element group
(the semiconductor element array) that generates a specific
identification number. FIG. 2 schematically shows the one-bit
circuit configuration.
[0042] Accordingly, in the present embodiment, the formation of the
OD thinned wiring 1a in the active region 1 enables increase in
possibility of accidental occurrence of irregular resistance rise
in the manufacturing process which is caused by disconnection of
the silicided layer of the OD thinned wiring 1a. Accordingly, when
an access transistor is selected through a word line, the presence
or absence of the resistance rise is recognized as variation in
output from a corresponding bit line through the selected access
transistor, resulting in detection of the presence or absence of
the resistance rise by a sense amplifier. In consequence, a
specific identification number can be set based on the irregular
deviation in electric characteristic of the element composing the
semiconductor element array in the present embodiment which is
caused due to a random failure in the manufacturing process.
[0043] In the present embodiment, the irregular deviation in
electric characteristic of an element which is caused due to a
random failure in the manufacturing process is utilized as a
specific identification number, so that the specific identification
number can be set for the device without a new step added to the
general manufacturing process. Further, the conventionally utilized
variation in physical quantity of an identification element which
corresponds to process variation is on a micro scale while the
variation in electric characteristic of an element which is caused
due to a failure is comparatively large variation, in other words,
is irregular deviation. Accordingly, the specific identification
number can be indicated with high reliability independent from
environment where the element is situated (for example, temperature
environment). Further, the specific identification number is
impossible to be changed from outside naturally, and therefore, an
artificially unforgeable semiconductor chip and the like applicable
to IC money, IC tags, ID cars, and the like can be obtained.
[0044] It is noted that in the present embodiment, outputs from the
bit lines, that is, variation in electric characteristic of the
elements may be dealt with as binary (0/1) information with a
predetermined threshold value set. In this case, a specific number
of 2 raised to power of "an ordinal number of elements" can be
generated.
[0045] Further, it is preferable that the width of the OD thinned
line 1a is set smaller than the minimum width in the design rule
(the minimum width on design which invites no failure without any
flaw by particles, for example, and the like). This enables further
increase in possibility that irregular resistance rise by
disconnection of the silicided layer of the OD thinned wiring 1a
occurs accidentally in the manufacturing process.
[0046] In addition, in the present embodiment, the OD thinned
wiring 1a is formed on the contact region (via contact 3) side but
may, of course, be formed on a common region side of the active
region 1, as shown in FIG. 3.
Embodiment 2
[0047] An electronic device according to Embodiment 2 of the
present invention, specifically, an electronic device having a
semiconductor element array that generates a specific
identification number will be described below with reference to the
drawing.
[0048] FIG. 4 schematically shows a layout of the semiconductor
element array in the electronic device according to Embodiment
2.
[0049] As shown in FIG. 4, the semiconductor element array in the
present embodiment includes a plurality of access transistors
composed of an active region (OD) 1 to serve as a pair of a source
region and a drain region and a gate electrode 2 formed on the
active region 1 to serve as a word line. Wherein, the active region
1 includes a region which is connected to at least one of the
source region and the drain region and which the plurality of
access transistors share in common. The other one of the source
region and the drain region is connected to one end part of a gate
wring (a wiring formed on the same layer where the gate electrode 2
is formed) 5 through a shared contact 6. A via contact 7 is formed
on the other end part (a contact region) of the gate wring 5 so
that the gate wiring 5 is electrically connected through the via
contact 7 to an upper wiring 4 serving as a bit line.
[0050] The gate wiring 5 is thinned partially. In other words, the
gate wiring 5 includes a thinned gate wiring 5a. Also, the surface
of the gate wiring 5 including the thinned gate wiring 5a is
silicided.
[0051] In the present embodiment, a necessary number of one-bit
configurations each composed of the aforementioned access
transistor, the gate wiring 5 connected thereto, and the like are
arranged in an array to form a memory element group (the
semiconductor element array) that generates a specific
identification number.
[0052] Accordingly, in the present embodiment, the formation of the
thinned gate wiring 5a in the gate wiring 5 enables increase in
possibility of accidental occurrence of irregular resistance rise
in the manufacturing process which is caused by disconnection of
the silicided layer of the OD thinned wiring 5a. Accordingly, when
an access transistor is selected through a word line, the presence
or absence of the resistance rise is recognized as variation in
output from a corresponding bit line through the selected access
transistor, resulting in detection of the presence or absence of
the resistance rise by a sense amplifier. In consequence, a
specific identification number can be set based on the irregular
deviation in electric characteristic of the element composing the
semiconductor element array in the present embodiment which caused
due to a random failure in the manufacturing process.
[0053] In the present embodiment, the irregular deviation in
electric characteristic of an element which is caused due to a
random failure in the manufacturing process is utilized as a
specific identification number, so that the specific identification
number can be set for the device without a new step added to the
general manufacturing process. Further, the conventionally utilized
variation in physical quantity of an identification element which
corresponds to process variation is on a micro scale while the
variation in electric characteristic of an element which is caused
due to a failure is comparatively large variation, in other words,
is irregular deviation. Accordingly, the specific identification
number can be indicated with high reliability independent from
environment where the element is situated (for example, temperature
environment). Further, the specific identification number is
impossible to be changed from outside naturally, and therefore, an
artificially unforgeable semiconductor chip and the like applicable
to IC money, IC tags, ID cars, and the like can be obtained.
[0054] It is noted that in the present embodiment, outputs from the
bit lines, that is, variation in electric characteristic of the
elements) may be dealt with as binary (0/1) information with a
predetermined threshold value set. In this case, a specific number
of 2 raised to power of "an ordinal number of elements" can be
generated.
[0055] Further, it is preferable that the width of the thinned gate
wiring 5a is set smaller than the minimum width in the design rule
(the minimum width on design which invites no failure without any
flaw by particles, for example, and the like). This enables further
increase in possibility that irregular resistance rise by
disconnection of the silicided layer of the thinned gate wiring 5a
occurs accidentally in the manufacturing process.
Embodiment 3
[0056] An electronic device according to Embodiment 3 of the
present invention, specifically, an electronic device having a
semiconductor element array that generates a specific
identification number will be described below with reference to the
drawing.
[0057] FIG. 5 schematically shows a layout of the semiconductor
element array in the electronic device according to Embodiment
3.
[0058] As shown in FIG. 5, the semiconductor element array in the
present embodiment includes a plurality of access transistors
composed of an active region (OD) 1 to serve as a pair of a source
region and a drain region and a gate electrode 2 formed on the
active region 1 to serve as a word line. Wherein, the active region
1 includes a region which is, connected to at least one of the
source region and the drain region and which the plurality of
access transistors share in common. A via contact 3 is formed on
the end part (a contact region) of other one of the source region
and the drain region so that the active region 1 is electrically
connected through the via contact 3 to an upper wiring 4 serving as
a bit line.
[0059] Wherein, in the present embodiment, a via contact 3A having
a diameter smaller than a diameter designed based on the design
rule or a via contact 3B a predetermined distance or a further
distance shifted from the active region 1, that is, a via contact
3B extending over the active region 1 and an isolation region
surrounding the active region 1 is formed as the via contact 3.
[0060] In the present embodiment, a necessary number of one-bit
configurations each composed of the aforementioned access
transistor, the wiring 4 connected thereto, and the like are
arranged in an array to form a memory element group (the
semiconductor element array) that generates a specific
identification number.
[0061] Accordingly, in the present embodiment, the via contact 3A
having a diameter smaller than a diameter designed based on the
design rule or the via contact 3B extending over the active region
1 and the isolation region surrounding the active region 1 is
formed as the via contact 3, enabling increase in possibility of
accidental occurrence of irregular resistance rise in the
manufacturing process which is caused by connection failure between
the active region 1 and the via contact 3A or the via contact 3B.
Accordingly, when an access transistor is selected through a word
line, the presence or absence of the resistance rise is recognized
as variation in output from a corresponding bit line through the
selected access transistor, resulting in detection of the presence
or absence of the resistance rise by a sense amplifier. In
consequence, a specific identification number can be set based on
the irregular deviation in electric characteristic of the elements
composing the semiconductor element array in the present embodiment
which is caused due to a random failure in the manufacturing
process.
[0062] In the present embodiment, the irregular deviation in
electric characteristic of an element which is caused due to a
random failure in the manufacturing process is utilized as a
specific identification number, so that the specific identification
number can be set for the device without a new step added to the
general manufacturing process. Further, the conventionally utilized
variation in physical quantity of an identification element which
corresponds to process variation is on a micro scale while the
variation in electric characteristic of an element which caused is
due to a failure is comparatively large variation, in other words,
is irregular deviation. Accordingly, the specific identification
number can be indicated with high reliability independent from
environment where the element is situated (for example,
-temperature environment). Further, the specific identification
number is impossible to be changed from outside naturally, and
therefore, an artificially unforgeable semiconductor chip and the
like applicable to IC money, IC tags, ID cars, and the like can be
obtained.
[0063] It is noted that in the present embodiment, outputs from the
bit lines, that is, variation in electric characteristic of the
elements) may be dealt with as binary (0/1) information with a
predetermined threshold value set. In this case, a specific number
of 2 raised to power of "an ordinal number of elements" can be
generated.
[0064] Further, it is preferable that the diameter of the via
contact 3A is set smaller than the minimum diameter in the design
rule (the minimum diameter on design which invites no failure
without any flaw by particles, for example, and the like). This
enables further increase in possibility that irregular resistance
rise by connection failure of the via contact 3A occurs
accidentally in the manufacturing process.
Embodiment 4
[0065] An electronic device according to Embodiment 4 of the
present invention, specifically, an electronic device having a
semiconductor element array that generates a specific
identification number will be described below with reference to the
drawing.
[0066] FIG. 6 schematically shows a layout of the semiconductor
element array in the electronic device according to Embodiment
4.
[0067] As shown in FIG. 6, the semiconductor element array in the
present embodiment includes a plurality of access transistors
composed of an active region (OD) 1 to serve as a pair of a source
region and a drain region and a gate electrode 2 formed on the
active region 1 to serve as a word line. Wherein, the active region
1 includes a region which is connected to at least one of the
source region and the drain region and which the plurality of
access transistors share in common. A via contact 3 is formed on
the end part (a contact region) of the other one of the source
region and the drain region so that the active region 1 is
electrically connected through the via contact 3 to an upper wiring
4 serving as a bit line.
[0068] In the present embodiment, polysilicon is used as a material
of the gate electrode 2 and the surface of the gate electrode 2 is
silicided. Further, the width of the gate electrode 2 is set
smaller than the width set based on the design rule so that the
polysilicon forming the gate electrode 2 exhibits excess reactivity
locally through silicidation of the gate electrode 2. This allows a
phenomenon (full silicidation) that the silicide layer reaches the
gate insulating film to be caused easily. In this way, a fully
silicided (FUSI) electrode 2a having a work function different from
that of the other gate electrodes 2 is formed, resulting in local
formation of an access transistor having a threshold value (Vt)
different from the other access transistors (as to threshold value
variation by full silicidation, see "Threshold voltage control in
NiSi-gated MOSFETs through silicidation induced impurity
segregation (SIIS)," by Jakub Kedzierski et al., Technical Digest
of International Electron Devices Meeting, 2003, for example).
[0069] In the present embodiment, a necessary number of one-bit
configurations each composed of the aforementioned access
transistor, the wiring 4 connected thereto, and the like are
arranged in an array to form a memory element group (the
semiconductor element array) that generates a specific
identification number.
[0070] Accordingly, in the present embodiment, the thinning the
gate electrode 2 enables increase in possibility that irregular
deviation in threshold value of an access transistor which is
caused by local full silicidation in the gate electrode 2 occurs
accidentally in the manufacturing process. Accordingly, when an
access transistor is selected through a word line, the presence or
absence of the variation in threshold value is recognized as
variation in output from a corresponding bit line through the
selected access transistor, resulting in detection of the presence
or absence of the resistance rise by a sense amplifier. In
consequence, a specific identification number can be set based on
the irregular deviation in electric characteristic of the element
composing the semiconductor element array in the present embodiment
which is caused due to a random failure in the manufacturing
process.
[0071] In the present embodiment, the irregular deviation in
electric characteristic of an element which is caused due to a
random failure in the manufacturing process is utilized as a
specific identification number, so that the specific identification
number can be set for the device without a new step added to the
general manufacturing process. Further, the conventionally utilized
variation in physical quantity of an identification element which
corresponds to process variation is on a micro scale while the
variation in electric characteristic of the elements which is
caused due to a failure is comparatively large variation, in other
words, is irregular deviation. Accordingly, the specific
identification number can be indicated with high reliability
independent from environment where the element is situated (for
example, temperature environment). Further, the specific
identification number is impossible to be changed from outside
naturally, and therefore, an artificially unforgeable semiconductor
chip and the like applicable to IC money, IC tags, ID cars, and the
like can be obtained.
[0072] It is noted that in the present embodiment, outputs from the
bit lines, that is, variation in electric characteristic of the
elements may be dealt with as binary (0/1) information with a
predetermined threshold value set. In this case, a specific number
of 2 raised to power of "an ordinal number of elements" can be
generated.
[0073] Further, it is preferable that the width of the gate
electrode 2 is set, smaller than the minimum width in the design
rule (the minimum width on design which invites no failure without
any flaw by particles, for example, and the like). This enables
further increase in possibility that irregular deviation in
threshold value which is caused by full silicidation in the gate
electrode 2 occurs accidentally in the manufacturing process.
[0074] In addition, in the present embodiment, a cobalt silicide
layer or a nickel silicide layer may be used as the silicided layer
in the gate electrode 2.
Embodiment 5
[0075] An electronic device according to Embodiment 5 of the
present invention, specifically, an electronic device having a
semiconductor element array that generates a specific
identification number will be described below with reference to the
drawing.
[0076] FIG. 7 schematically shows a layout of the semiconductor
element array in the electronic device according to Embodiment
5.
[0077] As shown in FIG. 7, the semiconductor element array in the
present embodiment is composed of a first element group (a part
capable of being written, hereinafter referred to as a writable
part) having an electric fuse that invites disconnection of a
silicided layer through writing from outside and a second element
group (a random part) having a physical fuse that invites
disconnection of the silicided layer which is caused due to a
random failure.
[0078] The layout of the elements in the random part is basically
the same as the layout of the semiconductor element array in the
electronic device according to Embodiment 2 shown in FIG. 4.
Specifically, each element in the random part includes an access
transistor composed of an active region (OD) 1 to serve as a pair
of a source region and a drain region and a gate electrode 2 formed
on the active region 1 to serve as a word line. The active region 1
includes a region which is electrically connected to one of the
source region and the drain region and which a plurality of access
transistors (including an access. transistor of an element in the
writable part described later) share in common. Further, the other
one of the source region and the drain region is connected to one
end part of a gate wiring 5 through a shared contact 6. A via
contact 7 is formed on the other end part (a contact region) of the
gate wiring 5 so that the gate wiring 5 is electrically connected
through the via contact 7 to an upper wiring 4 serving as a bit
line.
[0079] Wherein, the gate wiring 5 in the random part is thinned
partially. In other words, the gate wiring 5 in the random part
includes a thinned gate wiring 5a. Further, the surface of the gate
wiring 5 including the thinned gate wiring 5a is silicided.
[0080] On the other hand, each element in the writable part
includes, similar to the elements in the random part, an access
transistor composed of an active region (OD) 1 to serve as a pair
of a source region and a drain region and a gate electrode 2 formed
on the active region 1 to serve as a word line.
[0081] Difference of the elements in the writable part from those
in the random part lies in that the gate wiring 5 is not thinned
for preventing the silicided layer from being disconnected due to a
random failure, namely, for preventing irregular resistance rise.
In other words, the gate wiring 5 in the writable part has a line
width defined on the design rule. Wherein, the surface of the gate
wiring 5 in the writable part is silicided also. Further, the
access transistor in the writable part is connected to a write
decoder (decoder driver) through another contact 8 formed on the
shared contact 6 and another wiring 9 for connecting the contact
8.
[0082] In the thus composed random part of the semiconductor
element array in the present embodiment, a necessary number of
one-bit configurations each composed of the aforementioned access
transistor, the gate wiring 5 connected thereto, and the like are
arranged in an array to form a memory element group that generates
a specific identification number. Wherein, the formation of the
thinned gate wiring 5a in the gate wiring 5 in the random part, as
described above, enables increase in possibility that irregular
resistance rise by disconnection of the silicided layer of the
thinned gate wiring 5a occurs accidentally in the manufacturing
process. Accordingly, when an access transistor in the random part
is selected through a word line, the presence or absence of the
resistance rise is recognized as variation in output from a
corresponding bit line through the selected access transistor,
resulting in detection of the presence or absence of the resistance
rise by a sense amplifier. In consequence, a specific
identification number can be set based on the irregular deviation
in electric characteristic of an element composing the random part
which is caused due to a random failure in the manufacturing
process.
[0083] In the present embodiment, the irregular deviation in
electric characteristic of an element which is caused due to a
random failure in the manufacturing process is utilized as a
specific identification number, so that the specific identification
number can be set for the device without a new step added to the
general manufacturing process. Further, the conventionally utilized
variation in physical quantity of an identification element which
corresponds to process variation is on a micro scale while the
variation in electric characteristic of the element which is due to
a failure is comparatively large variation, in other words, is
irregular deviation. Accordingly, the specific identification
number can be indicated with high reliability independent from
environment where the element is situated (for example, temperature
environment). Further, the specific identification number is
impossible to be changed from outside naturally, and therefore, an
artificially unforgeable semiconductor chip and the like applicable
to IC money, IC tags, ID cars, and the like can be obtained.
[0084] Moreover, in the semiconductor element array in the present
embodiment, there are provided the two parts of the writable part
having the electrical fuse that invites disconnection (forced
disconnection) of the silicided layer through writing from outside
and the random part having the physical fuse that invites
disconnection (accidental disconnection) of the silicided layer
which is caused due to a random failure. With the two parts
provided, information such as a check digit used for parity check
is written into the writable part, generating a more highly
reliable specific identification number.
[0085] It is noted that in the present embodiment, outputs from the
bit lines in the random part, that is, variation in electric
characteristic of the element may be dealt with as binary (0/1)
information with a predetermined threshold value set. In this case,
a specific number of 2 raised to power of "an ordinal number of
elements" can be generated.
[0086] In addition, it is preferable that the width of the thinned
gate wiring 5a in the random pat is set smaller than the minimum
width in the design rule (the minimum width on design which invites
no failure without any flaw by particles, for example, and the
like).
[0087] This enables further increase in possibility that irregular
resistance rise by disconnection of the silicided layer of the
thinned gate wiring 5a occurs accidentally in the manufacturing
process.
Embodiment 6
[0088] An electronic device according to Embodiment 6 of the
present invention, specifically, an electronic device having a
semiconductor element array that generates a specific
identification number will be described below with reference to the
drawings
[0089] FIG. 8 schematically shows a layout of the semiconductor
element array in the electronic device according to Embodiment
6.
[0090] As shown in FIG. 8, the semiconductor element array in the
present embodiment includes a plurality of access transistors
composed of an active region (OD) 1 to serve as a pair of a source
region and a drain region and a gate electrode 2 formed on the
active region 1 to serve as a word line. Wherein, the active region
1 includes a region which is electrically connected to at least one
of the source region and the drain region and which the plurality
of access transistors share in common and a region lead out from
the other one of the source region and the drain region (the region
being not thinned, different from the case in Embodiment 1). The
surface of the active region 1 is silicided. Further, a via contact
3 is formed on the end part (a contact region) of the active region
1 which is lead out from the other one of the source region and the
drain region so that the active region 1 is electrically connected
through the via contact 3 to an upper wiring 4 serving as a bit
line.
[0091] In the present embodiment, a necessary number of one-bit
configurations, one of which is enclosed by a dash-and-dot line in
FIG. 8, are arranged in an array to form a memory element group
(the semiconductor element array) that generates a specific
identification number.
[0092] Moreover, in the present embodiment, using the semiconductor
element array shown in FIG. 8 as one unit, a plurality of such
units are arranged as shown, for example, in FIG. 9 (the respective
elements shown in FIG. 9 correspond to the elements shown in FIG. 4
in Embodiment 2). This enables concentrated arrangement of the
active regions 1 functioning as the memory elements within a
predetermined region R.
[0093] Further, in the present embodiment, an additional step of
locally heating the predetermined region R, that is, the active
regions 1 in the semiconductor element arrays of the present
embodiment is performed after a step called a second silicide RTP
(rapid thermal process) in a general CMOS (complementary
metal-oxide semiconductor device) manufacturing process. This
enables increase in possibility of accidental occurrence of
irregular resistance rise by disconnection of the silicided layer
in the active region 1. Accordingly, when an access transistor is
selected through a word line, the presence or absence of the
resistance rise is recognized as variation in output from a
corresponding bit line through the selected access transistor,
resulting in detection of the presence or absence of the resistance
rise by a sense amplifier. In consequence, a specific
identification number can be set based on the irregular deviation
in electric characteristic of the element composing the
semiconductor element array in the present embodiment which is
caused due to a random failure in the manufacturing process.
[0094] In the present embodiment, the irregular deviation in
electric characteristic of an element which is caused due to a
random failure in the manufacturing process is utilized as a
specific identification number. The conventionally utilized
variation in physical quantity of an identification element which
corresponds to process variation is on a micro scale while the
variation in electric characteristic of the elements which is
caused due to a failure is comparatively large variation, in other
words, is irregular deviation. Accordingly, the specific
identification number can be indicated with high reliability.
independent from environment where the element is situated (for
example, temperature environment). Further, the specific
identification number is impossible to be changed from outside
naturally, and therefore, an artificially unforgeable semiconductor
chip and the like applicable to IC money, IC tags, ID cars, and the
like can be obtained.
[0095] The present embodiment requires an additional step of
subjecting the active regions 1 to the local thermal treatment.
However, no step is necessitated which does not comply with the
design rule, such as the formation of the OD thinned wiring 1a, for
example, in Embodiment 1, for intentionally causing the irregular
resistance rise by disconnection of the silicided layer in the
active regions 1. Hence, a side effect derived from particle
generation and the like in the process can be prevented.
[0096] It is noted that in the present embodiment, outputs from the
bit lines, that is, variation in electric characteristic of the
elements may be dealt with as binary (0/1) information with a
predetermined threshold value set. In this case, a specific number
of 2 raised to power of "an ordinal number of elements" can be
generated.
[0097] In addition, in the present embodiment, a cobalt silicide
layer or a nickel silicide layer may be used as the silicided layer
in the active region 1. For using the cobalt silicide layer, the
temperature for the thermal treatment for locally heating the
active region 1 is preferably set within the range between
800.degree. C. and 900.degree. C., both inclusive. On the other
hand, for using the nickel silicide layer, the temperature for the
thermal treatment is preferably set within the range between
500.degree. C. and 700.degree. C., both inclusive.
Embodiment 7
[0098] An electronic device according to Embodiment 7 of the
present invention, specifically, an electronic device having a
semiconductor element array that generates a specific
identification number will be described below with reference to the
drawing.
[0099] FIG. 10 schematically shows a layout of the semiconductor
element array in the electronic device according to Embodiment
7.
[0100] As shown in FIG. 10, the semiconductor element array in the
present embodiment includes a plurality of access transistors
composed of an active region (OD) 1 to serve as a pair of a source
region and a drain region and a gate electrode 2 formed on the
active region 1 to serve as a word line. Wherein, the active region
1 includes a region which is electrically connected to at least one
of the source region and the drain region and which the plurality
of access transistors share in common. The other one of the source
region and the drain region is connected to a gate wring 5 (the
gate wiring 5 being not thinned, different from that in Embodiment
2) through a shared contact 6. A via contact 7 is formed on the
other end part (a contact region) of the gate wring 5 so that the
gate wiring 5 is electrically connected through the via contact 7
to an upper wiring 4 serving as a bit line. The surface of the gate
wiring 5 is silicided.
[0101] In the present embodiment, a necessary number of one-bit
configurations each composed of the aforementioned access
transistor, the wiring 5 connected thereto, and the like are
arranged in an array to form a memory element group (the
semiconductor element array) that generates a specific
identification number.
[0102] Also, in the present embodiment, using the semiconductor
element array shown in FIG. 10 as one unit, a plurality of such
units are arranged as shown, for example, in FIG. 9 (the respective
elements shown in FIG. 9 correspond to the elements shown in FIG. 4
in Embodiment 2), likewise the case in Embodiment 6. This enables
concentrated arrangement of the gate wirings 5 functioning as the
memory elements within the predetermined region R.
[0103] Further, in the present embodiment, an additional step of
locally heating the predetermined region R, that is, the gate
wirings 5 in the semiconductor element arrays of the present
embodiment is performed after a step called a second silicide RTP
in a general CMOS manufacturing process. This enables increase in
possibility of accidental occurrence of irregular resistance rise
by disconnection of the silicided layer in the gate wring 5.
Accordingly, when an access transistor is selected through a word
line, the presence or absence of the resistance rise is recognized
as variation in output from a corresponding bit line through the
selected access transistor, resulting in detection of the presence
or absence of the resistance rise by a sense amplifier. In
consequence, a specific identification number can be set based on
the irregular deviation in electric characteristic of the element
composing the semiconductor element array in the present embodiment
which is caused due to a random failure in the manufacturing
process.
[0104] In the present embodiment, the irregular deviation in
electric characteristic of an element which is caused due to a
random failure in the manufacturing process is utilized as a
specific identification number. The conventionally utilized
variation in physical quantity of an identification element which
corresponds to process variation is on a micro scale while the
variation in electric characteristic of the element which is due to
a failure is comparatively large variation, in other words, is
irregular deviation. Accordingly, the specific identification
number can be indicated with high reliability independent from
environment where the element is situated (for example, temperature
environment). Further, the specific identification number is
impossible to be changed from outside naturally, and therefore, an
artificially unforgeable semiconductor chip and the like applicable
to IC money, IC tags, ID cars, and the like can be obtained.
[0105] The present embodiment requires an additional step of
subjecting the gate wiring 5 to local thermal treatment. However,
no step is necessitated which does not comply with the design rule,
such as the formation of the thinned gate wiring 5a in, for
example, Embodiment 2, for intentionally causing the irregular
resistance rise by disconnection of the silicided layer in the gate
wiring 5. Hence, a side effect derived from particle generation and
the like in the process can be prevented.
[0106] It is noted that in the present embodiment, outputs from the
bit lines, that is, variation in electric characteristic of the
elements may be dealt with as binary (0/1) information with a
predetermined threshold value set. In this case, a specific number
of 2 raised to power of "an ordinal number of elements" can be
generated.
[0107] In addition, in the present embodiment, a cobalt silicide
layer or a nickel silicide layer may be used as the silicided layer
in the gate wiring 5. For using the cobalt silicide layer, the
temperature for the thermal treatment for locally heating the gate
wiring 5 is preferably set within the range between 800.degree. C.
and 900.degree. C., both inclusive. On the other hand, for using
the nickel silicide layer, the temperature for the thermal
treatment is preferably set within the range between 500.degree. C.
and 700.degree. C., both inclusive.
Embodiment 8
[0108] An electronic device according to Embodiment 8 of the
present invention, specifically, an electronic device having a
semiconductor element array that generates a specific
identification number will be described below with reference to the
drawing.
[0109] FIG. 11 schematically shows a layout of the semiconductor
element array in the electronic device according to Embodiment
8.
[0110] As shown in FIG. 11, the semiconductor element array in the
present embodiment includes a plurality of access transistors
composed of an active region (OD) 1 to serve as a pair of a source
region and a drain region and a gate electrode 2 formed on the
active region 1 to serve as a word line. Wherein, the active region
1 includes a region which is connected to at least one of the
source region and the drain region and which the plurality of
access transistors share in common. A via contact 3 is formed on
the end part (a contact region) of other one of the source region
and the drain region so that the active region 1 is electrically
connected through the via contact 3 to an upper wiring 4 serving as
a bit line.
[0111] In the present embodiment, polysilicon is used as a material
of the gate electrode 2 and the surface of the gate electrode 2 is
silicided. Further, the width of the gate electrode 2 is set equal
to or larger than the width determined based on the design rule,
different from the case in Embodiment 4.
[0112] In the present embodiment, also, a necessary number of
one-bit configurations each composed of the aforementioned access
transistor, the wiring 4 connected thereto, and the like are
arranged in an array to form a memory element group (the
semiconductor element array) that generates a specific
identification number.
[0113] Further, in the present embodiment, using the semiconductor
element array shown in FIG. 11 as one unit, a plurality of such
units are arranged as shown, for example, in FIG. 9 (the respective
elements shown in FIG. 9 correspond to the elements shown in FIG. 4
in Embodiment 2), likewise the case in Embodiment 6. This enables
concentrated arrangement of the gate electrodes 2 functioning as
the memory elements within the predetermined region R.
[0114] Moreover, in the present embodiment, an additional step of
locally heating the predetermined region R, that is, the gate
electrodes 2 in the semiconductor element arrays of the present
embodiment is performed after a step called a first silicide RTP in
a genral CMOS manufacturing process. Through this heating, the
polysilicon forming the gate electrode 2 exhibits excess reactivity
locally, allowing a phenomenon (full silicidation) that the
silicided layer reaches the gate insulating film to be caused
easily. As a result, a fully silicided (FUSI) electrode 2a having a
work function different from that of the other gate electrodes 2 is
formed, resulting in local formation of an access transistor having
a threshold value (Vt) different from that of the other access
transistors.
[0115] In other words, in the present embodiment, the additional
step of locally heating the gate electrode 2 is performed for
increasing the possibility of accidental occurrence of irregular
deviation in threshold value of the access transistor which is
caused by local full silicidation of the gate electrode 2.
Accordingly, when an access transistor is selected through a word
line, the presence or absence of the variation in threshold value
is recognized as variation in output from a correspoding bit line
through the selected access transistor, resulting in detection of
the presence or absence of the variation in threshold value by a
sense amplifier. In consequence, a specific identification number
can be set based on the irregular deviation in electric
characteristic of the element composing the semiconductor element
array in the present embodiment which is caused due to a random
failure in the manufacturing process.
[0116] In the present embodiment, the irregular deviation in
electric characteristic of an element which is caused due to a
random failure in the manufacturing process is utilized as a
specific identification number. The conventionally utilized
variation in physical quantity of an identification element which
corresponds to process variation is on a micro scale while the
variation in electric characteristic of an element which is caused
due to a failure is comparatively large variation, in other words,
is irregular deviation. Accordingly, the specific identification
number can be indicated with high reliability independent from
environment where the element is situated (for example, temperature
environment). Further, the specific identification number is
impossible to be changed from outside naturally, and therefore, an
artificially unforgeable semiconductor chip and the like applicable
to IC money, IC tags, ID cars, and the like can be obtained.
[0117] The present embodiment requires an additional step of
subjecting the gate electrode 2 to local thermal treatment to the
general manufacturing process. However, no step is necessitated
which does not comply with the design rule, such as the thinning of
the gate electrode 2 in, for example, Embodiment 4, for
intentionally causing the irregular resistance rise by
disconnection of the silicided layer in the gate electrode 2.
Hence, a side effect derived from particle generation and the like
in the process can be prevented.
[0118] In addition, in the present embodiment, a cobalt silicide
layer or a nickel silicide layer may be used as the silicided layer
in the gate electrode 2. For using the cobalt silicide layer, the
temperature for the thermal treatment for locally heating the gate
electrode 2 is preferably set within the range between 500.degree.
C. and 600.degree. C., both inclusive. On the other hand, for using
the nickel silicide layer, the temperature for the thermal
treatment is preferably set within the range between 300.degree. C.
and 500.degree. C., both inclusive.
[0119] Referring to the number of the elements, appropriate number
setting is a key to generation of irregular deviation in electric
characteristic of an element which is caused due to a random
failure in the manufacturing process of an electronic device such
as a semiconductor device in view of cost reduction and area
minimization of the semiconductor device. Under the circumstances,
it is possible in each embodiment of the present invention that
random failure occurrence rates are measured using, for example,
TEG (Test Element Group) first, a specific identification number
having the highest occurrence rate is obtained among the thus
measured occurrence rates, a product of the highest occurrence rate
and the number of manufactured semiconductor devices, that is, an
expected value is obtained, and then, the number of bits for
generating a specific identification number, that is, a size of the
semiconductor element array is determined so that the expected
value becomes sufficiently small. This attains rational and
appropriate setting of the number of the elements which enables
generation of a required number (kinds) of specific identification
numbers.
[0120] In addition, in each embodiment of the present invention, it
is preferable to generate a specific identification number in the
initial stages of the semiconductor manufacturing process by
setting a step of causing a random failure that causes irregular
variation in electric characteristic in the former half stages (an
element formation process and the like before a wiring process) of
the diffusion processes (processes until wafer dicing) in the
semiconductor device manufacturing process. This allows the
specific identification number incapable of artificial
falsification to be determined in the initial stages (in an FE
(Front-end) stage) of the semiconductor manufacturing process,
rather than writing of the specific identification number after the
semiconductor device has been manufactured, exhibiting remarkable
effects on security and on duplication prevention.
* * * * *