U.S. patent application number 11/346029 was filed with the patent office on 2006-06-15 for transistor device having a delafossite material.
Invention is credited to Randy Hoffman, John Wager.
Application Number | 20060125098 11/346029 |
Document ID | / |
Family ID | 34523178 |
Filed Date | 2006-06-15 |
United States Patent
Application |
20060125098 |
Kind Code |
A1 |
Hoffman; Randy ; et
al. |
June 15, 2006 |
Transistor device having a delafossite material
Abstract
A transistor device includes a channel of p-type substantially
transparent delafossite material. Source and drain contacts are
interfaced to the channel. Gate dielectric is between a gate
contact and the channel.
Inventors: |
Hoffman; Randy; (Corvallis,
OR) ; Wager; John; (Corvallis, OR) |
Correspondence
Address: |
HEWLETT-PACKARD COMPANY;Intellectual Property Administration
P.O. Box 272400
Ft. Collins
CO
80527-2400
US
|
Family ID: |
34523178 |
Appl. No.: |
11/346029 |
Filed: |
February 2, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10738690 |
Dec 17, 2003 |
7026713 |
|
|
11346029 |
Feb 2, 2006 |
|
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Current U.S.
Class: |
257/749 ;
257/E21.411 |
Current CPC
Class: |
H01L 29/78648 20130101;
H01L 29/66969 20130101; H01L 27/1225 20130101; H01L 29/7869
20130101 |
Class at
Publication: |
257/749 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Claims
1. A method of using a transistor device, the transistor device
comprising a channel of p-type substantially transparent
delafossite material, a source contact interfaced to said channel,
a drain contact interfaced to said channel, a gate contact, and a
gate dielectric between said gate contact and said channel, the
method comprising: arranging the transistor device with additional
transistor devices; providing voltages to said source, drain and
gate contacts to induce conduction in said channel.
2. The method of claim 1, wherein said providing voltages comprises
providing a negative voltage to said gate to draw holes from one or
both of said source and drain contacts.
3. The method of claim 2, further comprising providing additional
voltages to operate the transistor device, said providing
additional voltages comprising a providing a turn-off voltage to
said gate contact.
4. The method of claim 1, wherein said arranging arranges the
transistor device with additional transistor devices in a switch
circuit configuration.
5. The method of claim 1, wherein said arranging arranges the
transistor device with additional transistor devices in an
amplifier circuit configuration.
6. The method of claim 1, wherein said arranging arranges the
transistor device with additional transistor devices in a load
circuit configuration.
7. A method of forming a transistor device, the method comprising:
in an appropriate sequence for a desired transistor configuration,
depositing thin film layers including thin film gate, source, and
drain contacts, gate dielectric and a substantially transparent
delafossite channel; and at appropriate times during the
appropriate sequence, patterning the thin film layers.
8. The method of claim 7, wherein depositing comprises applying
solution-based deposition techniques.
9. The method of claim 8, wherein said solution-based deposition
techniques comprise direct write techniques.
10. The method of claim 9, wherein said patterning comprises a
lithography and etching process.
11. The method of claim 9, wherein said patterning comprises a
direct-write patterning.
12. A method of forming a transistor device, the method comprising:
forming a channel of a p-type substantially transparent delafossite
material; forming a source contact interfaced to said channel;
forming a drain contact interfaced to said channel; forming a gate
contact; and forming a gate dielectric between said gate contact
and said channel.
13. The method of claim 12, wherein forming said channel further
comprises forming said channel using an undoped p-type
substantially transparent delafossite material.
14. The method of claim 12, wherein forming said gate contact
further comprises forming said gate contact over a substrate,
wherein forming said gate dielectric further comprises forming said
gate dielectric upon said gate contact, and wherein forming said
channel further comprises forming said channel upon said gate
dielectric, wherein said additional.
15. The method of claim 3, further comprising: forming an
additional gate dielectric; and forming an additional gate contact,
wherein said additional dielectric and said additional gate contact
is formed upon said channel and said source and drain contacts.
16. The method of claim 12, wherein forming said channel further
comprises forming said channel of said p-type substantially
transparent delafossite material using a channel material selected
from the group consisting of CuScO.sub.2, CuAlO.sub.2, CuYO.sub.2,
CuFeO.sub.2, CuCrO.sub.2, CuGaO.sub.2, CulnO.sub.2, AgCoO.sub.2,
AgGaO.sub.2, AglnO.sub.2, AgScO.sub.2, AgCrO.sub.2 and mixtures
thereof.
17. The method of claim 12, wherein forming said gate dielectric
further comprises forming said gate dielectric using a dielectric
material selected from the group consisting of SiO.sub.2,
Si.sub.3N.sub.4, Al.sub.2O.sub.3, Ta.sub.2O.sub.5, HfO.sub.2,
ZrO.sub.2, and mixtures thereof.
18. The method of claim 12, wherein forming said source, drain and
gate contacts further comprises forming said source, drain and gate
contacts using a doped semiconductor selected from the group
consisting of GaN, BaCu.sub.2S.sub.2, NiO, Cu.sub.2O, CuScO.sub.2,
CuAlO.sub.2, CuYO.sub.2, CuFeO.sub.2, CuCrO.sub.2, CuGaO.sub.2,
CulnO.sub.2, AgCoO.sub.2, AgGaO.sub.2, AglnO.sub.2, AgScO.sub.2,
AgCrO.sub.2, and mixtures thereof.
19. The method of claim 1, wherein forming said source and drain
contacts further comprises forming said source and drain contacts
upon a substrate, wherein forming said channel further comprises
forming said channel upon said substrate, and wherein forming said
gate dielectric further comprises forming said gate dielectric upon
said source and drain contacts and said channel.
20. The method of claim 19, wherein forming said channel further
comprises forming said channel of said p-type substantially
transparent delafossite material using a channel material selected
from the group consisting of CuScO.sub.2, CuAlO.sub.2, CuYO.sub.2,
CuFeO.sub.2, CuCrO.sub.2, CuGaO.sub.2, CulnO.sub.2, AgCoO.sub.2,
AgGaO.sub.2, AglnO.sub.2, AgScO.sub.2, AgCrO.sub.2, and mixtures
thereof.
21. The method of claim 19, wherein forming said gate dielectric
further comprises forming said gate dielectric using a dielectric
material selected from the group consisting of SiO.sub.2,
Si.sub.3N.sub.4, Al.sub.2O.sub.3, Ta.sub.2O.sub.5, HfO.sub.2,
ZrO.sub.2, and mixtures thereof
22. The method of claim 19, wherein forming said source, drain and
gate contacts further comprises forming said source, drain and gate
contacts using a doped semiconductor selected from the group
consisting of GaN, BaCu.sub.2S.sub.2, NiO, Cu.sub.2O, CuScO.sub.2,
CuAlO.sub.2, CuYO.sub.2, CuFeO.sub.2, CuCrO.sub.2, CuGaO.sub.2,
CulnO.sub.2, AgCoO.sub.2, AgGaO.sub.2, AglnO.sub.2, AgScO.sub.2,
AgCrO.sub.2, and mixtures thereof
23. The method of claim 12, wherein forming each of said source,
drain and gate contacts, and said gate dielectric further
comprises: forming a transparent source contact; forming a
transparent drain contact; forming a transparent gate contact; and
forming a transparent gate dielectric wherein a transparent device
is formed.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional application and claims the
benefit and priority of U.S. patent application Ser. No. 10/738,690
filed Dec. 17, 2003.
BACKGROUND
Description of the Prior Art
[0002] Thin film transistors are of great interest in the
semiconductor industry as they represent a more universally
applicable technology than traditional transistor devices. In some
cases, thin film transistors also provide new properties that
designers may leverage for great advantage. One interesting
property is transparency.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] FIG. 1 is a schematic cross-section of an exemplary
embodiment bottom gate p-type transparent channel thin film
transistor;
[0004] FIG. 2 is a schematic cross-section of an exemplary
embodiment top gate p-type transparent channel thin film
transistor;
[0005] FIG. 3 is a schematic cross-section of an exemplary
embodiment bottom gate p-type transparent channel thin film
transistor;
[0006] FIG. 4 is a schematic cross-section of an exemplary
embodiment top gate p-type transparent channel thin film
transistor;
[0007] FIGS. 5 and 6 are schematic cross-sections of exemplary
embodiment dual gate p-type transparent channel thin film
transistors;
[0008] FIG. 7 is a schematic cross-section of a portion of an
exemplary embodiment CMOS circuit including a p-type transparent
thin film transistor; and
[0009] FIG. 8 is a schematic cross-section of an exemplary CMOS
circuit with an embodiment of an integrated device.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0010] The disclosed subject matter concerns transparent channel
thin film transistors and a p-type transparent channel thin film
transistor. In embodiments, an undoped or lightly doped delafossite
material forms a p-type channel in a thin film transistor. In
example embodiments, gate, source, drain regions and isolations are
also formed from transparent materials to form a completely
transparent device. Additional embodiments of the invention concern
the integration of a p-type transparent delafossite channel
transistor as the basis for a complementary metal oxide
semiconductor (CMOS) circuit. A p-type transparent delafossite
channel transistor may be integrated with conventional n-channel
transparent thin film transistors for forming a CMOS circuit in
accordance with embodiments of the invention. A CMOS transparent
thin film circuit is thereby formed, and extends the general
advantages of complementary circuits to a transparent channel thin
film transistor circuit.
[0011] Thin film transistors of the embodiments of the invention
have the general applicability of thin film transistors.
Transparent device embodiments of the invention may be particularly
well suited to display applications. Transparent devices are less
likely to be affected by light than non-transparent devices, as the
transparent devices absorb little to no energy from light.
[0012] Thin film transistors of example embodiments of the
invention may be solution-processed at low temperatures. Choosing
delafossite materials that are either soluble in a solution or
capable of suspension in a solution permits processing by a
solution technique, e.g., ink jet printing or spin coating. The
solution-processed thin film transistors may be fabricated by
simple techniques, e.g., direct printing of circuits. Screen
printing is an example technique for patterning drain and source
regions of solution-processed thin film transistors.
[0013] Embodiments of thin film transistor devices will now be
illustrated. In the description, particular exemplary devices and
device applications will be used for purposes of illustration, but
the embodiments of the invention are not limited to the formation
of the particular illustrated devices. Dimensions and illustrated
devices may be exaggerated for purposes of illustration and
understanding of the embodiments. Reference numerals may be used in
different embodiments to indicate similar features. The elements of
the drawings are not necessarily to scale relative to each other.
Rather, emphasis has instead been placed upon clearly illustrating
the embodiments of the invention. A device illustrated by a
two-dimensional schematic layer structure will be understood by
artisans to provide teaching of three-dimensional device structures
and integrations.
[0014] Exemplary embodiments will now be discussed with respect to
the figures. All device layers in the following description are
thin film layers. FIG. 1 shows an exemplary embodiment bottom gate
thin-film transistor 8. A p-type transparent channel 10 is
controlled by co-planar source and drain contacts 12, 14 and a gate
contact 16, which is isolated from the transparent channel 10 by
gate dielectric 18. A substrate 20 upon which the transistor 8 is
formed should have good dielectric properties and be compatible
with the thin film materials used to form the transistor 8.
Suitable exemplary substrates include glass and plastic. Particular
examples include polycarbonate, polyarylate,
polyethylenterephtalate (PET), polyestersulfone (PES), polyimide,
polyolefin, and polyethylene naphtthalate (PEN).
[0015] Embodiments of the transistor 8 include partially
transparent devices, e.g., where the p-type transparent channel 10
is the only transparent thin film, as well as completely
transparent devices, i.e., where all of the thin films are formed
from transparent materials. Additional embodiments include the use
of a transparent substrate. The p-type transparent channel 10 is a
delafossite film that is undoped or lightly doped. In lightly doped
layers, the delafossite has a doping level low enough to maintain
its transparency and semiconductor performance. As an example,
lightly doped embodiments of the invention include doping levels
that result in a carrier (hole) concentration of less than
.about.10.sup.17 cm.sup.-3. The apparent optical band gap of
undoped delafossites is in the near-UV range, while heavily doped
(and conductive) films may be nearly opaque. Delafossites are the
materials having the crystal structure of CuFeO.sub.2. Example
delafossites include CuScO.sub.2, CuAlO.sub.2, CuYO.sub.2,
CuFeO.sub.2, CuCrO.sub.2, CuGaO.sub.2, CulnO.sub.2, AgCoO.sub.2,
AgGaO.sub.2, AglnO.sub.2, AgScO.sub.2, and AgCrO.sub.2. Any dopant
suitable to provide hole carriers may be used. For example,
CuYO.sub.2 and CulnO.sub.2 can be doped p-type using Ca. As another
example CuCrO.sub.2 can be doped p-type using Mg. Also, processing
that results in a slight surplus of oxygen is often used to obtain
p-type conductivity in these materials, and if controlled properly,
may produce light doping levels for use as a p-type semiconductor
channel in a transistor. Undoped and lightly doped p-type channels
will yield an enhancement-mode or weakly depletion-mode transistor
device. A negative gate voltage will draw holes from the source and
drain contacts 12, 14 to the p-type channel 10 in a region near its
interface with the gate dielectric 18. Undoped and lightly doped
delafossite films additionally have the advantage of providing a
reasonably small positive gate voltage to deplete holes from the
channel, thereby producing a relatively low gate voltage turn-off
condition.
[0016] Any number of materials may be employed for the gate
dielectric 18, gate contact 16, source 12 and drain 14. The gate
dielectric 18 for example may be a film of SiO.sub.2,
Si.sub.3N.sub.4, Al.sub.2O.sub.3, Ta.sub.2O.sub.5, HfO.sub.2,
ZrO.sub.2, or the like. The gate contact and source/drain layers
may, for example, be formed from a transparent conductor (i.e., a
p-type doped wide-band gap semiconductor) such as p-type doped GaN,
BaCu.sub.2S.sub.2, NiO, Cu.sub.2O, or various delafossites
(CuScO.sub.2, CuAlO.sub.2, CuYO.sub.2, CuFeO.sub.2, CuCrO.sub.2,
CuGaO.sub.2, CulnO.sub.2, AgCoO.sub.2, AgGaO.sub.2, AglnO.sub.2,
AgScO.sub.2, AgCrO.sub.2), or the like. Gate contact and
source/drain layers may also comprise metals such as Au, Pt, Pd,
Ni, Cu, W, Mo, Cr, Ag, In, Sn, Ga, Zn, Al, Ti, or the like.
[0017] It is beneficial to choose a source and drain contact
material to produce efficient hole injection from the source into
the p-type delafossite channel 10 at the source/channel interface.
Materials may be selected for a desired level of electrical
performance. Overall device performance is likely to vary
significantly for devices built using various source/drain contact
materials. If the source, drain and gate contact films are formed
of transparent materials, appropriate gate materials will likely
also be transparent, thereby producing a complete device that is
substantially transparent.
[0018] The delafossite channel 10 and transistor 8 have the
capability to provide hole injection in the undoped or lightly
doped channel, thereby creating a p-type device. Other transparent
semiconductors typically have a high ionization potential
(separation between valence band edge and vacuum level), e.g. in
the range of 6-8 eV. Hole injection into the transparent channel is
achieved when the source and drain contacts are formed of a
material (metal or doped semiconductor) having a work function that
is nearly equal to or greater than the ionization potential of the
channel material. However, even high work function metals, e.g.,
Au, Pd and Pt, have work functions smaller than 6 eV. The lower
ionization potential of the undoped and lightly doped delafossite
materials provides the ability meet the conditions for hole
injection.
[0019] Other exemplary embodiment transistors of the invention are
shown in FIGS. 2-6. The reference numerals from FIG. 1 are adopted
to label similar elements in FIGS. 2-6. FIG. 2 shows an exemplary
embodiment top gate p-type transparent channel thin film transistor
22 with co-planar source and drain contacts 12 and 14. FIG. 3 shows
an exemplary embodiment bottom gate p-type transparent channel thin
film transistor 24 with staggered contacts. FIG. 4 shows an
exemplary embodiment top gate p-type transparent channel thin film
transistor 26 with staggered contacts. FIG. 5 illustrates an
exemplary embodiment dual gate p-type transparent channel thin film
transistor 28. FIG. 6 illustrates another exemplary embodiment dual
gate p-type transparent channel thin film transistor 30.
[0020] FIG. 7 shows a portion of an exemplary embodiment CMOS
circuit 32 including a p-type transparent thin film transistor 34
and an n-type transparent thin film transistor 36. The p-type
transparent thin film transistor 34 includes an undoped or lightly
doped transparent thin film channel 10. The n-type transparent thin
film transistor 36 includes an n-type transparent thin film channel
38, for example ZnO. Alternative embodiments include CMOS
integrations that include non-transparent thin film transistors,
both n-type and p-type. Source 12, drain 14 and gate 16 contacts
form part of a circuit interconnect pattern in the CMOS circuit 32.
While two transistors are shown, the circuit 32 may include many
transistors. The circuit may be arranged, for example, as an
integrated circuit where transistors 34 and 36, and other
transistors in the integrated circuit act as switches. In other
embodiments, the circuit arrangement and applied voltages may
provide amplification, for example. The circuit arrangement and
applied voltages may also provide operation as a load device, for
example to provide a resistance in a CMOS circuit. In operation,
the undoped or lightly doped delafossite channel 10 uses a negative
voltage to draw holes from the source 12 and drain 14 into the
channel near the gate insulator. A range of negative voltages for a
CMOS integrated circuit arranged in a CMOS switch configuration
produces a conducting operation in the switch. As mentioned above,
reasonable positive gate voltages will deplete the channel of free
holes to turn off the transistor.
[0021] A variety of techniques are available for the formation of
p-type transparent channel thin-film transistors, and circuits that
include these transistors. Thin-film deposition techniques such as
evaporation (thermal, e-beam), sputtering (DC, RF, ion beam),
chemical vapor deposition (CVD), atomic layer deposition (ALD),
molecular beam epitaxy (MBE), and the like may be employed.
Alternate methods may also be employed, such as solution-based
deposition from a liquid precursor (spin-coating, inkjet printing,
etc). Film patterning may employ traditional photolithography
combined with etching or lift-off processes, or may use alternate
techniques such as shadow masking or direct-write patterning (i.e.,
inkjet printing).
[0022] With reference to the transistor 8 of FIG. 1, an initial
deposition on the substrate 20 is an inkjet printing of a
solution-based conductor to form the gate contact 16. The gate
contact 16 may be part of a circuit interconnect pattern, for
example patterned by a direct write process. In an alternate
embodiment, a spin coating is used to deposit gate contact
material, which is then patterned by a photolithography and etching
procedure, or perhaps a more sophisticated process such as laser
ablation. A spin coating process, for example, then deposits gate
dielectric material 18. Additional direct write steps form the
channel 10, and the gate and source contacts.
[0023] FIG. 8 shows an exemplary embodiment including a CMOS
circuit 32 in accordance with FIG. 7 combined with an integrated
device 40. In a preferred embodiment, the entire CMOS thin film
circuit 32 is formed to be transparent, i.e., p-type thin film
transistors 34 and n-type thin film transistors 36 are formed as
transparent devices. The substrate 20 is also transparent, e.g., a
transparent plastic. The integrated device 40 may be, for example,
an emissive display or include receptors for sensing or encoding or
some other function. The integrated device 40 may be in the form of
a thick film integration, e.g., silicon wafer based integration or
a group III-V based integration, bonded or otherwise attached to
the substrate 20. It might also be an additional thin film
integration formed on the backside of the substrate 20. Because the
CMOS circuit is transparent, one optical path that may be defined
to the integrated device 40 is through the CMOS circuit 32. This
provides designers with an added level of flexibility, as
electronics embodied in the CMOS thin film circuit 32 may be placed
irrespective of optical paths necessary for device operation. In
other embodiments of a display or sensor, the CMOS thin film
circuit 32 is outside of the optical paths in an integrated device.
A fully transparent CMOS thin film circuit 32 or a CMOS circuit 32
with transparent channels is less likely to be affected by light in
a display or sensor device.
[0024] While specific embodiments of the present invention have
been shown and described, it should be understood that other
modifications, substitutions and alternatives are apparent to one
of ordinary skill in the art. Such modifications, substitutions and
alternatives can be made without departing from the spirit and
scope of the invention, which should be determined from the
appended claims.
* * * * *