U.S. patent application number 10/542720 was filed with the patent office on 2006-06-08 for fast switching power insulated gate semiconductor device.
This patent application is currently assigned to North-West University. Invention is credited to Ocker Cornelis De Jager, Barend Visser.
Application Number | 20060118832 10/542720 |
Document ID | / |
Family ID | 32772476 |
Filed Date | 2006-06-08 |
United States Patent
Application |
20060118832 |
Kind Code |
A1 |
Visser; Barend ; et
al. |
June 8, 2006 |
Fast switching power insulated gate semiconductor device
Abstract
An insulated gate semiconductor device (30) includes a gate
(34), a source terminal (36), a drain terminal (38) and a variable
input capacitance at the gate. A ratio between the input
capacitance (C.sub.fiss) when the device is on and the input
capacitance C.sub.iiss when the device is off is less than two and
preferably substantially equal to one. This is achieved in one
embodiment of the invention by an insulation layer 32 at the gate
having an effective thickness d.sub.ins larger than a minimum
thickness.
Inventors: |
Visser; Barend;
(Potchefstroom, ZA) ; De Jager; Ocker Cornelis;
(Potchefstroom, ZA) |
Correspondence
Address: |
ALSTON & BIRD LLP;BANK OF AMERICA PLAZA
101 SOUTH TRYON STREET, SUITE 4000
CHARLOTTE
NC
28280-4000
US
|
Assignee: |
North-West University
1 Hoffman Street Joon Van Rooy Building
Potschefstroom
ZA
2531
|
Family ID: |
32772476 |
Appl. No.: |
10/542720 |
Filed: |
January 21, 2004 |
PCT Filed: |
January 21, 2004 |
PCT NO: |
PCT/ZA04/00005 |
371 Date: |
January 30, 2006 |
Current U.S.
Class: |
257/232 ;
257/E25.014; 257/E29.132; 257/E29.257 |
Current CPC
Class: |
H01L 29/42364 20130101;
H01L 2924/0002 20130101; H01L 29/7802 20130101; H03K 17/04123
20130101; H01L 2924/0002 20130101; H01L 2924/00 20130101; H01L
25/07 20130101 |
Class at
Publication: |
257/232 |
International
Class: |
H01L 27/148 20060101
H01L027/148 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 21, 2003 |
ZA |
2003/0552 |
Claims
1. An insulated gate device comprising a gate connected to a gate
terminal and having a variable input capacitance at the gate
terminal as the device is switched between an off state and an on
state, a ratio between a final value of the capacitance when the
device is on and an initial value of the capacitance when the
device is off is smaller than 2.0.
2. A device as claimed in claim 1 comprising a power metal oxide
silicon field effect transistor (MOSFET).
3. A device as claimed in claim 1 wherein the ratio is less than
1.5.
4. A device as claimed in claim 3 wherein the ratio is
substantially equal to 1.
5. A device as claimed in claim 1 comprising a capacitor connected
between the gate terminal and the gate of the device.
6. A device as claimed in claim 2 wherein the MOSFET has a vertical
structure in that the gate and a source of the device are provided
on one face of a chip body of the device and a drain of the MOSFET
is provided on an opposite face of the body.
7. A device as claimed in claim 6 wherein the capacitor is
integrated on the chip body.
8. A device as claimed in claim 7 wherein the capacitor is
superimposed on the gate of the MOSFET.
9. A device as claimed in claim 5 wherein the capacitor is a
discrete component connected in series between the gate and the
gate terminal and packaged in the same package.
10. A device as claimed in claim 5 wherein the gate is connected
directly to a fourth terminal of the device.
11. A device as claimed in claim 9 wherein biasing resistors
connected to the gate are included in the same package.
Description
TECHNICAL FIELD
[0001] THIS invention relates to insulated gate semiconductor
devices such as metal oxide silicon field effect transistors
(MOSFET's), more particularly to such devices for use in power
switching applications and to a method of driving such devices.
BACKGROUND ART
[0002] In known MOSFET structures, it is presently preferred to
minimize the gate voltage V.sub.GS required for switching of the
device and which then implies a relatively large input gate
capacitance.
[0003] Capacitance inherent in the gate structures of insulated
gate devices limits the switching speeds of these devices. It is
also well known that the Miller effect has an influence on the
input capacitance at the gate of devices of the aforementioned kind
in that the input capacitance of a typical commercially available
MOSFET varies during switching of the device. The input capacitance
has a first value C.sub.iiss when the device is off and a second
value C.sub.fiss when the device is on. The ratio of the second and
first values for a known and commercially available IRF 740 power
MOSFET is in the order of 2.5. It has been found that such a ratio
impairs the switching speed of these devices.
[0004] The total switching time T.sub.s of the IRF 740 MOSFET to
switch on is made up by the sum of a turn-on delay time T.sub.don
of about 14 ns and a drain source voltage fall time T.sub.f of
about 24 ns and is equal to about 38 ns. The corresponding time to
switch off is about 77 ns. These times are too long for some
applications.
OBJECT OF THE INVENTION
[0005] Accordingly, it is an object of the present invention to
provide an insulated gate device and method and circuit of driving
such a device with which the applicant believes the aforementioned
disadvantages may at least be alleviated.
SUMMARY OF THE INVENTION
[0006] According to the invention an insulated gate device
comprises a gate connected to a gate terminal and having a variable
input capacitance at the gate terminal as the device is switched
between an off state and an on state, a ratio between a final value
of the capacitance when the device is on and an initial value of
the capacitance when the device is off is smaller than 2.0.
[0007] The aforementioned ratio is preferably less than 1.5, more
preferably less than 1.4, even more preferably less than 1.3, still
more preferably less than 1.2 and most preferably substantially
equal to 1.
[0008] The device may comprise a semiconductor device, preferably a
field effect transistor (FET) more preferably a power metal oxide
silicon field effect transistor (MOSFET) such as a V-MOS, D-MOS and
U-MOS.
[0009] The MOSFET may have a vertical structure in that the gate
and a source of the device are provided on one face of a chip body
of the device and a drain of the MOSFET is provided on an opposite
face of the body.
[0010] The device may comprise a capacitor connected between the
gate terminal and the gate of the device.
[0011] The capacitor may be integrated on the chip body and in one
embodiment may be superimposed on the gate of the device.
[0012] Alternatively, the capacitor is a discrete component
connected in series between the gate and the gate terminal and
packaged in the same package.
[0013] The gate may be connected directly to a fourth terminal of
the device.
[0014] In this specification the invariant device parameter
(.beta.) is used to denote the effective dielectricum thickness of
a conduction channel of the device in the off state, which is
defined as the product of an effective gate capacitance area (A)
and the difference between an inverse of a first value of a gate
capacitance of the insulated gate device, that is when the device
is off and an inverse of a second value of the gate capacitance,
that is when the device is on. That is:
.beta..ident.A(1/C.sub.iiss-1/C.sub.fiss)=.varies..sub.max.
[0015] According to one aspect of the invention there is provided
an insulated gate device comprising a gate and an insulation layer
at the gate, the layer having an effective thickness (d) of at
least a quotient of the device parameter as defined and a ratio of
maximum charge accommodatable on the gate and a minimum charge
required on the gate for complete switching, minus one (1). That
is:
d.gtoreq.d.sub.min.apprxeq..beta./[(Q.sub.G(max)/Q.sub.G(min))-1]
where Q.sub.G(max) is the maximum allowable steady state charge for
safe operation and Q.sub.G(min) is the minimum charge required for
complete switching.
[0016] According to another aspect of the invention there is
provided an insulated gate device comprising a gate, the device
having a capacitance at the gate which is a function of the
effective thickness of an insulation layer at the gate, the
effective thickness of the layer being selected to ensure that a
first ratio between a final value of the capacitance when the
device is on and an initial value of the capacitance when the
device is off is smaller or equal to a second ratio of a maximum
charge receivable on the gate and a charge required to reach a
threshold voltage of the gate of the device.
[0017] According to yet another aspect of the invention there is
provided an insulated gate device comprising a gate, the device
having a capacitance at the gate which is a function of the
effective thickness of an insulation layer at the gate, the
effective thickness of the layer being selected to ensure that a
first ratio between a final value of the capacitance when the
device is on and an initial value of the capacitance when the
device is off is smaller or equal to a second ratio of a maximum
voltage applyable to the gate and a threshold voltage required on
the gate to switch the device on.
[0018] According to yet another aspect of the invention there is
provided a method of driving an insulated gate semiconductor
device, the device comprising an insulation layer at a gate thereof
providing a capacitance which varies between an initial value when
the device is off and a final value when the device is on, the
method comprising the step of depositing at least a Miller charge
on the gate while the capacitance has said initial value.
[0019] The method preferably comprises the step of depositing
substantially sufficient charge for a desired steady state switched
on state of the device on the gate while the capacitance has said
initial value.
[0020] The invention also extends to a drive circuit for a device
as herein defined and/or described.
BRIEF DESCRIPTION OF THE ACCOMPANYING DIAGRAMS
[0021] The invention will now further be described, by way of
example only, with reference to the accompanying diagrams
wherein:
[0022] FIG. 1 is a schematic representation of a known insulated
gate semiconductor device in the form of a power MOSFET;
[0023] FIG. 2(a) is a diagrammatic representation of a gate
structure of the MOSFET while it is off;
[0024] FIG. 2(b) is a diagrammatic representation of a gate
structure of the MOSFET when it is partially on;
[0025] FIG. 2(c) is a diagrammatic representation of a gate
structure of the MOSFET when it is fully switched on;
[0026] FIG. 3 is a schematic representation of a first embodiment
of a power MOSFET according to the invention;
[0027] FIG. 4 is a typical graph for the steady state of
gate-to-source voltage against total gate charge marked A of a
conventional MOSFET as well as various similar graphs marked B for
MOSFET's according to the invention;
[0028] FIG. 5 is a graph of total switching time against a ratio of
initial charge transferred to the gate and the Miller charge of a
variety of MOSFET's;
[0029] FIG. 6 is a graph of drain-source rise time against turn-on
delay time of a variety of MOSFET's;
[0030] FIG. 7 is a graph of minimum and maximum gate source
voltages required on a MOSFET according to the invention against
total switching time;
[0031] FIG. 8(a) are oscillographs of V.sub.GS and V.sub.DS against
time for a MOSFET with a ratio
C.sub.fiss/C.sub.iiss.apprxeq.2.16;
[0032] FIG. 8(b) are similar graphs for a MOSFET with a ratio
C.sub.fiss/C.sub.iiss.apprxeq.1.63;
[0033] FIG. 8(c) are similar graphs for a MOSFET with a ratio
C.sub.fiss/C.sub.iiss.apprxeq.1.34;
[0034] FIG. 8(d) are similar graphs for a MOSFET with the ratio
C.sub.ffiss/C.sub.iiss.apprxeq.1.17;
[0035] FIG. 9 is a schematic representation of a second embodiment
of the MOSFET according to the invention;
[0036] FIG. 10 is a schematic representation of a third embodiment
of the MOSFET according to the invention;
[0037] FIG. 11 is a block diagram of another embodiment of the
device according to the invention; and
[0038] FIG. 12 is a basic diagram of drive circuit for a device
according to the invention.
DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION
[0039] A known insulated gate device in the form of a known power
metal oxide silicon field effect transistor (MOSFET) is generally
designated by the reference numeral 10 in FIG. 1.
[0040] The MOSFET 10 comprises a gate 12, a drain 14 and a source
16. The device 10 has a gate capacitance CG between the gate and
the source.
[0041] It is well known that when a voltage V.sub.GS is applied to
the gate as shown at 80 in FIG. 8(a), charge is deposited on the
gate causing the device to switch on and a voltage V.sub.DS to
switch from a maximum value shown at 82 to a minimum value shown at
84. Similarly, when the charge is removed from the gate, the device
is switched off and the voltage V.sub.DS switches to the maximum
value.
[0042] The total switching time T.sub.s (illustrated in FIG. 8(a))
is constituted by the sum of a turn-on delay time T.sub.don and a
rise time T.sub.r. The turn-on delay time is defined to be the time
between % rise of the gate-to-source voltage V.sub.GS above 10% of
its maximum value and the onset of drain-to-source conduction, that
is when the voltage V.sub.DS has decreased by 10%. The rise time is
defined as the time interval corresponding to a decrease in
V.sub.DS from 90% to 10% of its maximum value when the device is
switched on.
[0043] Referring to FIGS. 2(a) to 2(c), in the known devices, the
gate capacitance C.sub.G may be modelled as effectively comprising
two capacitors C.sub.g and C.sub.c in series. As shown in FIGS.
2(a) to 2(c) the first capacitor C.sub.g is an invariable capacitor
and its value scales to 1/d, being the effective thickness (d) of
an insulation layer 18 at the gate of the device. The second
capacitor C.sub.c is a variable capacitor having a value of .infin.
when the device is switched on as shown in FIG. 2(c), a value of
A/.varies..sub.max when the device is off as shown in FIG. 2(a) and
a value of A/.varies..sub.max (with
0<.varies.<.varies..sub.max) while the capacitance changes,
i.e. the channel switches off or on. The gate capacitance C.sub.G
may hence be written as: C G = .times. 1 / [ 1 / C g .function. ( d
) + 1 / C c .function. ( .varies. ) ] = .times. A / ( d + .varies.
) ##EQU1## where A is an effective area, which includes proper
normalization constants. Thus, .varies. is a maximum
(.varies..sub.max) when the device is switched off as shown in FIG.
2(a) and .varies.=0 when the device is switched on as shown in FIG.
2(c).
[0044] Hence, the device has a gate or input capacitance with a
first value C.sub.iiss when the device is off and a second value
C.sub.fiss when the device is on. The capacitance retains the first
value until the Miller effect takes effect.
[0045] An effective maximum conduction channel dielectricum
thickness (.beta.)=.varies..sub.max is defined, which is
proportional to a difference in the inverse of the gate capacitance
when the device is off C.sub.iiss and when the device is on
C.sub.fiss, that is:
.beta..ident.A(1/C.sub.iiss-1/C.sub.fiss)=.varies..sub.max. The
ratio C.sub.fiss/C.sub.iiss may be written as d + .times. .varies.
max d . ##EQU2##
[0046] As shown in FIG. 3, according to the invention by increasing
the effective thickness d.sub.ins of the insulation layer 32 at the
gate 34 and hence by decreasing the gate capacitance C.sub.G, the
total switching time T.sub.s of a MOSFET 30 may be decreased. A
minimum value for the effective thickness d.sub.ins is given by:
d.sub.ins.gtoreq..beta./[(Q.sub.G(max)/Q.sub.G(min))-1] wherein
Q.sub.G(min) is the minimum charge required for complete switching
and wherein Q.sub.G(max) is the maximum allowable gate charge on
the device which includes a safety margin. Destruction will occur
when Q.gtoreq.Q.sub.G(max).
[0047] Defining V.sub.GS(min) as the minimum gate voltage for
complete switching and V.sub.GS(max) as the maximum allowable gate
voltage on the device, before damage to the device, it is known
that Q.sub.G(max)/Q.sub.G(min)>V.sub.GS(max)/V.sub.GS(min). This
inequality implies a slightly larger limit than that calculated
from the charge ratios Q.sub.G(max)/Q.sub.G(min):
d.sub.ins.gtoreq..beta./[(V.sub.GS(max)/V.sub.GS(min))-1]
[0048] With this minimum effective thickness for d.sub.ins, the
switching time of the device is mainly limited by the gate source
inductance and capacitance.
[0049] By increasing d.sub.ins, beyond this minimum, allows for
reducing the rise or fall time by compensating for the source
inductance L.sub.s voltage .epsilon..sub.s during switching and
which is: .epsilon.s=L.sub.sdi/dt+iR.sub.s
.epsilon.s.sub.(max).apprxeq.L.sub.sI.sub.DS(max)/T.sub.s+I.sub.DS(max)R.-
sub.s.
[0050] In Table 1 there are provided relevant details of four
differently modified MOSFET's with progressively decreasing gate
capacitance, C.sub.G. TABLE-US-00001 TABLE 1 Turn-on Initial &
Final Delay Time Modified Input Gate Predicted Measured Gate
Applied Charge & Switching Capacitance Gate Transferred
Observed Time C.sub.iiss, C.sub.fiss C.sub.fiss Voltage
C.sub.iissV.sub.GS & C.sub.fissV.sub.GS T.sub.d(on) T.sub.s No.
(nF) C.sub.iiss V.sub.GS (volt) (nC) (ns) (ns) i 1.2 2.6 2.16 15 18
40 6.3 6 38 (20 ns/div) ii 0.86 1.4 1.63 32 28 45 5.3 5 20 (20
ns/div) iii 0.58 0.78 1.34 120 70 94 4.4 <2 <4 (10 ns/div) iv
0.35 0.41 1.17 200 70 82 3.4 <2 <4 (10 ns/div)
[0051] For a conventional IRF 740 MOSFET:
.epsilon..sub.s(max).apprxeq.7.4 nH (40 A/27 ns)+4 volt=15 volt
V.sub.G(internal).apprxeq.V.sub.GS(max)-.epsilon..sub.s(max)=20
volt-15 volt=5 volt
[0052] For the device in row iv of Table 1
.epsilon..sub.s(max).apprxeq.7.4 nH (40 A/2.5 ns)+5 volt=123 volt
V.sub.G(internal).apprxeq.V.sub.GS(max)-.epsilon..sub.s(max).apprxeq.200
volt-123 volt=77 volt
[0053] From this example it is clear that V.sub.G(internal) is
still larger than the modified threshold gate voltage
V.sub.GSTM=V.sub.GS(tmin)=73 volt, shown in FIG. 4, and the slow
rise time due to the Miller effect is thus effectively
counteracted. It follows that minimization of the product
L.sub.sC.sub.iiss minimizes the switching time T.sub.s of the
device, assuming the combined gate and source serves resistance is
negligible.
[0054] If a gate voltage, V.sub.GS, substantially larger than the
threshold gate voltage, V.sub.GST, is supplied in a time much
shorter than the turn-on delay time, the latter may be approximated
as: T.sub.don.apprxeq.(2/3)(L.sub.sC.sub.iiss).sup.1/2.
[0055] It can be shown that: T.sub.s.varies.1/d.sub.ins.sup.1/2
which indicates that the total switching time is reduced by
increasing the effective thickness d.sub.ins of layer 32.
[0056] Another important feature of the invention is that at least
a minimum required charge Q.sub.G(min) or Miller charge (see FIG.
4) must be transferred to the gate while the gate capacitance
assumes its lower initial value of C.sub.iiss rather when the
larger input capacitance C.sub.fiss determines the final switched
state of the MOSFET. Hence the charge to be transferred is
Q.sub.G=V.sub.GSC.sub.iiss.gtoreq.Q.sub.G(min).
[0057] Thus, the following minimum source to gate voltage must be
applied. V.sub.GS.gtoreq.V.sub.GS(min)=Q.sub.G(min)/C.sub.iiss.
[0058] Also, Q.sub.G=V.sub.GSC.sub.fiss.ltoreq.Q.sub.G(max) [0059]
and the corresponding voltage limit is given by
V.sub.GS.ltoreq.V.sub.GS(max)=Q.sub.G(max)/C.sub.fiss,
[0060] This could also be written as:
C.sub.fiss/C.sub.iiss.ltoreq.Q.sub.G(max)/Q.sub.G(min) or
C.sub.fiss/C.sub.iiss.ltoreq.V.sub.GS(max)/V.sub.GS(min).
[0061] Oscillograms illustrating V.sub.GS and V.sub.DS against time
during switching on for each of the devices referenced i to iv in
Table 1 are shown in FIGS. 8(a) to 8(d) respectively. The decrease
in gate capacitance is clear from the second column in the Table,
and the larger required input V.sub.GS and decreasing switching
times are clear from both the Table and the oscillograms.
[0062] The last two devices iii and iv in Table 1 with minimized
gate capacitance and wherein the ratio
C.sub.fiss/C.sub.iiss.ltoreq.1,34, represent MOSFET's close to
optimum, since the initial gate charge is already more than the
minimum gate charge Q.sub.G(min) (shown in FIG. 4 and which for a
typical MOSFET is in the order of 30 nC) required for complete
switching. The increased gate to source input voltage V.sub.GS and
spectacular drop in total switching times T.sub.S are
noticeable.
[0063] In FIG. 4, comparative graphs for a known MOSFET is shown at
A and for MOSFET's according to the invention at B. The ratio
C.sub.fiss/C.sub.iiss for the known IRF 740 MOSFET is in the order
of 2.5 whereas the same ratio for the last device according to the
invention in Table 1 is 1.17. The device according to the invention
has a total switching time of <4 ns which is about an order
faster than the 38 ns of the known and comparable IRF 740
MOSFET.
[0064] In FIG. 5 there is shown a graph of total switching time as
a function of the initial gate charge relative to the minimum gate
charge Q.sub.G(min) The circle at 40 represents standard operation
of an IRF 740 MOSFET. However, the circles at 42 and 44 illustrate
the improved operation of the MOSFET's referenced iii and iv in
Table 1.
[0065] In FIG. 6 there is shown a graph of rise time T, against
turn-on delay time T.sub.don for a plurality of different devices.
The mark at 50 indicates standard operation of an IRF 740 MOSFET
and the circles 52 and 54 indicate the improvement in total
switching time T.sub.s of the devices referenced iii and iv in
Table 1 to a point where the rise time becomes negligible and the
total switching time T.sub.s approximates the turn-on delay time
T.sub.don.
[0066] It can further be shown that the product of V.sub.GS and the
square of the total switching time T.sub.s is band limited as
follows:
(2.pi./3).sup.2Q.sub.G(min)L.sub.s.ltoreq.V.sub.EST.sub.S.ltoreq.(2.pi./3-
).sup.2Q.sub.G(max)L.sub.S which means that the operating voltage
V.sub.GS of the device according to the invention (which is much
higher than the corresponding voltage for prior art devices) is
limited as follows:
(2.pi./3).sup.2Q.sub.G(min)L.sub.s/T.sub.s.sup.2.ltoreq.V.sub.G-
S.ltoreq.(2.pi./3)Q.sub.G(max)L.sub.s/T.sub.s.sup.2 and as
illustrated in FIG. 7. The internal source resistance R.sub.s has a
negligible effect on these expressions and is therefore omitted for
better clarity.
[0067] Hence, by minimizing the product of Miller charge or
Q.sub.G(min) and L.sub.s, reduced total switching times T.sub.s and
required operating voltages V.sub.GS may be achieved.
[0068] In FIG. 9 there is shown a further embodiment of the device
according to the invention and designated 90. The device comprises
a gate 92, connected to a gate terminal 94. The insulation layer
with increased effective thickness d.sub.ins is shown at 96.
Conventional source and drain terminals are shown at 98 and 99
respectively. A further and so-called floating gate 95 is connected
to a fourth and user accessible terminal 97.
[0069] In FIG. 10, yet another embodiment of the device according
to the invention is shown at 100. In this case, the further gate 95
is not connected to a user accessible terminal, similar to terminal
97, but biasing resistors 102 and 104 may be provided as discrete
components or integral with the chip body 106.
[0070] In FIG. 11, still a further embodiment of the device is
shown at 110. The device 110 comprises a conventional MOSFET 112
having a gate 114. A capacitor 116 is connected in series between
the gate and a gate terminal 118 of the device. The drain and
source of the MOSFET are connected to a drain terminal 120 and
source terminal 122 respectively. The device is packaged in a
single package 124 providing the aforementioned terminals. An
optional fourth terminal 124 connected to the gate 114 may also be
provided. The capacitor 116 may be integrated with the MOSFET on a
single chip. In other embodiments, the capacitor may be a discrete
capacitor, but packaged in the same package 124. In still other
embodiments, the optional fourth terminal may be omitted and
biasing resistors between the gate terminal and the gate and
between the gate and the source may be provided in the same
package.
[0071] In FIG. 12 there is shown a diagram of a drive circuit 130
for the device 30, 90, 100 and 110 according to the invention. The
drive circuit comprises a voltage source 132 (typically 50V-600V
and which may even exceed V.sub.DD) and a fast switching device 134
connected in a circuit and in close proximity to the gate terminal
of the device according to the invention to reduce unwanted
inductance in the gate source circuit.
[0072] In use, the fast switching device 134 is controlled to apply
a voltage which is sufficiently larger than the threshold voltage
of the device to the gate of the device. As is clear from table 1,
this voltage is larger than the voltage required in conventional
devices. Due to the reduced LCR parameters in the gate source
circuit, charge transfer to the gate of the device will be faster
than with conventional devices which results in the faster
switching times in the drain source circuit as shown in table
1.
* * * * *