U.S. patent application number 10/904677 was filed with the patent office on 2006-05-25 for high surface area aluminum bond pad for through-wafer connections to an electronic package.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Richard J. Rassel, Edmund J. Sprogis.
Application Number | 20060110905 10/904677 |
Document ID | / |
Family ID | 36461452 |
Filed Date | 2006-05-25 |
United States Patent
Application |
20060110905 |
Kind Code |
A1 |
Adkisson; James W. ; et
al. |
May 25, 2006 |
HIGH SURFACE AREA ALUMINUM BOND PAD FOR THROUGH-WAFER CONNECTIONS
TO AN ELECTRONIC PACKAGE
Abstract
A bond pad for effecting through-wafer connections to an
integrated circuit or electronic package and method of producing
thereof. The bond pad includes a high surface area aluminum bond
pad in order to resultingly obtain a highly reliable, low
resistance connection between bond pad and electrical leads.
Inventors: |
Adkisson; James W.;
(Jericho, VT) ; Gambino; Jeffrey P.; (Westford,
VT) ; Jaffe; Mark D.; (Shelburne, VT) ;
Rassel; Richard J.; (Colchester, VT) ; Sprogis;
Edmund J.; (Underhill, VT) |
Correspondence
Address: |
SCULLY, SCOTT, MURPHY & PRESSNER
400 GARDEN CITY PLAZA
GARDEN CITY
NY
11530
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
New Orchard Road
Armonk
NY
|
Family ID: |
36461452 |
Appl. No.: |
10/904677 |
Filed: |
November 23, 2004 |
Current U.S.
Class: |
438/612 ;
257/E23.011; 257/E23.02; 438/106; 438/613; 438/614 |
Current CPC
Class: |
H01L 2924/01047
20130101; H01L 24/05 20130101; H01L 2924/014 20130101; H01L
2924/01014 20130101; H01L 23/481 20130101; H01L 24/03 20130101;
H01L 2924/01022 20130101; H01L 2924/01073 20130101; H01L 2924/01046
20130101; H01L 2924/01082 20130101; H01L 2924/01033 20130101; H01L
2924/01074 20130101; H01L 2924/01076 20130101; H01L 2224/0401
20130101; H01L 2924/01019 20130101; H01L 2924/14 20130101; H01L
2924/01078 20130101; H01L 2924/3011 20130101; H01L 2924/01024
20130101; H01L 23/3114 20130101; H01L 24/02 20130101; H01L
2924/01079 20130101; H01L 2924/01028 20130101; H01L 2924/01072
20130101; H01L 2924/1461 20130101; H01L 2224/05569 20130101; H01L
2924/01013 20130101; H01L 2924/01027 20130101; H01L 2924/01029
20130101; H01L 2924/1461 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
438/612 ;
438/613; 438/614; 438/106 |
International
Class: |
H01L 21/44 20060101
H01L021/44; H01L 21/50 20060101 H01L021/50 |
Claims
1. An arrangement comprising a bond pad for effectuating a
through-wafer connection to an integrated circuit chip or
electronic package, said bond pad incorporating a high surface
contact area forming a low-electrical resistance connection between
said bond pad and electrical leads of said integrated circuit or
electronic package.
2. An arrangement comprising a bond pad as claimed in claim 1,
wherein said high surface contact area comprises via bars formed at
a bottom surface of said bond pad for increasing the contact area
of said bond pad.
3. An arrangement comprising a bond pad as claimed in claim 2,
wherein said bond pad is constituted of aluminum and said via bars
are constituted of materials which are resistant to corrosion from
applicable ambient conditions, and which are selected from the
group of metals consisting of tungsten, a combination of tungsten
and aluminum, Cr, Au, Ni, NiMoP, Co, CoWP or CoWB.
4. An arrangement comprising a bond pad as claimed in claim 2,
wherein a plurality of said bond pads are each connected to
electrical leads, a plurality of slotted said vias being arranged
below each of said bond pads, and via bars constituted of materials
which are resistant to corrosion from applicable ambient
conditions, and which are selected from the group of metals
consisting of tungsten or a combination of tungsten and aluminum,
Cr, Au, Ni, NiMoP, Co, CoWP or CoWB, being located in each of said
vias for increasing the contact areas of said bond pads.
5. An arrangement comprising a bond pad as claimed in claim 1,
wherein an isotropic etch is implemented at an angular relationship
to said bond pad so as to increase an electrical side contact
surface of said bond pad.
6. An arrangement comprising a bond pad as claimed in claim 1,
wherein a metal mask-forming layer is provided on the surface of
said bond pad, and the surface area of said bond pad is
increased.
7. An arrangement comprising a bond pad as claimed in claim 6,
wherein a shadow mask provides said metal mask-forming layer of
evaporated metal to be deposited on the surface of said bond pad,
or said metal is deposited by a selective plating process, such as
electroplating or electroless plating.
8. An arrangement comprising a bond pad as claimed in claim 6,
wherein an isotropic etch is implemented at an angular relationship
to said bond pad so as to increase an electrical side contact
surface of said bond pad.
9. An arrangement comprising a bond pad as claimed in claim 6,
wherein said mask-forming layer is consisting of a metal selected
from the group of materials consisting of aluminum, gold, silver,
silicon-based solder, lead-based solder, palladium, platinum,
chromium, nickel, copper or alloys of said materials.
10. A method of producing low-electrical resistance connections to
a bond pad, comprising providing an aluminum bond pad for
effectuating a through-wafer connection to an integrated circuit
chip or electronic package, and imparting a high-surface contact
area to said bond pad to form said low-electrical resistance
connection between said bond pad and electrical leads of said
integrated circuit or electronic package.
11. A method as claimed in claim 10, wherein said high surface
contact area comprises forming via bars at a bottom surface of said
bond pad for increasing the contact area of said bond pad.
12. A method as claimed in claim 11, wherein said via bars are
constituted of materials which are resistant to corrosion from
applicable ambient conditions, and which are selected from the
group of metals consisting of tungsten, a combination of tungsten
and aluminum, Cr, Au, Ni, NiMoP, Co, CoWP or CoWB.
13. A method as claimed in claim 11, wherein a plurality of said
bond pads are each connected to electrical leads, a plurality of
slotted said vias being arranged below each of said bond pads, and
said via bars are constituted of materials which are resistant to
corrosion from applicable ambient conditions, and which are
selected from the group of metals consisting of tungsten, a
combination of tungsten and aluminum, Cr, Au, Ni, NiMoP, Co, CoWP
or CoWB, and are located in each of said vias for increasing the
contact areas of said bond pads.
14. A method as claimed in claim 10, wherein an isotropic etch is
implemented at an angular relationship to said bond pad so as to
increase an electrical side contact surface of said bond pad.
15. A method as claimed in claim 10, wherein a metal mask-forming
layer is provided on the surface of said bond pad, and the surface
area of said bond pad is increased.
16. A method as claimed in claim 15, wherein a shadow mask provides
said metal mask-forming layer of evaporated metal to be deposited
on the surface of said bond pad, or said metal is deposited by a
selective plating process, such as electroplating or electroless
plating.
17. A method as claimed in claim 15, wherein an isotropic etch is
implemented at an angular relationship to said bond pad so as to
increase an electrical side contact surface of said bond pad.
18. A method as claimed in claim 15, wherein said mask-forming
layer is constituted of a metal selected from the group of
materials consisting of aluminum, gold, silver, silicon-based
solder, lead-based solder, palladium, platinum, chromium, nickel,
copper or alloys of said materials.
19. An integrated circuit chip comprising a side chip surface, a
bond pad having a first surface extending coplanarly with said side
chip surface; an electrical lead extending adjacent to said bond
pad, said electrical lead includes a surface extending coplanarly
with said side chip surface so as to increase a contact surface
area for electrical coupling to said bond pad forming a
low-electrical resistance connection therebetween.
20. An integrated circuit chip as claimed in claim 19, wherein said
increased surface contact area comprises via bars formed at a
bottom surface of said bond pad for increasing the contact area of
said bond pad.
21. An integrated circuit chip as claimed in claim 20, wherein said
bond pad is constituted of aluminum and said via bars are
constituted of materials which are resistant to corrosion from
applicable ambient conditions, and which are selected from the
group of metals consisting of tungsten, a combination of tungsten
and aluminum, Cr, Au, Ni, NiMoP, Co, CoWP or CoWB.
22. An integrated circuit chip as claimed in claim 20, wherein a
plurality of said bond pads are each connected to electrical leads,
a plurality of slotted said vias being arranged below each of said
bond pads, and via bars constituted of materials which are
resistant to corrosion from applicable ambient conditions, and
which are selected from the group of metals consisting of tungsten,
a combination of tungsten and aluminum, Cr. Au, Ni, NiMoP, Co, CoWP
or CoWB, being located in each of said vias for increasing the
contact areas of said bond pads.
23. An integrated circuit chip as claimed in claim 20, wherein an
isotropic etch is implemented at an angular relationship to said
bond pad so as to increase an electrical side contact surface of
said bond pad.
24. An integrated circuit chip as claimed in claim 20, wherein a
metal mask-forming layer is provided on the surface of said bond
pad, and the surface area of said bond pad is increased by
evaporation of metal through a shadow mask, or by selective plating
processes, such as electroplating or electroless plating.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to the provision of a bond pad
for effecting through-wafer connections to an integrated circuit or
electronic package, and which pad comprises a high surface area
aluminum bond pad in order to resultingly obtain a highly reliable,
low resistance connection between bond pads and electrical
leads.
[0003] In the current state-of-the-technology, through-wafer
connections are frequently employed in the formation of advanced
types of electronic packages, for instance, such as, but not
limited to, 3D packaging, MEMS packaging, or CMOS imager packaging.
In particular, the process which is utilized for these connections
is designed to etch a via through the rear side of the wafer and
through the bond pads, so as to expose the edges of the respective
bond pads. Leads are then formed so as to connect the edges of the
bond pads to solder bumps, which are arranged on the rear sides of
the electronic package. Thus, for multilevel aluminum (Al) wiring,
multiple levels are employed in order to form the connection
between the leads and the bond pads so as to be able to obtain low
resistance electrical connections. However, when employing (Cu)
copper wiring, this particular approach is subject to a poor or
relatively low degree of reliability in the use of multiple Cu
levels to form connections between the bond pads and leads, as a
consequence of oxidation and corrosion of the copper material. A
single aluminum pad is frequently employed as a final metal layer
in Cu interconnect processes. Nevertheless, the use of such a
single aluminum bond pad in effecting a connection to the leads may
result in the formation of a high resistance connection, which has
an adverse effect on reliability and may generate a high degree of
heat shortening the service life of the electronic package in which
it is installed.
[0004] Various aspects of the applicable technology have been
developed, and prior art publications are in existence, which
address themselves to the concept of employing vias under bond pads
to provide for through-wafer connections or for the protection of
underlying dielectrics. However, these constructions require either
an extra mask, for instance, such as for through-wafer connections,
or alternatively, necessitate that a metal layer be arranged
beneath the via for the protection of underlying dielectrics.
[0005] 2. Discussion of the Prior Art
[0006] Chisholm, et al., U.S. Pat. No. 6,586,839 B2 disclose the
provision of vias beneath bond pads, which vias are intended to
protect low-k dielectrics from sustaining any damage. These vias
land on the underlying metal; and are required to employ this
structure in order to mechanically strengthen the latter. This,
however, requires the provision of arranging metal below the vias,
inasmuch as such metal would of necessity be copper and would be
subject to being exposed to ambient conditions and thereby
susceptible to corrosion. In contrast to this prior art, which is
plainly used for mechanical or structural integrity of low-k
dielectrics beneath a bond pad, the inventive approach is intended
to improve the electrical characteristics and increase cross
section area of contacts from pads to leads on the backside of
wafer.
[0007] Rolfson, U.S. Pat. No. 6,060,378 discloses the formation of
a thick bond pad by adding a dielectric and a mask, and forming a
thick damascene metal pad on top of a standard bond pad. Although
this is somewhat similar to a general aspect of the present
invention, in which the latter adds metal to the top of a bond pad
using a shadow mask or selective plating, in contrast with the
prior art the inventive approach resides in that there is an
elimination of any deposit of additional layers over the remainder
of the chip, inasmuch as such additional layers would be
detrimental to the microlens, or similar MEMS structures.
[0008] With regard to the disclosures of Siniaguine, U.S. Pat. No.
6,639,303 B2; Cheng, et al., U.S. Patent Publication No.
2004/0141421 A1; and Pogge, et al., U.S. Patent Publication No.
2004/0097002 A1, these all require the application of an extra mask
in order to produce through wafer vias below a bond pad. These vias
extend all the way through a silicon wafer, whereas contrastingly,
pursuant to the invention the via only extends through the
dielectric on top of the silicon (Si), so as to structurally,
distinguish over these patent publications.
SUMMARY OF THE INVENTION
[0009] To the contrary, in order to provide clear distinctions and
advantages over the current state-of-the-art, pursuant to the
invention there are employed vias or via bars beneath an aluminum
bond pad in order to increase the cross-sectional contact area of
metal, such as when there is provided a cut through the bond pad
for electronic packaging. Pursuant to the present invention, there
are provided advantages over the prior art in that there is
eliminated the need for an extra mask in order to form the via or
via bar, and whereas moreover, there are eliminated the arranging
of metal lines beneath the via bar, this being an undesirable
aspect as is presented in the prior art, inasmuch as such metal
lines would normally be constituted of copper and would be exposed
to an ambient environment during package forming and, consequently,
subject to potentially corrosive conditions.
[0010] Accordingly, an object of the present invention is directed
to utilizing various novel and unique aspects in that there are
provided via bars under a bond pad pursuant to the first
embodiment, and in an alternative manner, according to another
embodiment there is added metal to the top of a bond pad in order
to provide an extended or additional contact area to thereby
produce a high surface area aluminum bond pad for the formation of
a through-wafer connection to an electronic package.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Reference may now be made to the following detailed
description of the preferred embodiments of the invention, taken in
conjunction with the accompanying drawings; in which:
[0012] FIGS. 1A through 1C describe sequential steps in the
formation of the etching of vias in the back sides of an electronic
package, and then forming the leads to connect the edges of bond
pads to solder bumps in accordance with the prior art;
[0013] FIGS. 2A and 2B illustrate, respectively, perspective and
enlarged views of a section of the bond pads and leads after
singulation pursuant to the prior art;
[0014] FIG. 3 illustrates an enlarged diagrammatic detail of a
portion of the bond pads and lead connection pursuant to the prior
art;
[0015] FIGS. 4A through 4C illustrate sequential steps in the
formation of a first embodiment of a structure utilizing via bars
underneath bond pads pursuant to the invention;
[0016] FIGS. 5A and 5B illustrate a further embodiment showing
sequential steps of adding metal to the top of a bond pad,
respectively, before and after package via etch pursuant to the
invention; and
[0017] FIGS. 6A and 6B illustrate, diagrammatically, plan and end
views of typical corrugated aluminum pads with slotted vias
therebeneath.
DETAILED DESCRIPTION OF THE INVENTION
[0018] Referring to FIGS. 1A through 1C of the drawings, setting
forth a prior art example of producing an electronic package, this
is directed to a process for forming through-wafer connections by
etching a via through the backside of a wafer and through bond
pads, so as to expose the edges of the pads.
[0019] Hereby, as shown in FIG. 1A of the drawings, a front glass
plate 10 has a plurality of spacer rims 12 attached thereto, and a
die 14 is located to form a cavity 16 between the backside 18 of
the front glass plate 10 and a silicon pad 20, etches 22 are
implemented from the backside of the die so as to form I/Os
(inputs/outputs) to the die. Thereafter, as shown in FIG. 1B of the
drawings, a layer of glue 24 is employed to attach a back glass
plate 26, and notching at angles to a normal is implemented for
forming the initial structure 30 prior to singulation (by
dicing).
[0020] Thereafter, as shown in FIG. 1C of the drawings, BGA solder
bumps 32 are suitably fastened to the back plate and leads 34,
which are connected extending along the notched surface 36 so as to
connect to bond pads 38 formed beneath the spacer rim portions 12.
Thereafter, final dicing along lines A is implemented to provide
for singulation and to form discrete structures, as shown in FIGS.
2A and 2B of the drawings. In this instance, as illustrated, epoxy
40 attaches the silicon 20 to the back glass plate 26 and
attachment surfaces are also provided for the BGA solder bumps 32
and the back surface of the back glass plate.
[0021] As set forth hereinabove, the spacer rims area comprise the
bond pads 38, which are connected to the BGA solder bumps 32 by
means of leads 34 extending along the angularly notched sides of
the structure. A cavity 44 is formed below the back surface of the
front glass plate 10 and the cavity provides an optically or
mechanically sensitive area, as is known in the technology.
[0022] As shown in the enlarged detail of FIG. 3, this structure 50
discloses prior art multi-level aluminum-tungsten vias 52 with
multi-level bond pads 54 to form connections between the leads 56
and the bond pads 54. This essentially provides a low-resistance
connection to the aluminum and tungsten via structures; however,
due to the use of copper wiring, normally employing multiple-level
through connections between the bond pads and leads, poor
reliability may be encountered due to oxidation and corrosion of
the copper. Moreover, a single aluminum pad is frequently employed
as the final metal layer in the copper interconnect processes and,
if connected to the leads, may produce a high-resistance
connection, with the attendant drawbacks.
[0023] The present invention may use a single aluminum pad, but
increases the surface area of this pad by forming via bars of
either W (via bar width <2.times. the thickness of W) or W+Al
(via bar width >2.times. the thickness of W) underneath the pad,
or alternatively by adding metal on top of the pad.
[0024] Via bars can be formed using the standard via mask or by
using an additional mask. The depth of the via bar can be enhanced
in two ways: (1) use RIE (reactive ion etch) lag to obtain a much
greater etch depth for the via bar compared to the via, or (2) use
an additional mask to form the via bars before the vias. Hereby,
the surface area can also be increased by using an isotropic etch
of the dielectric which is selective with regard to the metal
(dilute HF for SiO.sub.2 dielectric, O.sub.2 plasma for organic
dielectric), so as to recess the edge of the package via with
respect to the metal.
[0025] A first one of these inventive embodiments (W+Al via bar, no
additional masks) is shown in FIGS. 4A through 4C of the
drawings.
[0026] Reverting in greater particularity to the drawings, and
especially the first embodiment as exemplified in FIGS. 4A through
4C, there is diagrammatically shown in FIG. 4A a side view of an
electronic package 60 a notch has been formed to expose the bond
pads Provided is a glass plate 62, the back surface thereof
includes a polymer layer 64, and along the edges at one side
consisting of silicon dioxide or silicon nitrate, and the rear
surface of which is contacted an Al or aluminum bond pad 66. A via
68 is provided beneath the bond pad 66. Tungsten (W) via bars 68
are provided at one end of bond pad 66, to provide connection to
the circuits. Tungsten (W) via bar 70 is provided beneath the bond
pads 66, and therebeneath a further glass plate is bonded thereto
by means of epoxy and which forms the rear surface for the
attachment thereto of BGA solder bumps (not shown). As shown in
FIG. 4B of the drawings, which is a side view after the via etch
has been implemented to the electronic package 60, there is
indicated that in the structure thereof an optional isotropic etch
76 may be provided extending diagonally across one edge so as to
increase the surface area of the bond pad 66. The via bars can also
be formed from metals, such as tungsten, a combination of tungsten
and aluminum, Cr, Au, Ni, NiMoP, Co, CoWP or CoWB.
[0027] As shown in an edge view of the electronic package in the
direction of the arrow A in FIG. 4B, in FIG. 4C there are shown the
various tungsten and aluminum via bars 80 beneath the aluminum bond
pad 66, which provide for an increased surface area for a low
resistance electrical contact.
[0028] As previously noted, the edge 82 of the electronic package
60 may be cut at an angle relative to the normal for positioning of
the leads interconnecting the bond pads. This eliminates the need
for applying of the additional masks, as is provided for in the
prior art.
[0029] As indicated, an RIE lag can be used so that via bars 70 are
at a greater depth than vias 68, and the isotropic etch, which is
optional of the dielectric may be provided in connection with the
type of metal employed where dilute HF is employed for SiO.sub.2
dielectric, and O.sub.2 plasma for an organic dielectric, for
recessing or angling the edge of the package with regard to the
metal. This also eliminates the requirement for an additional mask
in comparison with the prior art, as shown for the invention in
FIGS. 4A through 4C.
[0030] As shown in the embodiment of FIGS. 5A and 5B, in which the
same reference numerals are used as in the previous embodiment for
identical or similar elements, in this instance, an additional
metal layer, such as aluminum, gold, silver, silicon based solder,
lead based solder, palladium, platinum, chromium, nickel, copper or
alloys thereof can be added on top of the bond pad after forming a
terminal via. The additional metal is formed, as shown in FIG. 5A,
by using a shadow mask to deposit the metal, wherein the aluminum
is evaporated, and, if required as well, a barrier layer, such as
of titanium, tantalum, tungsten, tantalum nitrate, tungsten
nitrate, or titanium tungsten. These materials are not shown in the
drawings.
[0031] Suitable electroplating or electroless plating may be
employed to add the metal layer, whereby electroless plating
requires no additional masks. On the other hand, electroplating
will require one or two additional masks, which define a seed layer
used to electroplate metal, as is known in the art.
[0032] Thereafter, an optional isotropic etch may be applied, as in
the previous embodiment, as shown in the side view of FIG. 5B,
after an electronic package etch, so as to increase the bond pad
surface at an essentially angular relationship relative to the
normal.
[0033] From the foregoing, it is also shown in FIGS. 6A and 6B,
that each aluminum pad 80 may have slotted vias 82 provided under
the respective bond pad into which the tungsten via bars 84 can be
inserted and connected by means of leads 86 to the electronic
package structure 88, as shown in FIG. 6A and sectional view of
FIG. 6B.
[0034] From the foregoing, it becomes apparent by the invention
that a highly reliable connection is produced, which avoids the use
of copper for the connection between bond pads and leads, thereby
reducing any possibility of corrosion; and there is also provided a
low-resistance connection between the bond pads and the leads due
to the high cross-sectional surface area, and also the possibility
of utilizing single layer aluminum bond pads.
[0035] A particular use of the invention may also be ascertained in
that it can be utilized in chip scale packaging (CSP) resulting in
smaller integrated circuit package sizes. Further, in another
application of the invention, there may be utilized image sensors,
which benefit from the resultingly smaller packages, since a
reduction in the size of an image sensor package enables the
installation and utilization thereof in cell phone cameras.
Pursuant to another application of the invention, there may be
utilized MEMS sensors, which benefit from the resultantly smaller
packages, since a reduction in the size of a MEMS sensor package
enables the installation and utilization thereof in consumer
portable electronics (GPS devices, and the like).
[0036] While the present invention has been particularly shown and
described with respect to preferred embodiments thereof, it will be
understood by those skilled in the art that the foregoing and other
changes in forms and details may be made without departing from the
spirit and scope of the present invention. It is therefore intended
that the present invention not be limited to the exact forms and
details described and illustrated, but fall within the spirit and
scope of the appended claims.
* * * * *