U.S. patent application number 11/220619 was filed with the patent office on 2006-05-25 for multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Soo-doo Chae, Chung-woo Kim, Moon-kyung Kim, Jo-won Lee.
Application Number | 20060108629 11/220619 |
Document ID | / |
Family ID | 36460164 |
Filed Date | 2006-05-25 |
United States Patent
Application |
20060108629 |
Kind Code |
A1 |
Chae; Soo-doo ; et
al. |
May 25, 2006 |
Multi-bit non-volatile memory device, method of operating the same,
and method of fabricating the same
Abstract
A multi-bit non-volatile memory device and methods of operating
and fabricating the same may be provided. The memory device may
include a channel region formed in a semiconductor substrate, and a
source and drain that form a Schottky contact with the channel
region. Also, a central gate electrode may be located on a portion
of the channel region, and first and second sidewall gate
electrodes may be formed on the channel region along the outer
sides of the central gate electrode. First and second storage nodes
may be formed between the channel region and the sidewall gate
electrodes.
Inventors: |
Chae; Soo-doo; (Gyeonggi-do,
KR) ; Kim; Moon-kyung; (Gyeonggi-do, KR) ;
Lee; Jo-won; (Gyeonggi-do, KR) ; Kim; Chung-woo;
(Gyeonggi-do, KR) |
Correspondence
Address: |
BUCHANAN INGERSOLL PC;(INCLUDING BURNS, DOANE, SWECKER & MATHIS)
POST OFFICE BOX 1404
ALEXANDRIA
VA
22313-1404
US
|
Assignee: |
Samsung Electronics Co.,
Ltd.
Gyeonggi-do
KR
|
Family ID: |
36460164 |
Appl. No.: |
11/220619 |
Filed: |
September 8, 2005 |
Current U.S.
Class: |
257/315 ;
257/E21.21; 257/E21.423 |
Current CPC
Class: |
H01L 29/7923 20130101;
H01L 29/66833 20130101; G11C 16/0475 20130101; H01L 29/40117
20190801 |
Class at
Publication: |
257/315 |
International
Class: |
H01L 29/788 20060101
H01L029/788 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 19, 2004 |
KR |
10-2004-0095051 |
Claims
1. A multi-bit non-volatile memory device comprising: a channel
region formed in a semiconductor substrate; a source and a drain
located at the each ends of the channel region of the semiconductor
substrate, and forming a Schottky contact with the channel region;
a central gate electrode formed on a portion of the channel region;
first and second sidewall gate electrodes formed parallel to the
central gate electrode on the channel region and along the outer
sides of the central gate electrode; and a first storage node
formed between the channel region and the first sidewall gate
electrode and a second storage node formed between the channel
region and the second sidewall gate electrode.
2. The device of claim 1, wherein the source and the drain are
composed of a metal silicide.
3. The device of claim 2, wherein the metal silicide is any one
material selected from the group consisting of titanium silicide,
cobalt silicide, tungsten silicide, nickel silicide and platinum
silicide.
4. The device of claim 2, wherein the channel region is doped with
an n-type or a p-type impurity.
5. The device of claim 2, wherein the storage nodes are composed of
a nitride layer.
6. The device of claim 2, further comprising: a first insulating
layer between the storage nodes and the channel region, and a
second insulating layer between the storage nodes and the sidewall
gate electrodes.
7. The device of claim 6, wherein the first insulating layer and
the second insulating layer are each a silicon oxide layer.
8. The device of claim 6, further comprising a third insulating
layer between the central gate electrode and the channel
region.
9. The device of claim 8, further comprising a fourth insulating
layer between the central gate electrode and the sidewall gate
electrodes.
10. The device of claim 9, wherein the fourth insulating layer
comprises a silicon nitride layer.
11. The device of claim 10, wherein the fourth insulating layer
further comprises silicon oxide layers on both sides of the silicon
nitride layer.
12. The device of claim 1, wherein the sidewall gate electrodes
comprise polysilicon.
13. The device of claim 1, wherein the central gate electrode
comprises polysilicon.
14. A multi-bit non-volatile memory device comprising: a channel
region formed in a semiconductor substrate; a source and a drain
composed of a metal silicide formed in the semiconductor substrate
on the sides of the channel region; a first insulating layer
located on a portion of the channel region; a central gate
electrode located on the first insulating layer; first and second
sidewall gate electrodes formed parallel to the central gate
electrode on the channel region, and along the outer sides of the
central gate electrode; a second insulating layer located between
the sidewall gate electrodes and the central gate electrode; a
first storage node formed between the first sidewall gate electrode
and the channel and a second storage node formed between the second
sidewall gate electrode and the channel; a third insulating layer
located between the storage nodes and the sidewall gate electrodes;
and a fourth insulating layer located between the storage nodes and
the channel.
15. The device of claim 14, wherein the storage nodes are composed
of a silicon nitride layer.
16. The device of claim 14, wherein the insulating layers are each
a silicon oxide layer.
17. The device of claim 14, wherein the channel region is doped
with an n-type or a p-type impurity.
18. A method of programming a multi-bit non-volatile memory device
using the device of claim 1, wherein a program voltage is
selectively supplied to at least one word line after the first and
second sidewall gate electrodes are set as first and second word
lines and the source and the drain are grounded, thereby storing
charge in the storage node corresponding to the selected word
line.
19. The method of claim 18, wherein the central gate electrode is
grounded.
20. The method of claim 18, wherein the channel region is doped
with an n-type impurity, and the program voltage is positive.
21. The method of claim 18, wherein the channel region is doped
with a p-type impurity, and the program voltage is negative.
22. A method of erasing a multi-bit non-volatile memory device
using the device of claim 1, wherein an erasing voltage is
selectively supplied to at least one word line after the first and
second sidewall gate electrodes are set as first and second word
lines and the source and the drain are grounded, thereby erasing
charge from the storage node corresponding to the selected word
line.
23. The method of claim 22, wherein the central gate electrode is
grounded.
24. The method of claim 22, wherein the channel region is doped
with an n-type impurity, and the erasing voltage is negative.
25. The method of claim 22, wherein the channel region is doped
with a p-type impurity, and the erasing voltage is positive.
26. A method of reading out charge stored in storage nodes using
the device of claim 1, wherein the central gate electrode is
selected and supplied with a turn-on voltage, and a positive
voltage and a negative voltage are alternately supplied between the
drain and the source, so that the amount and direction of a current
are used to determine whether charge is stored in the storage
nodes.
27. The method of claim 26, wherein the sidewall gate electrodes
are grounded.
28. The method of claim 26, wherein the channel region is doped
with an n-type impurity, and the turn-on voltage is positive.
29. The method of claim 26, wherein the channel region is doped
with a p-type impurity, and the turn-on voltage is negative.
30. A method of fabricating a multi-bit non-volatile memory device
comprising: doping an impurity into a semiconductor substrate to
form a channel region; forming a first insulating layer on a
portion of the channel region; forming a central gate electrode
layer on the first insulating layer; patterning the central gate
electrode layer and the first insulating layer to form a first
insulating film and a central gate electrode; forming a second
insulating layer on the resultant structure including the central
gate electrode; forming a storage node layer on the second
insulating layer; forming a third insulating layer on the storage
node; forming a sidewall gate electrode layer on the third
insulating layer; sequentially anisotropically etching the sidewall
gate electrode layer, the third insulating layer, the storage node
layer and the second insulating layer, to form first and second
sidewall gate electrodes along the sides of the central gate
electrode; and forming a metal silicide in the channel region
located on the outer sides of the sidewall gate electrodes, to form
a source and a drain.
31. The method of claim 30, wherein the insulating layers are each
a silicon oxide layer.
32. The method of claim 30, wherein the storage node layer is a
silicon nitride layer.
33. The method of claim 30, wherein the sidewall gate electrode
layer comprises polysilicon.
34. The method of claim 30, wherein forming the metal silicide
comprises forming a metal layer, performing thermal treatment, and
performing selective wet etching.
35. The method of claim 34, wherein the metal layer is any one
selected from the group consisting of a titanium layer, a cobalt
layer, a tungsten layer, a nickel layer and a platinum layer.
Description
BACKGROUND OF THE DISCLOSURE
[0001] This application claims the priority of Korean Patent
Application No. 10-2004-0095051, filed on Nov. 19, 2004, in the
Korean Intellectual Property Office, the disclosure of which is
incorporated herein in its entirety by reference.
[0002] 1. Field of the Disclosure
[0003] Embodiments of the present disclosure relate to a
semiconductor memory device, and more particularly to-a multi-bit
non-volatile memory (NVM) device, a method of operating the same,
and a method of fabricating the same.
[0004] 2. Description of the Related Art
[0005] Semiconductor memory devices can be broadly store data in a
hard disc and classified as either volatile or non-volatile memory.
In order to perform fast data processing when power is being turned
on, a volatile memory such as DRAM is employed in an apparatus such
as a computer.
[0006] However, instead of the DRAM typically used for computers,
the growing market for mobile phones and digital cameras has
created a demand for non-volatile memory with fast processing speed
which can store data regardless of whether power is
interrupted.
[0007] Flash memory is a widely used type of non-volatile memory
device, with a storage node structure for storing electric charge.
Two common forms of flash memory are the floating gate type and the
SONOS type with an oxide/nitride/oxide (ONO) structure.
Hereinafter, a conventional SONOS type non-volatile memory device
will be described with reference to FIG. 1.
[0008] Referring to FIG. 1, a SONOS type non-volatile memory device
uses a nitride layer 120 as a storage node. An oxide layer 115 for
tunneling charge or injecting hot carriers is located between the
nitride layer 120 and a semiconductor substrate 105.
[0009] A blocking insulating film, e.g., a silicon oxide layer, 125
is formed between the nitride layer 120 and a control gate
electrode 130. By this construction, the nitride layer 120 as the
storage node is separated from the semiconductor substrate 105 and
the control gate electrode 130 by the oxide layers 115 and 125.
Accordingly, once charge is stored in the nitride layer 120, it can
be maintained even if the power supply is cut off.
[0010] In this structure, programming is performed to store charge
in the nitride layer 120 by supplying a program voltage to the
control gate electrode 130. By doing so, the electrons accelerated
in source and drain regions 110 are energized and then injected
into the nitride layer 120. This method is hot carrier
injecting.
[0011] Otherwise, the electrons of the semiconductor substrate 105
may be injected into the nitride layer 120 by tunneling, in
accordance with a voltage supplied to the control gate electrode
130.
[0012] Erasing the charge from the nitride layer 120 is performed
by supplying a negative voltage to the control gate electrode 130,
or supplying a positive voltage to the semiconductor substrate 105.
At this time, the charge stored in the nitride layer 120 is erased
by tunneling.
[0013] A multi-bit SONOS type non-volatile memory is currently
under development. This device utilizes the local pinning of
charges stored in the nitride layer 120. That is, when opposite
electric fields are applied to both ends of the source and drain
regions 110, electrons can be separately stored in both ends of the
nitride layer 120.
[0014] However, multi-bit operation using the single nitride layer
120 has a problem in that the two different stored charges cannot
be distinguished as a gate length is decreased. Moreover, the
mixing of the stored charge cannot be completely prevented.
SUMMARY OF THE DISCLOSURE
[0015] Embodiments of the present disclosure provide a reliable
multi-bit non-volatile memory device.
[0016] The present disclosure may also provide a multi-bit
operation method of the multi-bit non-volatile memory device.
[0017] The present disclosure may also provide a method of
fabricating the multi-bit non-volatile memory device.
[0018] According to an aspect of the present disclosure, there may
be provided a multi-bit non-volatile memory device including a
channel region formed in a semiconductor substrate. A source and a
drain may be located at the each ends of the channel region of the
semiconductor substrate and form a Schottky contact with the
channel region, and a central gate electrode may be formed on a
portion of the channel region. First and second sidewall gate
electrodes may be formed parallel to the central gate electrode on
the channel region and along the outer sides of the central gate
electrode. Furthermore, a first storage node may be formed between
the channel region and the first sidewall gate electrode, and a
second storage node may be formed between the channel region and
the second sidewall gate electrode.
[0019] Here, the source and the drain may be composed of a metal
silicide. Moreover, a first insulating layer may be formed between
the storage nodes and the channel region, and a second insulating
layer may be formed between the storage nodes and the sidewall gate
electrodes.
[0020] Additionally, a third insulating layer may be formed between
the central gate electrode and the channel region. A fourth
insulating layer may be added between the central gate electrode
and the sidewall gate electrodes.
[0021] According to another aspect of the present disclosure, there
may be provided a multi-bit non-volatile memory device including a
channel region formed in a semiconductor substrate. A source and a
drain of a metal silicide may be formed in the semiconductor
substrate at the sides of the channel region, and a first
insulating layer may be located on a portion of the channel region.
A central gate electrode may be located on the first insulating
layer, and first and second sidewall gate electrodes may be formed
parallel to the central gate electrode on the channel region and
along the outer sides of the central gate electrode. A second
insulating layer may be located between the sidewall gate
electrodes and the central gate electrode, and a first storage node
formed between a first sidewall gate electrode and the channel, and
a second storage node formed between the second sidewall gate
electrode and the channel. A third insulating layer may be located
between the storage nodes and the sidewall gate electrodes, and a
fourth insulating layer may be located between the storage nodes
and the channels. At this time, the storage nodes may be composed
of a silicon nitride layer.
[0022] According to still another aspect of the present disclosure,
there may be provided a method of programming a multi-bit
non-volatile memory device using the foregoing device. Here, a
program voltage may be selectively supplied to at least one word
line after the first and second sidewall gate electrodes are set as
first and second word lines and the source and the drain may be
grounded. Thus, charge may be stored in the storage node
corresponding to the selected word line.
[0023] At this time, the channel region may be doped with an n-type
impurity, and the program voltage may be positive. Alternatively,
the channel region may be doped with a p-type impurity, and the
program voltage may be negative.
[0024] According to yet another aspect of the present disclosure,
there may be provided a method of erasing a multi-bit non-volatile
memory device using the foregoing device. Here, an erasing voltage
may be selectively supplied to at least one word line after the
first and second sidewall gate electrodes are set as first and
second word lines and the source and the drain may be grounded.
Thus, the charge stored in the storage node corresponding to the
selected word line may be erased.
[0025] According to another aspect of the present disclosure, there
may be provided a method of reading out charge stored in the
storage nodes using the foregoing device. Here, the central gate
electrode may be selected and supplied with a turn-on voltage, and
a positive voltage and a negative voltage may be alternately
supplied between the drain and the source. Thus, the amount and
direction of a current may be used to determine whether charge is
stored in the storage nodes.
[0026] At this time, the channel region may be doped with an n-type
impurity, and the turn-on voltage may be positive. Also, the
channel region may be doped with a p-type impurity, and the turn-on
voltage may be negative.
[0027] According to another aspect of the present disclosure, there
may be provided a method of fabricating a multi-bit non-volatile
memory device, including doping an impurity into a semiconductor
substrate to form a channel region. After forming a first
insulating layer on a portion of the channel region, a central gate
electrode layer may be formed on the first insulating layer. Then,
the central gate electrode layer and the first insulating layer may
be patterned to form a first insulating film and a central gate
electrode. A second insulating layer may be formed on the resultant
structure including the central gate electrode, and a storage node
layer may be formed on the second insulating layer. After forming a
third insulating layer on the storage node, a sidewall gate
electrode layer may be formed on the third insulating layer. By
sequentially anisotropically etching the sidewall gate electrode
layer, the third insulating layer, the storage node layer and the
second insulating layer, first and second sidewall gate electrodes
may be formed along the sides of the central gate electrode. Then,
a metal silicide may be formed in the channel region located on the
outer sides of the sidewall gate electrodes, thereby forming a
source and a drain.
[0028] Here, forming the metal silicide may include forming a metal
layer, performing thermal treatment and performing selective wet
etching.
BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The above and other features and advantages of the present
disclosure will become more apparent by describing in detail
exemplary embodiments thereof with reference to the attached
drawings in which:
[0030] FIG. 1 is a sectional view of a conventional SONOS type
non-volatile memory device;
[0031] FIG. 2 is a sectional view of a multi-bit non-volatile
memory device according to an embodiment of the present
disclosure;
[0032] FIG. 3 is a sectional view showing the multi-bit
non-volatile memory device and its connection ports according to
the embodiment of the present disclosure;
[0033] FIGS. 4 through 6 plot energy bands for illustrating a
readout operation of the multi-bit non-volatile memory device
according to the embodiment of the present disclosure; and
[0034] FIGS. 7 through 12 are sectional views showing a method of
fabricating the multi-bit non-volatile memory device according to
the embodiment of the present disclosure.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE DISCLOSURE
[0035] Embodiments of the present disclosure will now be described
more fully with reference to the accompanying drawings. The
invention may, however, be embodied in many different forms, and
should not be construed as being limited to the embodiments set
forth herein. In the drawings, the thicknesses of layers and
regions may be exaggerated for clarity.
[0036] FIG. 2 is a sectional view showing a multi-bit non-volatile
memory device according to an embodiment of the present
disclosure.
[0037] Referring to FIG. 2, a multi-bit non-volatile memory device
200 may include a pair of storage nodes 240a and 240b, separated
from each other. Also, a pair of sidewall gate electrodes 250a and
250b may be respectively positioned over the storage nodes 240a and
240b. The storage nodes 240a and 240b may store charge.
[0038] Tunneling insulating layers 235a and 235b may be located
between one of the storage nodes 240a and 240b, and a channel
region 210 of a semiconductor substrate 205, e.g., a silicon
substrate, respectively. The charge may migrate by tunneling
through the tunneling insulating layers 235a and 235b, between the
channel region 210 and the storage nodes 240a and 240b. For this
reason, the tunneling insulating layers 235a and 235b may have a
thickness that allows for charge tunneling under an operating
voltage.
[0039] Furthermore, blocking insulating film 245a may be located
between the storage node 240a and the sidewall gate electrode 250a.
Blocking insulating film 245b may be located between the storage
node 204b and the sidewall gate electrode 250b. The storage nodes
240a and 240b may be insulated from the sidewall gate electrodes
250a and 250b by the blocking insulating films 245a and 245b,
respectively.
[0040] More specifically, the storage nodes 240a and 240b may be
composed of a silicon nitride layer. At this time, the tunneling
insulating layers 235a and 235b and the blocking insulating films
245a and 245b may be composed of a silicon oxide layer.
Accordingly, the insulating layers between the sidewall gate
electrodes 250a and 250b and the channel region 210 may have an ONO
structure of oxide layer/nitride layer/oxide layer.
[0041] A left SONOS structure may be formed from the channel region
210 to the left sidewall gate electrode 250a, and a right SONOS
structure may be formed from the channel region 210 to the right
sidewall gate electrode 250b. Accordingly, two SONOS structures may
be provided within a single cell of the non-volatile memory device
200, thereby preparing a memory structure for multi-bit operation.
At this time, the channel region may be doped with an n-type
impurity or a p-type impurity.
[0042] As shown in FIG. 2, a central gate electrode 230 may be
located between two sidewall gate electrodes 250a and 250b. Also, a
gate insulating layer 225 may be provided between the central gate
electrode 230 and the channel region 210. By supplying a voltage
higher than a threshold voltage to the central gate electrode 230,
the current through the center of the channel region 210 may be
controlled.
[0043] In more detail, the central gate electrode 230 may include
polysilicon, and the gate insulating layer 225 may be composed of a
silicon oxide layer. The two sidewall gate electrodes 250a and 250b
may include polysilicon.
[0044] Preferably, as shown in FIG. 2, the tunneling insulating
layers 235a and 235b, the storage nodes 240a and 240b, and the
blocking insulating films 245a and 245b may extend between the
central gate electrode 230 and the sidewall gate electrodes 250a
and 250b, thereby constituting a spacer structure.
[0045] A source 255 and a drain 260 may be located on the outer
sides of the channel region 210. At this time, the source 255 and
the drain 260 may form a Schottky contact with the channel region
210, in contrast to the conventional structure. More specifically,
the source 255 and the drain 260 may be composed of a metal
silicide.
[0046] The metal silicide may be any one material selected from the
group consisting of titanium silicide, cobalt silicide, tungsten
silicide, nickel silicide and platinum silicide. Such a metal
silicide may form the Schottky contact with the silicon of the
channel region 210.
[0047] Hereinafter, multi-bit operation of the non-volatile memory
device 200 may be described.
[0048] FIG. 3 is a sectional view of the multi-bit non-volatile
memory device and its connecting ports according to an embodiment
of the present disclosure.
[0049] Referring to FIG. 3, a source voltage V.sub.s may be
supplied to the source 255, and a drain voltage V.sub.d may be
supplied to the drain 260. A gate voltage V.sub.g may be supplied
to the central gate electrode 230, a control gate voltage V.sub.sg1
may be supplied to the left sidewall gate electrode 250a, and
another control gate voltage V.sub.sg2 may be supplied to the right
sidewall gate electrode 250b. At this time, the semiconductor
substrate 205 may be grounded, although not shown in the
drawing.
[0050] Here, the polarity of the supplied voltages may be changed
according to whether the channel region 210 is doped with an n-type
impurity or a p-type impurity. Therefore, each case will be
described separately.
[0051] The following Table 1 shows programming for the n-type
channel. TABLE-US-00001 TABLE 1 V.sub.sg1 V.sub.sg2 V.sub.g V.sub.s
V.sub.d (1, 1) + + 0 0 0 (1, 0) + 0 0 0 0 (0, 1) 0 + 0 0 0 (0, 0) 0
0 0 0 0
[0052] Referring to Table 1, a positive (+) voltage higher than the
threshold voltage relative to the channel region (210 of FIG. 3)
may be supplied to V.sub.sg1 or V.sub.s 92 to selectively store
charge in the storage nodes (240a and 240b of FIG. 3), thereby
programming the cell.
[0053] Here, the state "1" denotes that the storage node is in a
programmed state, and "0" denotes an erased state. For example,
(1,1) denotes that both storage nodes 240a and 240b are programmed.
(1,0) denotes that the left storage node 240a is programmed and the
right storage node 240b is erased. Particularly, in case of the
n-type channel, stored electrons create a "1" while stored holes
create a At this time, V.sub.g, V.sub.s and V.sub.d may be supplied
with no voltage or are grounded. Accordingly, without incurring a
current flow between the source ( 255 of FIG. 3) and the drain (260
of FIG. 3), the charge, i.e., electrons, of the channel region 210
may migrate to the storage nodes 240a and 240b by tunneling in
accordance with the voltage supplied between the channel region 210
and the sidewall gate electrodes 250a and 250B
[0054] Table 2 shows erasing to state (0,0) for the n-type channel
region. TABLE-US-00002 TABLE 2 V.sub.sg1 V.sub.sg2 V.sub.g V.sub.s
V.sub.d (1, 1) - - 0 0 0 (1, 0) - 0 0 0 0 (0, 1) 0 - 0 0 0 (0, 0) 0
0 0 0 0
[0055] Referring to Table 2, a negative (-) voltage more than the
threshold voltage relative to the channel region (210) is supplied
to V.sub.sg1 or V.sub.sg2 to selectively erase the charge stored in
the storage nodes (240a and 240b).
[0056] Here, a negative erasing voltage lower than that of the
channel region 210 may be supplied to the sidewall gate electrodes
250a and 250b, thereby erasing the charge stored in the storage
nodes 240a and 240b.
[0057] For example, in order to erase from state (1,0) to state
(0,0), the erasing voltage may be supplied only to the left
sidewall gate electrode 250a. At this time, V.sub.g, V.sub.s and
V.sub.d may be supplied with no voltage or are grounded.
[0058] Table 3 represents a readout operation for the n-type
channel. TABLE-US-00003 TABLE 3 V.sub.g V.sub.s V.sub.d I.sub.s
I.sub.d (1, 1) + + 0 0 0 (1, 1) + 0 + 0 0 (1, 0) + + 0 + - (1, 0) +
0 + 0 0 (0, 1) + + 0 0 0 (0, 1) + 0 + - + (0, 0) + + 0 + - (0, 0) +
0 + - +
[0059] Referring to Table 3, the positive (+) voltage higher than
the threshold voltage, i.e., a turn-on voltage, is supplied to
V.sub.g, and another voltage may be supplied to V.sub.s and V.sub.d
alternatively so as to read out individual states. At this time,
individual states may be read out by checking the amount and
direction of the currents I.sub.s and I.sub.d between the source
255 and the drain 260. At this time, the polarity of the reference
characters I.sub.s and I.sub.d denotes the current directions.
Also, V.sub.sg1 and V.sub.sg2 may be floated or grounded.
[0060] As shown in Table 3, bidirectional current combinations
between source 255 and the drain 260 may correspond to the
respective states on a one-to-one basis. For example, under state
(1,1), no current flows regardless of supplying the positive
voltage to Vs or Vd. Under state (0,1), no current flows when a
positive voltage is supplied to Vs, but a current flows from the
drain 260 toward the source 255 when a positive voltage is supplied
to Vd.
[0061] Hereinafter, the procedure for reading state (1,0) will be
given as an example for illustrating the readout operation, with
reference to energy bands plotted in FIGS. 4 through 6. Other
states will be easily understood by those skilled in the art when
considering the example.
[0062] Here, the left represents the energy band between the source
( 255 of FIG. 3) and the channel region ( 210 of FIG. 3), and the
right represents the energy band between the drain (260 of FIG. 3)
and the channel region ( 210 of FIG. 3). Also, reference character
E.sub.f denotes the Fermi energy, E.sub.c denotes a conduction band
energy, and E.sub.v denotes a valence band energy.
[0063] FIG. 4 shows the energy band before reading out state
(1,0).
[0064] Referring to FIG. 4, in state (1,0), electrons are stored in
the left storage node (240a of FIG. 3), and holes are stored in the
right storage node (240b of FIG. 3).
[0065] Accordingly, as shown in the left graphs of FIG. 4, the
channel region 210 contacting the source 255 is in a depletion
state, and the Schottky barrier becomes raised. Also, the channel
region 210 contacting the drain 260 is in an accumulation state as
shown in the right graphs of FIG. 4, and the Schottky barrier is
lowered. At this time, E.sub.f is determined relatively in
accordance with the quantity of stored electrons and holes.
[0066] FIG. 5 represents the energy band when a positive voltage is
supplied to V.sub.s in state (1,0).
[0067] Referring to FIG. 5, the energy band graph shown in FIG. 4
is changed, since the positive voltage is supplied to the source
255. That is, as the positive voltage is supplied to the source
255, the Schottky barrier of the source 255 and the channel region
210 is lowered.
[0068] Also, although the drain 260 is grounded, the right storage
node 240b stores holes. Accordingly, the effect is as if the right
sidewall gate electrode 250b was supplied with a positive voltage.
Therefore, the channel region 210 contacting the drain 260 is in an
accumulation state, which in turn lowers the Schottky barrier.
[0069] At this time, the turn-on voltage is applied to the central
gate electrode ( 230 of FIG. 3). By doing so, the channel region
210 below the central gate electrode 230 is put in an inversion
state, to allow current to flow. Thus, current can flow through a
junction between the source 255 and the channel region 210, the
channel region 210, and a junction between the channel region 210
and the drain 260. In other words, as is shown in [Table 3], the
current flows from the source 255 to the drain 260.
[0070] FIG. 6 represents the energy band when a positive voltage is
supplied to V.sub.d under state (1,0).
[0071] Referring to FIG. 6, as the positive voltage is supplied to
the drain 260, the channel region 210 contacting the drain 260 is
in the accumulation state as shown in the right graphs, which in
turn lowers the Schottky barrier. That is, the current can flow
through the junction region between the drain 260 and the channel
region 210.
[0072] However, as shown in the left graphs of FIG. 6, the source
255 is grounded, as it is before performing the reading out as
shown in FIG. 4. That is, the electrons are stored in the left
storage node 240a, so that the channel region 210 is in the
depletion state. Consequently, the Schottky barrier is heightened.
Therefore, no current flows through the junction region between the
source 255 and the channel region 210.
[0073] At this time, the threshold voltage is supplied to the
central gate electrode 230 to invert the channel region 210,
thereby allowing the current to flow. However, since the current
cannot flow through the junction between the source 255 and the
channel region 210, no current flows between the source 255 and the
drain 260 as shown in [Table 3].
[0074] The readout operation has been described using state (1,0)
as an example. Therefore, it is obvious that other states can
easily be inferred by those of ordinary skill in the art, using a
similar principle and referring to Table 3 and FIGS. 4 through
6.
[0075] On the other hand, when the channel region (210 of FIG. 3)
is a p-type channel, the present disclosure can be easily adapted
by those of ordinary skill in the art, with reference to the n-type
state of Table 3, and FIGS. 4 through 6. In this case, the
polarities are all the reverse of those for the n-type. For
example, for the p-type channel, all positive voltages of [Table 3]
are changed to negative voltages when programming. Therefore,
negative voltages are supplied to the sidewall gate electrodes
(250a and 250b of FIG. 3) that will be programmed with respect to
the channel region (210 of FIG. 3). Also, all negative voltages of
[Table 4] are changed to the positive voltages when erasing. In
other words, the positive voltage with respect to the channel
region 210 is supplied to the sidewall, gate electrodes 250a and
250b that will be erased with respect to the channel region
210.
[0076] The readout operation for the p-type channel may refer to
[Table 6]. At this time, the central gate electrode (230 of FIG. 3)
is supplied with a negative voltage higher than the threshold
voltage, i.e., the turn-on voltage. Furthermore, the selected
source 255 and the drain 260 are supplied with a negative voltage
instead of a positive voltage. By doing so, the current flowing
between the source 255 and the drain 260 is reversed.
[0077] As described above, the multi-bit non-volatile memory device
200 according to the present disclosure may allow for individual
programming and erasing of the two storage nodes 240a and 240b,
respectively. Therefore, multi-bit operation of 2 bits or more may
be performed using only a single cell of the multi-bit non-volatile
memory device 200.
[0078] In addition, the multi-bit non-volatile memory device 200
may enable a stable readout operation by changing the Schottky
barrier, because the voltage may be supplied between the source 255
and the drain 260. At this time, the central gate electrode 230 may
selectively turned on, so that the cells of a single column or row
can be selected from a cell array.
[0079] FIGS. 7 through 12 are sectional views showing a method of
fabricating the multi-bit non-volatile memory device according to
the embodiment of the present disclosure.
[0080] Referring to FIG. 7, a channel region 310 may be formed by
doping a surface region of a semiconductor substrate 305. Referring
to FIG. 8, a gate insulating layer 325' and a central gate
electrode layer 330' may be formed on the channel region 310. At
this time, the gate insulating layer 325' may be preferably a
silicon oxide layer. The silicon oxide layer may be formed by
oxidizing the silicon of the semiconductor substrate 305. Also, the
central gate electrode layer 330' may be a polysilicon layer or a
composite layer including polysilicon.
[0081] Referring to FIG. 9, the central gate electrode layer 330'
and the gate insulating layer 325' may be patterned, thereby
forming a central gate electrode 330 and a gate insulating layer
325. The patterning may be performed using photolithography and
etching.
[0082] Referring to FIG. 10, a tunneling insulating layer 335, a
storage node layer 340, a blocking insulating film 345, and a
sidewall gate electrode layer 350 may be sequentially formed on the
resultant structure including the central gate electrode 330. At
this time, the tunneling insulating layer 335 and the blocking
insulating film 345 may each be a silicon oxide layer.
[0083] The storage node layer 340 may be a silicon nitride layer.
The silicon oxide layers and the silicon nitride layer may be
formed by chemical vapor deposition (CVD). Preferably, the sidewall
gate electrode layer 350 may be a polysilicon layer or a composite
layer including polysilicon.
[0084] Referring to FIG. 11, the sidewall gate electrode layer 350,
the blocking insulating film 345, the storage node layer 340, and
the tunneling insulating layer 335 may be sequentially
anisotropically etched. By doing so, the sidewall gate electrodes
350a and 350b may be formed as spacers along the sidewalls of the
central gate electrode 330. Therefore, the sidewall gate electrodes
350a and 350b may be formed without requiring expensive
patterning.
[0085] At this time, a blocking insulating film 345a, a storage
node 340a and a tunneling insulating layer 335 a may be interposed
between the left sidewall gate electrode 350a and the central gate
electrode 330, and between the left sidewall gate electrode 350a
and the channel region 310.
[0086] Similarly, a blocking insulating film 345b, a storage node
340b and a tunneling insulating layer 335b may be interposed
between the right sidewall gate electrode 350b and the central gate
electrode 330, and between the right sidewall gate electrode 350b
and the channel region 310.
[0087] Referring to FIG. 12, a source 355 and a drain 360 may be
formed at both ends of the channel region 310. At this time, the
source 355 and the drain 360 may be composed of a metal
silicide.
[0088] The forming the metal silicide may include forming a metal
layer, thermal treatment and selective wet etching. At this time,
the metal layer may be any one selected from a titanium layer, a
cobalt layer, a tungsten layer, a nickel layer and a platinum
layer. Also, in view of the substance constituting the metal layer,
a thermal treatment may be added after wet etching.
[0089] Thereafter, interconnecting may be performed as is
well-known in the art. By doing so, the fabrication of the
multi-bit non-volatile memory device may be completed.
[0090] While the present invention has been particularly shown and
described with reference to exemplary embodiments thereof, it will
be understood by those of ordinary skill in the art that various
changes in form and details may be made therein without departing
from the spirit and scope of the present disclosure as defined by
the following claims.
* * * * *