U.S. patent application number 11/024422 was filed with the patent office on 2006-05-25 for semiconductor device.
Invention is credited to Hiroshi Itokawa, Koji Yamakawa.
Application Number | 20060108624 11/024422 |
Document ID | / |
Family ID | 36423815 |
Filed Date | 2006-05-25 |
United States Patent
Application |
20060108624 |
Kind Code |
A1 |
Itokawa; Hiroshi ; et
al. |
May 25, 2006 |
SEMICONDUCTOR DEVICE
Abstract
A semiconductor device comprises a capacitor including a bottom
electrode, a top electrode, and a dielectric film, the bottom
electrode comprising a first conductive film containing iridium, a
second conductive film provided between the dielectric film and the
first conductive film and formed of a noble metal film, a third
conductive film provided between the dielectric film and the second
conductive film and formed of a conductive metal oxide film having
a perovskite structure, and a diffusion prevention film provided
between the first conductive film and the second conductive film
and including at least one of a metal film and a metal oxide film,
the diffusion prevention film preventing diffusion of iridium
contained in the first conductive film, the dielectric film
including an insulating metal oxide film having a perovskite
structure, the insulating metal oxide film being expressed by
A(Zr.sub.xTi.sub.1-x)O.sub.3 (A is at least one A site element,
0<x<0.35).
Inventors: |
Itokawa; Hiroshi;
(Yokohama-shi, JP) ; Yamakawa; Koji; (Tokyo,
JP) |
Correspondence
Address: |
OBLON, SPIVAK, MCCLELLAND, MAIER & NEUSTADT, P.C.
1940 DUKE STREET
ALEXANDRIA
VA
22314
US
|
Family ID: |
36423815 |
Appl. No.: |
11/024422 |
Filed: |
December 30, 2004 |
Current U.S.
Class: |
257/310 ;
257/E21.009; 257/E21.021; 257/E21.664; 257/E27.104 |
Current CPC
Class: |
G11C 11/22 20130101;
H01L 28/65 20130101; H01L 28/55 20130101; H01L 27/11507 20130101;
H01L 28/75 20130101; H01L 27/11502 20130101 |
Class at
Publication: |
257/310 |
International
Class: |
H01L 29/94 20060101
H01L029/94 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 22, 2004 |
JP |
2004-337654 |
Claims
1. A semiconductor device comprising: a semiconductor substrate; a
capacitor provided above the semiconductor substrate and including
a bottom electrode, a top electrode, and a dielectric film provided
between the bottom electrode and the top electrode, the bottom
electrode comprising a first conductive film containing iridium, a
second conductive film provided between the dielectric film and the
first conductive film and formed of a noble metal film, a third
conductive film provided between the dielectric film and the second
conductive film and formed of a conductive metal oxide film having
a perovskite structure, and a diffusion prevention film provided
between the first conductive film and the second conductive film
and including at least one of a metal film and a metal oxide film,
the diffusion prevention film preventing diffusion of iridium
contained in the first conductive film, and the dielectric film
including an insulating metal oxide film having a perovskite
structure, the insulating metal oxide film being expressed by
A(Zr.sub.xTi.sub.1-x)O.sub.3 (A is at least one A site element,
0<x<0.35).
2. The semiconductor device according to claim 1, wherein the metal
film included in the diffusion prevention film contains at least
one of Ti, V, W, Zr, Co, Mg, Hf, Mo, Mn, Ta, Nb, Pb, and Al.
3. The semiconductor device according to claim 1, wherein the metal
oxide film included in the diffusion prevention film contains at
least one of Ti, V, W, Zr, Co, Mg, Hf, Mo, Mn, Ta, Nb, Pb, Al, and
Ru.
4. The semiconductor device according to claim 1, wherein the first
conductive film includes at least one of an iridium film and an
iridium oxide film.
5. The semiconductor device according to claim 1, wherein the
second conductive film includes at least one of a platinum film and
a ruthenium film.
6. The semiconductor device according to claim 1, wherein the
conductive metal oxide film contains at least one of Ru, Co, and
Ni.
7. The semiconductor device according to claim 1, wherein the
conductive metal oxide film is selected from an SrRuO.sub.3 film,
an (La,Sr)CoO.sub.3 film, a BaRuO.sub.3 film, and an LaNiO.sub.3
film.
8. The semiconductor device according to claim 1, wherein the
insulating metal oxide film is expressed by
A(Zr.sub.xTi.sub.1-x)O.sub.3 (0.25<x<0.35).
9. The semiconductor device according to claim 1, wherein the A
site element includes Pb.
10. The semiconductor device according to claim 1, further
comprising a plug which is connected to the bottom electrode and on
which the capacitor is formed.
11. The semiconductor device according to claim 10, further
comprising a transistor provided on the semiconductor substrate and
electrically connected to the plug.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from prior Japanese Patent Application No. 2004-337654,
filed Nov. 22, 2004, the entire contents of which are incorporated
herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device
having a capacitor.
[0004] 2. Description of the Related Art
[0005] In recent years, many efforts have been made to develop
ferroelectric memories using a ferroelectric film as a dielectric
film of a capacitor, that is, FeRAMs (Ferroelectric Random Access
Memories). A typical ferroelectric film used for a ferroelectric
memory is a Pb(Zr.sub.xTi.sub.1-x)O.sub.3 film (PZT film) having a
perovskite structure.
[0006] If a PZT film is used as a ferroelectric film, electrodes
are composed of conductive perovskite type metal oxide films such
as SrRuO.sub.3 films (SRO films) or the like in order to, for
example, improve their fatigue characteristic. For example, Jpn.
Pat. Appln. KOKAI Publication No. 2000-208725 and Jpn. Pat. Appln.
KOKAI Publication No. 2000-260954 describe ferroelectric capacitors
having electrodes each made of a stacked film composed of an SRO
film and a Pt film.
[0007] Further, what is called a COP (Capacitor On Plug) structure
has been proposed in which a capacitor is formed on a plug in order
to increase the degree of integration of the ferroelectric memory.
In the COP structure, to prevent the plug from being oxidized by
thermal treatment, a bottom electrode of the capacitor is partly
composed of an Ir film or Ir oxide film, which has an excellent
oxygen barrier characteristic.
[0008] However, with this structure, Ir disadvantageously diffuses
through the conductive perovskite type metal oxide film or a
capacitor dielectric film, which degrades the characteristics or
reliability of the capacitor. For example, Ir may react with Pb in
the PZT film to form a conductive oxide, which increases a leak
current of the capacitor or Ir may react with Sr in the SRO film to
degrade the crystallinity of the SRO film, which degrades the
characteristics or reliability of a dielectric film on the SRO
film.
[0009] Thus, a problem with a capacitor having a capacitor
dielectric film made of a metal oxide film having a perovskite
structure is that the diffusion of Ir may degrade the
characteristics or reliability of the capacitor.
BRIEF SUMMARY OF THE INVENTION
[0010] According to an aspect of the present invention, there is
provided a semiconductor device comprising a capacitor provided
above the semiconductor substrate and including a bottom electrode,
a top electrode, and a dielectric film provided between the bottom
electrode and the top electrode, the bottom electrode comprising a
first conductive film containing iridium, a second conductive film
provided between the dielectric film and the first conductive film
and formed of a noble metal film, a third conductive film provided
between the dielectric film and the second conductive film and
formed of a conductive metal oxide film having a perovskite
structure, and a diffusion prevention film provided between the
first conductive film and the second conductive film and including
at least one of a metal film and a metal oxide film, the diffusion
prevention film preventing diffusion of iridium contained in the
first conductive film, and the dielectric film including an
insulating metal oxide film having a perovskite structure, the
insulating metal oxide film being expressed by
A(Zr.sub.xTi.sub.1-x)O.sub.3 (A is at least one A site element,
0<x<0.35).
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0011] FIGS. 1 to 3 are sectional views schematically showing a
method of manufacturing a semiconductor device according to a first
embodiment of the present invention;
[0012] FIG. 4 is a graph showing a hysteresis characteristic of a
capacitor according to the first embodiment of the present
invention;
[0013] FIG. 5 is a graph showing a hysteresis characteristic of a
capacitor according to a comparative example of the first
embodiment of the present invention;
[0014] FIG. 6 is a graph showing the relationship between an x
value and the quantity of switching charges for a
Pb(Zr.sub.xTi.sub.1-x)O.sub.3 film (PZT film) according to the
first embodiment of the present invention;
[0015] FIG. 7 is a graph showing the intensity of an XRD pattern
according to the first embodiment of the present invention;
[0016] FIG. 8 is a graph showing the intensity of the XRD pattern
according to a comparative example of the first embodiment of the
present invention; and
[0017] FIG. 9 is a sectional view schematically showing a method of
manufacturing a semiconductor device according to a second
embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0018] Embodiments of the present invention will be described below
with reference to the drawings.
Embodiment 1
[0019] FIGS. 1 to 3 are sectional views schematically showing a
method of manufacturing a semiconductor device according to a first
embodiment of the present invention.
[0020] First, as shown in FIG. 1, an isolation region 101 of an STI
(Shallow Trench Isolation) structure is formed on a p-type silicon
substrate (semiconductor substrate) 100. Subsequently, an MIS
transistor is formed as described below.
[0021] First, as a gate insulating film 102, a silicon oxide film
of thickness about 6 nm is formed by thermal oxidization.
Subsequently, arsenic-doped n.sup.+ type polysilicon film 103 is
formed on the gate insulating film 102. Moreover, a WSi.sub.x film
104 and a silicon nitride film 105 are formed on the polysilicon
film 103. Subsequently, the polysilicon film 103, the WSi.sub.x
film 104, and the silicon nitride film 105 are processed by a
normal photo lithography process and a normal RIE process to form a
gate electrode. Subsequently, a silicon nitride film 106 is
deposited all over the surface of the resulting structure.
Moreover, RIE is carried out to form side wall spacers formed of
the silicon nitride film 106, on side walls of the gate electrode.
Although not described in detail, in the present step, source/drain
regions 107 are formed by ion implantation and thermal
treatment.
[0022] Then, as shown in FIG. 2, a CVD (Chemical Vapor Deposition)
process is used to deposit a silicon oxide film 108 all over the
surface of the resulting structure. Further, a CMP process is used
to execute a flattening process. Subsequently, a contact hole is
formed through the silicon oxide film 108 so as to reach one of the
source/drain regions 107. Then, a sputtering process or the CVD
process is used to deposit a titanium film. Subsequently, the
titanium film is nitrided by thermal treatment in a foaming gas to
form a TiN film 110. Moreover, the CVD process is used to deposit a
tungsten film 111. Subsequently, the CMP process is used to remove
the TiN film 110 and tungsten film 111 from outside the contact
hole, while leaving the TiN film 110 and the tungsten film 111 in
the contact hole. This forms a plug connected to one of the
source/drain regions 107. Then, the CVD process is used to deposit
a silicon nitride film 112 all over the surface of the resulting
structure. Furthermore, a control hole is formed so as to reach the
other source/drain region 107. Subsequently, a method similar to
that described above is used to form a TiN film 114 and a tungsten
film 115 in the contact hole. This forms a plug connected to the
other source/drain region 107.
[0023] Then, as shown in FIG. 3, a titanium (Ti) film 116 of
thickness about 10 nm is deposited by the sputtering process.
Subsequently, as a first conductive film 117, an iridium (Ir) film
117a of about 100 nm thickness and an iridium oxide (IrO.sub.2)
film 117b of about 50 nm thickness are sequentially deposited by
the sputtering process. The iridium film 117a and the iridium oxide
film 117b have an excellent oxygen barrier characteristic and can
thus prevent the oxidization of the plug 115 during the subsequent
thermal treatment step. Subsequently, as a diffusion prevention
film, a titanium (Ti) film 118a of thickness about 2.5 nm is
deposited by the sputtering process. The titanium film 118a
prevents the upward diffusion of the iridium contained in the
iridium film 117a and iridium oxide film 117b. Subsequently, as a
second conductive film, a platinum (Pt) film 119 of thickness about
50 nm is deposited by the sputtering process. Then, as a seed
layer, a titanium film 120 of about 1.5 nm thickness is deposited
by the sputtering process. Moreover, as a third conductive film, an
SrRuO.sub.3 film (SRO film) 121 of thickness about 2.5 nm is
deposited on the titanium film 120 by the sputtering process.
Subsequently, the SRO film 121 is crystallized by RTA (Rapid
Thermal Annealing) in an oxygen atmosphere. The SRO film 121 with
an excellent crystallinity can be easily formed by depositing the
film at a temperature of, for example, 500.degree. C.
[0024] Then, as a dielectric film (ferroelectric film) of the
capacitor, a Pb(Zr.sub.xTi.sub.1-x)O.sub.3 film (PZT film) 122
having a thickness of about 130 nm is formed by the sputtering
process. Moreover, the PZT film 122 is crystallized by RTA in an
oxygen atmosphere. In the present embodiment, the value of x is
0.30. That is, as the PZT film 122, a
Pb(Zr.sub.0.3Ti.sub.0.7)O.sub.3 film is formed.
[0025] Then, an SRO film 123 having a thickness of about 10 nm is
deposited by the sputtering process. Moreover, the SRO film 123 is
crystallized by RTA in an oxygen atmosphere. The SRO film 123 with
an excellent crystallinity can be easily formed by depositing the
film at a temperature of, for example, 500.degree. C. Furthermore,
a platinum film 124 of thickness about 50 nm is deposited by the
sputtering process.
[0026] Then, the CVD process is used to deposit a silicon oxide
film (not shown) all over the surface of the resulting structure.
Moreover, the photo lithography process and the RIE process are
used to pattern the silicon oxide film. Subsequently, the patterned
silicon oxide film is used as a mask to etch the platinum film 124,
the SRO film 123, and the PZT film 122 by the RIE process.
Furthermore, the photo lithography process and the RIE process are
used to pattern the SRO film 121, the titanium film 120, the
platinum film 119, the titanium film 118a, the iridium oxide film
117b, the iridium film 117a, and the titanium film 116.
[0027] In this manner, a ferroelectric capacitor is formed which
comprises a bottom electrode having the titanium film 116, the
iridium film 117a, the iridium oxide film 117b, the titanium film
118a, the platinum film 119, the titanium film 120, and the SRO
film 121, and a dielectric film formed of the PZT film 122, and a
top electrode having the SRO film 123 and the platinum film
124.
[0028] In the ferroelectric capacitor forming step described above,
the top electrode film, dielectric film and bottom electrode film
may be patterned by the same lithography and etching process. In
this case, side surfaces of the top electrode, dielectric film and
bottom electrode are positioned substantially within a same
plane.
[0029] Then, the CVD process is used to deposit a silicon oxide
film 125 all over the surface of the ferroelectric capacitor.
Subsequently, to recover from damage to the PZT film 122 during
etching, the capacitor is thermally treated at a temperature of
about 650.degree. C. in an oxygen atmosphere. During the thermal
treatment, the tungsten plug 115 is prevented from being oxidized
because the surface of the tungsten plug 115 is covered with the
iridium film 117a and iridium oxide film 117b, which have an
excellent oxygen barrier characteristic. Further, since the
titanium film 118a is formed on the iridium oxide film 117b, it
blocks the diffusion of the iridium contained in the iridium film
117a and iridium oxide film 117b. It is thus possible to prevent
the iridium from diffusing to the SRO film 121 and the PZT film 122
through the platinum film 119.
[0030] The subsequent steps are not shown. A ferroelectric memory
having a COP (Capacitor On Plug) structure is completed by
subsequently forming a contact connected to the tungsten film 111,
drive lines and bit lines, metal interconnects, and the like.
[0031] FIG. 4 is a graph showing the hysteresis characteristic of a
capacitor formed using a process similar to the above described
process. FIG. 5 is a graph showing the hysteresis characteristic of
a capacitor according to a comparative example. The axis of
abscissa indicates a voltage applied to the capacitor, while the
axis of ordinate indicates the polarization of the capacitor.
[0032] Specifically, for a sample-according to the present
embodiment, the following films are sequentially formed on a
silicon oxide film on a silicon substrate: a titanium film
(thickness: 10 nm), an iridium film (thickness: 100 nm), an iridium
oxide film (thickness: 50 nm), a titanium film (thickness: 2.5 nm),
a platinum film (thickness: 50 nm), a titanium film (thickness: 1.5
nm), an SRO film (thickness: 2.5 nm), a PZT film
(Pb(Zr.sub.0.3Ti.sub.0.7)O.sub.3 film, thickness: 130 nm), an SRO
film (thickness: 10 nm), and a platinum film (thickness: 50
nm).
[0033] For a sample according to the comparative example of the
present embodiment, the following films are sequentially formed on
a silicon oxide film on a silicon substrate: a titanium film
(thickness: 10 nm), an iridium film (thickness: 100 nm), an iridium
oxide film (thickness: 50 nm), a platinum film (thickness: 50 nm),
a titanium film (thickness: 2.5 nm), an SRO film (thickness: 10
nm), a PZT film (Pb(Zr.sub.0.3Ti.sub.0.7)O.sub.3 film, thickness:
130 nm), an SRO film (thickness: 10 nm), and a platinum film
(thickness: 50 nm). That is, the capacitor according to the
comparative example is not provided with any diffusion prevention
film (corresponding to the titanium 118a, shown in FIG. 3).
[0034] Comparison of FIG. 4 (present embodiment) with FIG. 5
(comparative example) clearly indicates that the capacitor
according to the present embodiment has a markedly improved
quantity of switching charges (Q.sub.SW) and a markedly improved
squareness compared to the capacitor of the comparative example.
That is, the capacitor according to the present embodiment has a
markedly improved hysteresis characteristic compared to the
capacitor of the comparative example.
[0035] FIG. 6 is a graph showing the relationship between an x
value and the quantity of switching charges for the
Pb(Zr.sub.xTi.sub.1-x)O.sub.3 film (PZT film) in a sample similar
to that described in FIG. 4.
[0036] As shown in FIG. 6, when the x value is 0.35 or more, the
quantity of switching charges decreases rapidly. That is, when the
x value is 0.35 or more, the capacitor characteristic is rapidly
degraded. Accordingly, to obtain a favorable capacitor
characteristic, it is necessary that the x value is less than 0.35
(0<x<0.35). Further, if the x value is 0.25 or less, it is
generally difficult to form a PZT film with an excellent
crystallinity or the like. Therefore, preferably,
0.25<x<0.35.
[0037] FIG. 7 is a graph showing the XRD pattern of a sample
according to the present embodiment. FIG. 8 is a graph showing the
XRD pattern of a sample according to the comparative example of the
present embodiment. The axis of abscissa indicates angle
(2.theta.), while the axis of ordinate indicates intensity.
[0038] For the sample according to the present embodiment, the
following films are sequentially formed on a silicon oxide film on
a silicon substrate: a titanium film (thickness: 10 nm), an iridium
film (thickness: 100 nm), an iridium oxide film (thickness: 50 nm),
a titanium film (thickness: 2.5 nm), a platinum film (thickness: 50
nm), a titanium film (thickness: 1.5 nm), an SRO film (thickness:
2.5 nm), and a PZT film (Pb(Zr.sub.0.3Ti.sub.0.7)O.sub.3 film,
thickness: 130 nm).
[0039] For the sample according to the comparative example, the
following films are sequentially formed on a silicon oxide film on
a silicon substrate: a titanium film (thickness: 10 nm), an iridium
film (thickness: 100 nm), an iridium oxide film (thickness: 50 nm),
a platinum film (thickness: 50 nm), a titanium film (thickness: 2.5
nm), an SRO film (thickness: 10 nm), and a PZT film
(Pb(Zr.sub.0.3Ti.sub.0.7)O.sub.3 film, thickness: 130 nm). That is,
the capacitor according to the comparative example is not provided
with any diffusion prevention film (corresponding to the titanium
film 118a, shown in FIG. 3).
[0040] For both samples according to the present embodiment and the
comparative example, respectively, each of the PZT film and SRO
film is obtained by forming an amorphous film by sputtering and
then annealing the amorphous film in an oxygen atmosphere for
crystallization.
[0041] Comparison of FIG. 7 (present embodiment) with FIG. 8
(comparative example) clearly indicates that the PZT film of the
sample according to the comparative example has a random
orientation and does not exhibit a favorable crystalliinty. In
contrast, the PZT film of the sample according to the present
embodiment exhibits a (111) orientation peak and thus a very
favorable crystallinity.
[0042] As described above, according to the present embodiment, the
titanium film 118a (diffusion prevention film), which acts as an
effective barrier for the diffusion of the iridium, is provided
between the platinum film 119 (second conductive film) and the
stacked film (first conductive film) made of the iridium film 117a
and the iridium oxide film 117b. This makes it possible to prevent
the iridium from diffusing to the SRO film 121 (third conductive
film) and PZT film 122 (dielectric film) through the platinum film
119. It is in turn possible to suppress the reaction of the iridium
with elements contained in the SRO film or the reaction of the
iridium with elements contained in the PZT film. Consequently, the
degradation of the SRO and PZT films can be prevented. In
particular, by setting the x value for the
Pb(Zr.sub.xTi.sub.1-x)O.sub.3 film (PZT film) at 0<x<0.35,
preferably 0.25<x<0.35, it is possible to obtain a reliable
capacitor with excellent characteristics.
[0043] In general, the iridium oxide film does not exhibit the
(111) orientation. Accordingly, if the platinum film is formed
directly on the iridium oxide film, the platinum film also does not
exhibit a favorable (111) orientation. It is thus not easy to
obtain an SRO film or PZT film (Pb(Zr.sub.xTi.sub.1-x)O.sub.3 film,
0.25<x<0.35) having a favorable (111) orientation. In the
present embodiment, the titanium film is formed between the iridium
oxide film and the platinum film. This allows the platinum film to
be easily (111) oriented, thus making it possible to obtain SRO and
PZT films having a favorable (111) orientation. It is therefore
possible to obtain favorable SRO and PZT films and thus a reliable
capacitor with excellent characteristics.
Embodiment 2
[0044] FIG. 9 is a sectional view schematically showing a method of
manufacturing a semiconductor device according to a second
embodiment of the present invention. The steps executed before the
steps of forming a capacitor are similar to those shown in FIGS. 1
and 2 for the first embodiment.
[0045] After the step shown in FIG. 2 for the first embodiment, the
titanium film 116 of thickness about 10 nm is deposited by the
sputtering process as shown in FIG. 9. Subsequently, as the first
conductive film 117, the iridium (Ir) film 117a of about 100 nm
thickness and the iridium oxide (IrO.sub.2) film 117b of about 50
nm thickness are sequentially deposited by the sputtering process.
Subsequently, a titanium (Ti) film of thickness about 2.5 nm is
deposited by the sputtering process. Moreover, the titanium film is
oxidized by RTA in an oxygen atmosphere to form the titanium oxide
film (TiO.sub.2 film) 118b as a diffusion prevention film. The
titanium oxide film 118b prevents the upward diffusion of the
iridium contained in the iridium film 117a and iridium oxide film
117b. Subsequently, as a second conductive film, the platinum (Pt)
film 119 of thickness about 50 nm is deposited by the sputtering
process. Then, as a seed layer, the titanium film 120 of about 1.5
nm thickness is deposited by the sputtering process. Moreover, as a
third conductive film, the SrRuO.sub.3 film (SRO film) 121 of
thickness about 2.5 nm is deposited on the titanium film 120 by the
sputtering process. Subsequently, the SRO film 121 is crystallized
by RTA in an oxygen atmosphere. The SRO film 121 with an excellent
crystallinity can be easily formed by depositing the film at a
temperature of, for example, 500.degree. C.
[0046] Then, as a dielectric film (ferroelectric film) of the
capacitor, the Pb(Zr.sub.xTi.sub.1-x)O.sub.3 film (PZT film) 122
having a thickness of about 130 nm is formed by the sputtering
process. Moreover, the PZT film 122 is crystallized by RTA in an
oxygen atmosphere. In the present embodiment, the value of x is
0.30. That is, as the PZT film 122, a
Pb(Zr.sub.0.3Ti.sub.0.7)O.sub.3 film is formed.
[0047] Then, the SRO film 123 having a thickness of about 10 nm is
deposited by the sputtering process. Moreover, the SRO film 123 is
crystallized by RTA in an oxygen atmosphere. The SRO film 123 with
an excellent crystallinity can be easily formed by depositing the
film at a temperature of, for example, 500.degree. C. Furthermore,
the platinum film 124 of thickness about 50 nm is deposited by the
sputtering process.
[0048] Then, the CVD process is used to deposit a silicon oxide
film (not shown) all over the surface of the resulting structure.
Moreover, the photo lithography process and the RIE process are
used to pattern the silicon oxide film. Subsequently, the patterned
silicon oxide film is used as a mask to etch the platinum film 124,
the SRO film 123, and the PZT film 122 by the RIE process.
Furthermore, the photo lithography process and the RIE process are
used to pattern the SRO film 121, the titanium film 120, the
platinum film 119, the titanium oxide film 118b, the iridium oxide
film 117b, the iridium film 117a, and the titanium film 116.
[0049] In this manner, a ferroelectric capacitor is formed which
comprises a bottom electrode having the titanium film 116, the
iridium film 117a, the iridium oxide film 117b, the titanium oxide
film 118b, the platinum film 119, the titanium film 120, and the
SRO film 121, a dielectric film formed of the PZT film 122, and a
top electrode having the SRO film 123 and the platinum film
124.
[0050] Then, the CVD process is used to deposit the silicon oxide
film 125 all over the surface of the ferroelectric capacitor.
Subsequently, to recover from damage done to the PZT film 122
during etching, the capacitor is thermally treated at a temperature
of about 650.degree. C. in an oxygen atmosphere. During the thermal
treatment, the tungsten plug 115 is prevented from being oxidized
because the surface of the tungsten plug 115 is covered with the
iridium film 117a and iridium oxide film 117b, which have an
excellent oxygen barrier characteristic. Further, since the
titanium oxide film 118b is formed on the iridium oxide film 117b,
it blocks the diffusion of the iridium contained in the iridium
film 117a and iridium oxide film 117b. It is thus possible to
prevent the iridium from diffusing to the SRO film 121 and the PZT
film 122 through the platinum film 119.
[0051] The subsequent steps are not shown. A ferroelectric memory
having the COP structure is completed by subsequently forming a
contact connected to the tungsten film 111, drive lines and bit
lines, metal interconnects, and the like.
[0052] As described above, according to the present embodiment, the
titanium oxide film 118b is provided between the platinum film 119
(second conductive film) and the stacked film (first conductive
film) made of the iridium film 117a and the iridium oxide film
117b. Thus, as in the case of the first embodiment, it is possible
to obtain favorable SRO and PZT films and thus a reliable capacitor
with excellent characteristics. Also in the present embodiment, the
relationship between the x value and the quantity of switching
charges for the Pb(Zr.sub.xTi.sub.1-x)O.sub.3 film (PZT film)
exhibits a tendency similar to that shown in FIG. 6. Accordingly,
as in the case of the first embodiment, by setting the x value for
the PZT film at 0<x<0.35, preferably 0.25<x<0.35, it is
possible to obtain a reliable capacitor with excellent
characteristics.
[0053] Various changes may be made to the above first and second
embodiments as described below.
[0054] The diffusion prevention film that prevents the diffusion of
the iridium may be a metal film containing at least one of Ti, V,
W, Zr, Co, Mg, Hf, Mo, Mn, Ta, Nb, Pb, and Al. Alternatively, it
may be a metal oxide film containing at least one of Ti, V, W, Zr,
Co, Mg, Hf, Mo, Mn, Ta, Nb, Pb, Al, and Ru. Alternatively, it may
be a stacked film of the above metal film and metal oxide film. The
metal oxide film may typically be a TiO.sub.2 film, a ZrO.sub.2
film, a CoO.sub.2 film, PbO.sub.2 film, Al.sub.2O.sub.3 film, an
SRO film, an Sr(Ru,Ti)O.sub.3 film, or the like. The stacked film
of the metal film and metal oxide film may typically be a Ti/SRO
film, a Ti/Sr(Ru,Ti)O.sub.3 film, a Co/SRO film, a
Co/Sr(Ru,Ti)O.sub.3 film, or the like. The effect of the SRO film
or Sr(Ru,Ti)O.sub.3 film in suppressing the diffusion of iridium is
mainly based on the reaction of iridium with the SRO film or
Sr(Ru,Ti)O.sub.3 film. Specifically, upon reacting with the SRO
film or Sr(Ru,Ti)O.sub.3 film, the iridium is consumed and thus
prevented from diffusing upward. The reaction with the iridium may
degrade the crystallinity of the SRO film or Sr(Ru,Ti)O.sub.3 film.
However, the SRO film or Sr(Ru,Ti)O.sub.3 film, used as a diffusion
prevention film, does not contact with the PZT film. Consequently,
the degraded crystallinity does not substantially affect the PZT
film or the like.
[0055] The first conductive film may be a single film of iridium
(Ir), a single film of iridium oxide (IrO.sub.2), or a stacked film
of the iridium film and iridium oxide film.
[0056] The second conductive film may be a noble metal film
including at least one of a platinum film and a ruthenium film.
[0057] The third conductive film may be a conductive metal oxide
film having a perovskite crystal structure (general formula:
ABO.sub.3) and containing at least one of Ru, Co, and Ni.
Typically, the third conductive film may be an SrRuO.sub.3 film, a
(La,Sr)CoO.sub.3 film, a BaRuO.sub.3 film, an LaNiO.sub.3 film, or
the like.
[0058] The dielectric film may be an insulating metal oxide film
having a perovskite structure expressed by
A(Zr.sub.xTi.sub.1-x)O.sub.3 (A denotes at least one A site
element, 0<x<0.35, preferably 0.25<x<0.35). In
particular, an insulating metal oxide film containing Pb as an A
site element is desirably used. The insulating metal oxide film may
typically be a Pb(Zr.sub.xTi.sub.1-x)O.sub.3 film (PZT film), a
(Pb,La) (Zr.sub.xTi.sub.1-x)O.sub.3 film, or the like.
[0059] The plug may be a tungsten plug or a polysilicon plug.
[0060] The diffusion prevention film, the first conductive film,
the second conductive film, the third conductive film, and the
dielectric film may be formed using the sputtering process, the CVD
process, or a sol-gel process.
[0061] The structure described in the foregoing embodiments can be
applicable to a series connected TC unit type ferroelectric memory,
which includes series connected memory cells each having a
transistor having a source terminal and a drain terminal and a
ferroelectric capacitor between the two terminals.
[0062] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
* * * * *