U.S. patent application number 10/303850 was filed with the patent office on 2006-05-11 for multilayer type printed-wiring board and method of measuring impedance of multilayer type printed-wiring board.
Invention is credited to Hiroyuki Fujita, Shoji Horie, Takashi Ishikawa, Takaharu Okubo.
Application Number | 20060096779 10/303850 |
Document ID | / |
Family ID | 18581955 |
Filed Date | 2006-05-11 |
United States Patent
Application |
20060096779 |
Kind Code |
A1 |
Okubo; Takaharu ; et
al. |
May 11, 2006 |
Multilayer type printed-wiring board and method of measuring
impedance of multilayer type printed-wiring board
Abstract
The impedance of a newly manufactured data transmission wire
pattern can be measured easily and accurately. A multilayer type
printed-wiring board 1 comprises a pair of data transmission wire
patterns 4, 5 arranged between a CPU module 2 and a memory module 3
on respective inner layer substrates 6, 7, impedance measuring wire
patterns 21 and 22 arranged respectively in the layers same as
those of the data transmission wire patterns 4, 5, a prepreg layer
11 arranged on the impedance measuring wire patterns 21, 22, land
sections 23, 23 for signals arranged on the prepreg layer 11 and
electrically connected to the impedance measuring wire patterns 21,
22 so as to be brought into contact with the signal terminal 41 of
a probe 40 and a GND land section 24 also arranged on the prepreg
layer 11 and electrically connected to the impedance measuring wire
patterns 21, 22 so as to be brought into contact with the GND
terminal 42 of the probe 40, the impedance measuring wire patterns
21, 22 having a pattern length not smaller than 30 mm that is the
minimal length required for use with a TDR unit and a pattern width
same as that of the data transmission wire patterns 4, 5.
Inventors: |
Okubo; Takaharu; (Ishikawa,
JP) ; Ishikawa; Takashi; (Ishikawa, JP) ;
Fujita; Hiroyuki; (Ishikawa, JP) ; Horie; Shoji;
(Ishikawa, JP) |
Correspondence
Address: |
RADER FISHMAN & GRAUER PLLC
LION BUILDING
1233 20TH STREET N.W., SUITE 501
WASHINGTON
DC
20036
US
|
Family ID: |
18581955 |
Appl. No.: |
10/303850 |
Filed: |
November 26, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09793977 |
Feb 28, 2001 |
6512181 |
|
|
10303850 |
Nov 26, 2002 |
|
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Current U.S.
Class: |
174/260 |
Current CPC
Class: |
G01R 31/2818 20130101;
G01R 31/2822 20130101; G01R 31/2812 20130101; H05K 1/0268
20130101 |
Class at
Publication: |
174/260 |
International
Class: |
H05K 1/16 20060101
H05K001/16 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 2, 2001 |
JP |
P2000-061874 |
Claims
1. A multilayer type printed-wiring board comprising; a first
insulating layer; a data transmission wire pattern arranged on said
first insulating layer and adapted to data transmission between a
CPU module and a main memory module to be used for the CPU; an
impedance measuring wire pattern arranged on said first insulating
layer in the layer same as that of said data transmission wire
pattern with a predetermined clearance to any adjacent wiring
pattern; a second insulating layer arranged on said data
transmission wire pattern and said impedance measuring wire
pattern; and land sections for signals arranged on said second
insulating layer and electrically connected to said impedance
measuring wire pattern arranged on said first insulating layer by
way of a through hole so as to be held in contact with the signal
terminal of the probe for measuring the impedance of said impedance
measuring wire pattern and a GND (grounding) land section held in
contact with the GND terminal of said probe; said impedance
measuring wire pattern having a pattern length not smaller than
about 30 mm and a pattern width same as that of said data
transmission wire pattern.
2. The multilayer type printed-wiring board according to claim 1,
wherein the transmission frequency of said data transmission wire
pattern is not less than 130 MHz.
3. The multilayer type printed-wiring board according to claim 1,
wherein the clearance between said impedance measuring wire pattern
and any adjacent wiring pattern is not less than twice of the
pattern width of said impedance measuring wire pattern.
4. The multilayer type printed-wiring board according to claim 1,
wherein the wiring pattern arranged around the impedance measuring
wire pattern is a GND pattern connected to said GND land section by
way of a plurality of through holes.
5. The multilayer type printed-wiring board according to claim 1,
wherein a plurality of impedance measuring wire patterns are
arranged in different layers and electrically connected to each
other by way of through holes.
6. A method of measuring the impedance of a multilayer type
printed-wiring board comprising: a first insulating layer; a data
transmission wire pattern arranged on said first insulating layer
and adapted to data transmission between a CPU module and a main
memory module to be used for the CPU; an impedance measuring wire
pattern arranged on said first insulating layer in the layer same
as that of said data transmission wire pattern with a predetermined
clearance to any adjacent wiring pattern; a second insulating layer
arranged on said data transmission wire pattern and said impedance
measuring wire pattern; land sections for signals arranged on said
second insulating layer and electrically connected to said
impedance measuring wire pattern arranged on said first insulating
layer by way of a through hole so as to be held in contact with the
signal terminal of the probe for measuring the impedance of said
impedance measuring wire pattern and a GND (grounding) land section
held in contact with the GND terminal of said probe; and said
impedance measuring wire pattern having a pattern length not
smaller than about 30 mm and a pattern width same as that of said
data transmission wire pattern; said method comprising a step of:
measuring the impedance of said impedance measuring wire pattern by
bringing the signal terminal and the GND terminal of said probe
into contact respectively with said land sections for signal and
said GND land section.
7. The method of measuring the impedance of a multilayer type
printed-wiring board according to claim 6, wherein the transmission
frequency of said data transmission wire pattern is not less than
130 MHz.
8. The method of measuring the impedance of a multilayer type
printed-wiring board according to claim 6, wherein the clearance
between said impedance measuring wire pattern and any adjacent
wiring pattern is not less than twice of the pattern width of said
impedance measuring wire pattern.
9. The method of measuring the impedance of a multilayer type
printed-wiring board according to claim 6, wherein the wiring
pattern arranged around the impedance measuring wire pattern is a
GND pattern connected to said GND land section by way of a
plurality of through holes.
10. The method of measuring the impedance of a multilayer type
printed-wiring board according to claim 6, wherein a plurality of
impedance measuring wire patterns are arranged in different layers
and electrically connected to each other by way of through
holes.
11. The method of measuring the impedance of a multilayer type
printed-wiring board according to claim 10, wherein the impedances
of said wiring patterns arranged in different layers are measured
by measuring said plurality of impedance measuring patterns
arranged in different layers in a single measuring operation.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to a multilayer type printed-wiring
board provided with a checking coupon for measuring the
characteristic impedance of the data transmission wire pattern
arranged between a CPU module and a memory module.
[0003] 2. Related Background Art
[0004] Electronic devices such as game machines for home use and
mobile telephone sets typically comprises a printed-wiring board
arranged in the cabinet thereof and a CPU (central processing unit)
module and a main memory module are mounted there along with other
modules. The CPU module and the memory module are connected to each
other by a data transmission wire pattern arranged on the
printed-wiring board.
[0005] Meanwhile, the data transmission wire pattern of a
printed-wiring board have to be designed in such a way that the
impedance of the wire pattern shows a value that corresponds to the
impedance specified for the CPU module and the memory module
mounted on the printed-wiring board so that the CPU and the memory
may operate reliably on a stable basis.
[0006] However, some of the data transmission wire patterns of the
printed-wiring boards shipped from manufacturing plants after the
completion of the manufacturing process can show discrepancies
between the design values and the actual values due to various
reasons including the conditions for etching copper foils in the
data transmission wire patterns to consequently give rise to an
impedance greater or smaller than the design value. When the
impedance does not agree with the design value, it is no longer
possible to transmit exchange signals between the CPU module and
the memory module.
BRIEF SUMMARY OF THE INVENTION
[0007] In view of the above circumstances, it is therefore an
object of the present invention to provide a novel multilayer type
printed-wiring board adapted to measuring the impedance of the data
transmission wire pattern on the manufacturing floor in an easy and
simple fashion.
[0008] Another object of the present invention is to provide a
multilayer type printed-wiring board comprising a pair of data
transmission wire patterns arranged at the opposite sides of the
inner layer substrate and adapted to measuring the impedances of
the two data transmission wire patterns in a single measuring
operation to improve the efficiency of the measurement process.
[0009] According to the invention, the above objects are achieved
by providing a multilayer type printed-wiring board comprising;
[0010] a first insulating layer;
[0011] a data transmission wire pattern arranged on said first
insulating layer and adapted to data transmission between a CPU
module and a main memory module to be used for the CPU;
[0012] an impedance measuring wire pattern arranged on said first
insulating layer in the layer same as that of said data
transmission wire pattern with a predetermined clearance to any
adjacent wiring pattern;
[0013] a second insulating layer arranged on said data transmission
wire pattern and said impedance measuring wire pattern; and
[0014] land sections for signals arranged on said second insulating
layer and electrically connected to said impedance measuring wire
pattern arranged on said first insulating layer by way of a through
hole so as to be held in contact with the signal terminal of the
probe for measuring the impedance of said impedance measuring wire
pattern and a GND (grounding) land section held in contact with the
GND terminal of said probe;
[0015] said impedance measuring wire pattern having a pattern
length not smaller than about 30 mm and a pattern width same as
that of said data transmission wire pattern when using a TDR (time
domain reflectometer) unit.
[0016] As pointed out above, the impedance measuring wire pattern
for measuring the impedance of the multilayer type printed-wiring
board is arranged in the layer same as that of the data
transmission wire pattern adapted to data transmission between the
CPU module and the main memory module to be used for the CPU, for
which a certain level of impedance have to be secured.
[0017] Preferably, the transmission frequency of said data
transmission wire pattern of said multilayer type printed-wiring
board is not less than 130 MHz so as to allow high speed data
transmissions.
[0018] Preferably, the clearance between said impedance measuring
wire pattern of said multilayer type printed-wiring board and any
adjacent wiring pattern is not less that twice of the pattern width
of said impedance measuring wire pattern so as not to have any
interference of the adjacent wiring pattern.
[0019] Preferably, the wiring pattern arranged around the impedance
measuring wire pattern of the multilayer type printed-wiring board
is a GND pattern connected to said GND land section by way of a
plurality of through holes so as to eliminate any inductance
component.
[0020] Still preferably, when a plurality of data transmission wire
patterns are arranged in different layers in said multilayer type
printed-wiring board, a plurality of impedance measuring wire
patterns are arranged in different layers in correspondence to the
respective data transmission wire patterns and electrically
connected to each other by way of through holes.
[0021] Thus, with a multilayer type printed-wiring board according
to the invention, since an impedance measuring wire pattern is
arranged in the layer of the data transmission wire pattern and the
pattern width that affects the impedance of the device is made
equal to that of the data transmission wire pattern so that the
impedance of the data transmission wire pattern can be measured
accurately by means of a method of measuring the impedance of a
multilayer type printed-wiring board according to the invention.
The impedance of a multilayer type printed-wiring board can be
measured accurately by means of a TDR (time domain reflectometer)
unit when the impedance measuring wire pattern has a pattern length
not smaller than about 30 mm.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0022] FIG. 1 is a schematic plan view of an embodiment of
multilayer type printed-wiring board according to the
invention;
[0023] FIG. 2 is a schematic cross sectional view of a principal
part of the multilayer type printed-wiring board of FIG. 1;
[0024] FIG. 3 is an exploded schematic perspective view of a
checking pattern arranged on the multilayer type printed-wiring
board of FIG. 1;
[0025] FIG. 4A is a schematic plan view of the checking pattern of
FIG. 3 and FIG. 4B is a schematic cross sectional view of the
checking pattern of FIG. 3.
[0026] FIG. 5 is a schematic perspective view of a principal part
of the multilayer type printed-wiring board of FIG. 1 being
measured for impedance by means of a TDR unit;
[0027] FIG. 6 is a graph illustrating the waveform of the impedance
of the multilayer type printed-wiring board of FIG. 1; and
[0028] FIG. 7 is a schematic cross sectional view of another
embodiment of multilayer type printed-wiring board according to the
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0029] Now, a multilayer type printed-wiring board and a method of
measuring the impedance of a multilayer type printed-wiring board
according to the invention will be described in greater detail by
referring to the accompanying drawing. FIG. 1 is a schematic plan
view of an embodiment of multilayer type printed-wiring board
according to the invention. The multilayer type printed-wiring
board 1 has a total of six electro-conductive layers and is adapted
to be used in a game machine for home use.
[0030] Referring to FIG. 1, the multilayer type printed-wiring
board 1 comprises a CPU (central processing unit) module 2 and a
pair of memory modules 3, 3 to be used for the CPU module 2 that
are arranged on one of the opposite sides of the multilayer type
printed-wiring board 1. The CPU module 2 has an operating frequency
higher than that of any ordinary CPU and is adapted to operate at a
frequency above about 290 MHz or more and typically between 300 MHz
and 400 MHz so that it may be able to operate for a high speed
image processing operation at a rate of 66 million polygons per
second. The memory modules 3, 3 operate as main memory of the CPU
module 2, each having a memory capacity of 128 Mbytes. The memory
modules 3, 3 are adapted to high speed serial data transmission
between the CPU module 2 and themselves and typically comprises so
many RDRAMs (Direct Rambus Dynamic Random-access Memories:
trademark, available from Rambus Technology).
[0031] The printed-wiring board 1 carrying the CPU module 2 and the
memory modules 3, 3 further comprises data transmission wire
patterns 4, 5 operating as data transmission paths between the CPU
module 2 and the memory modules 3, 3 and arranged respectively in
the inner layers of the second layer and the fourth layer as shown
in FIG. 2. The data transmission wire patterns 4, 5 are designed to
show a transmission frequency equal to or slightly higher than the
operating frequency of the CPU module 2 so that they may
effectively operate for high speed data transmissions between the
CPU module 2 and the memory modules 3, 3. More specifically, the
data transmission wire patterns 4, 5 are designed to show a
transmission frequency of about 400 MHz so as to correspond to the
operating frequency between 300 MHz and 400 MHz of the CPU module
2.
[0032] The data transmission wire patterns 4, 5 are additionally
designed to show an impedance with a permissible error range
specified for the CPU module 2 and the memory modules 3, 3 so that
the CPU module 2 and the memory modules 3, 3 may accurately
identify signals and electric power is less consumed in a high
speed data transmission. More specifically, the data transmission
wire patterns 4, 5 are designed to show an impedance of
40.+-.4.OMEGA. same as the one specified for the CPU module 2 and
the memory modules 3, 3 including the permissible error range.
[0033] The layered structure of the above described embodiment of
multilayer type printed-wiring board 1 will be discussed below.
Referring now to FIG. 2, the multilayer type printed-wiring board 1
comprises first and second inner layer substrates 6, 7. Of these,
the inner layer substrate 6 carries on one of the surfaces thereof
the data transmission wire pattern 4 of the second layer and on the
other surface thereof a wiring pattern 8 that operates as a GND
layer and forms the third layer. On the other hand, the inner layer
substrate 7 carries on one of the surfaces thereof the data
transmission wire pattern 5 of the fourth layer and on the other
surface thereof a wiring pattern 9 that operates as a power supply
layer and forms the fifth layer. Then, the inner layer substrates
6, 7 carrying thereon respectively the wiring pattern 8 of the
third layer and the data transmission wire pattern 5 of the fourth
layer that are arranged vis-a-vis are pressed and bonded together
with a prepreg layer 10 interposed therebetween, said prepreg layer
10 being made of glass fibers impregnated with epoxy resin.
[0034] Another wiring pattern 12 that operates as a GND layer and
forms the first layer is arranged on the inner layer substrate 6
with another prepreg layer 11 interposed therebetween. Still
another wiring pattern 14 that operates as a signal layer and forms
the sixth layer is arranged on the inner layer substrate 7 with
still another prepreg layer 13 interposed therebetween. Thus, the
multilayer printed-wiring board 1 having the above listed layers
shows a strip line structure, in which the data transmission wire
pattern 4 is sandwiched by the inner layer substrate 6 that
operates as an insulating layer and the prepreg layer 11 and the
insulating layer is provided on the opposite surfaces thereof with
the respective wiring patterns 8, 12, whereas the data transmission
wire pattern 5 is sandwiched by the inner layer substrate 7 that
operates as an insulating layer and the prepreg layer 10 and the
insulating layer is provided on the opposite surfaces thereof with
the respective wiring patterns 8, 9.
[0035] Meanwhile, the above described data transmission wire
pattern 4, 5 are required to show an impedance equal to
40.+-.4.OMEGA. in order for each of the CPU modules 2 and the
memory modules 3, 3 to accurately recognize signals and realize a
high speed data transmission therebetween. For this purpose the
multilayer type printed-wiring board 1 is provided with checking
coupons 16, 17 for checking the respective impedances of the data
transmission wire patterns 4, 5. More specifically, the impedance
measuring wire patterns of the checking coupons 16, 17 are arranged
in the respective layers of the data transmission wire patterns 4,
5 and the impedances of the impedance measuring wire patterns are
observed by a TDR unit. To be more accurate, each of the checking
coupons 16, 17 occupies two separates positions in order to
accurately check the impedance of the data transmission wire
pattern 16 or 17, whichever appropriate. Since both the checking
coupons 16, 17 have a same configuration, only the checking coupon
16 will be described below.
[0036] Referring to FIG. 3, the checking coupon 16 comprises a
first impedance measuring wire pattern 21 for measuring the
impedance on one of the opposite surfaces of the inner layer
substrate 6 that operates as an insulating layer, a second
impedance measuring wire pattern 22 for measuring the impedance on
one of the opposite surfaces of the inner layer substrate 7 that
operates as an insulating layer and land sections including land
sections 23, 23 for signals and a GND land section 24 arranged on
the prepreg 11 operating as an insulating layer.
[0037] The first impedance measuring wire pattern 21 arranged on
one of the opposite surfaces of the inner layer substrate 6 is
found in the second layer same as the data transmission wire
pattern 4 and made to show a pattern width and a pattern height
same as those of the data transmission wire pattern 4 so that its
impedance characteristics may be identical with those of the data
transmission wire pattern 4. The first impedance measuring wire
pattern 21 is provided at an end thereof with a first connecting
section 21a for establishing electric connection with one of the
land sections 23, 23 for signals that is brought into contact with
the probe arranged in the first layer and at the other end thereof
with a second connecting section 21b for establishing electric
connection with the second impedance measuring wire pattern 22. The
first impedance measuring wire pattern 21 is also provided with a
peripheral clearance 26 for preventing any electric interference of
the wiring pattern 25 arranged adjacently relative to it. The
clearance 26 has a width more than twice, preferably more than
three times, of the width W1 of the first impedance measuring wire
pattern 21 in order to reliably eliminate any interference of the
wiring pattern 25. In this embodiment, the wiring pattern 25
operates as GND (ground). The first impedance measuring wire
pattern 21 is formed in the step of patterning the copper foil
bonded onto the inner layer substrate 6 of the second layer.
[0038] On the other hand, the second impedance measuring wire
pattern 22 arranged on one of the opposite surfaces of the inner
layer substrate 7 is found in the fourth layer same as the data
transmission wire pattern 5 and made to show a pattern width and a
pattern height same as those of the data transmission wire pattern
5 so that its impedance characteristics may be identical with those
of the data transmission wire pattern 5. The second impedance
measuring wire pattern 22 is provided at an end thereof with a
first connecting section 22a for establishing electric connection
with the second connecting section 21b of the first impedance
measuring wire pattern 21 arranged in the second layer and at the
other end thereof with a second connecting section 22b for
establishing electric connection with the other land section 23 for
signals arranged in the first layer. The second impedance measuring
wire pattern 22 is also provided with a peripheral clearance 28 for
preventing any electric interference of the wiring pattern 27
arranged adjacently relative to it. The clearance 28 has a width
more than twice, preferably more than three times, of the width W2
of the second impedance measuring wire pattern 22 in order to
reliably eliminate any interference of the wiring pattern 27. In
this embodiment, the wiring pattern 27 operates as GND (ground).
The first impedance measuring wire pattern 22 is formed in the step
of patterning the copper foil bonded onto the inner layer substrate
7 of the fourth layer.
[0039] The prepreg layer 11 is formed on the first impedance
measuring wire pattern 21 arranged on one of the surfaces of the
inner layer substrate 6 and the land section 23 for signals to be
brought into contact with the probe of the TDR unit for measuring
impedances and the GND land section 24 are arranged in part of the
wiring pattern 12 of the GND layer that is by turn arranged on the
prepreg layer 11. The land sections 23, 23 for signals are made to
show a substantially circular profile and the GND land 24 is
arranged around the outer peripheries of the land sections 23, 23
for signals with the clearances 29 separating them from each other
in order to electrically isolate it from the land sections 23, 23
for signals as part of the wiring pattern 12 arranged around the
prepreg layer 11 and operating as GND.
[0040] Now, the electric connections between the land sections 23,
23 and 24 of the first layer, the first impedance measuring wire
pattern 21 of the second layer and the second impedance measuring
wire pattern 22 of the fourth layer will be described below. The
first impedance measuring wire pattern 21 and the second impedance
measuring wire pattern 22 are electrically connected to each other
by way of the second connecting section 21b of the second impedance
measuring wire pattern and the first connecting section 22a of the
second impedance measuring wire pattern 22 illustrated in FIGS. 2
and 3. As shown in FIGS. 2 and 3, the second connecting section 21b
of the second impedance measuring wire pattern 21 and the first
connecting section 22a of the second impedance measuring wire
pattern 22 are electrically connected to each other by bonding the
inner layer substrates 6, 7 with the prepreg layer 6 interposed
therebetween, subsequently boring a through hole 31 running through
the second connecting section 21b and first connecting section 22a
by means of a drill and forming a plating layer (not shown) on the
inner wall of the through hole by means of a non-electrolytic or
electrolytic plating method.
[0041] One of the land sections 23, 23 for signals of the first
layer is electrically connected to the first connecting section 22a
of the first impedance measuring wire pattern 21 of the second
layer. On the other band, the other land section 23 for signals and
the first connecting section 22a are electrically connected to each
other by boring a through hole 32 through the center of the land
section 23 for signals of the substrate integrally that is formed
by laying the prepreg layer 11 where the copper foil of the first
layer is bonded to the inner layer substrates 6, 7 that are bonded
to each other on the prepreg layer 13 where the copper foil of the
sixth layer is bonded and bonding the two prepreg layers together
in a press process and subsequently forming a plating layer on the
inner wall of the through hole 32.
[0042] The other land section 23 of the first layer is electrically
connected to the second connecting section 22b of the second
impedance measuring wire pattern 22 of the fourth layer. To be more
accurate, the other land section 23 for signals and the second
connecting section 22b become electrically connected to each other
by forming a plating layer (not shown on the inner wall of a
through hole 33 that is formed simultaneously with the above
described through hole 32.
[0043] Meanwhile, the first and second impedance measuring wire
patterns 21, 22 are made to have a length L that is not less than
about 30 mm in order to ensure that the impedance measured by means
of a TDR unit shows a stable waveform.
[0044] In the case of this embodiment, the applicable transmission
frequency of the first and second impedance measuring wire pattern
21, 22 arranged respectively in the layers of the data transmission
wire patterns 4, 5 is 400 MHz. Therefore, if a digital signal of
400 MHz is transmitted as a base band signal, the use of a band of
1.2 GHz is required. Since .times. .times. the .times. .times.
effective .times. .times. wavelength .times. .times. .lamda.
.times. .times. .times. is .times. .times. .times. expressed
.times. .times. by .times. .times. .times. formula .times. .times.
C .times. .times. 0 .times. .times. ( light .times. .times. .times.
velocity .times. .times. in .times. .times. .times. vacuum ) =
.lamda. .times. .times. 0 .times. ( wavelength ) f .function. (
frequency ) , .lamda. .times. .times. 0 = C .times. .times. 0 / f =
( 3 108 ) / ( 1.2 107 ) = 2.5 10 - 1 = 0.25 .times. ( m ) = 250
.times. ( mm ) ##EQU1## is obtained.
[0045] Therefore, the effective wavelength .lamda. in a conductor
is expressed by [Formula 1] below. .lamda. .function. ( effective
.times. .times. wavelength ) = .lamda. 0 / .times. .times. eff
.function. ( coefficient .times. .times. of .times. .times. self
.times. - .times. induction ) = 0.25 / 4 = 0.125 .times. ( m ) =
125 .times. mm ##EQU2##
[0046] When measuring impedances by means of a TDR unit, the
minimal length, or min L, of the data transmission wire patterns 4,
5 is expressed by formula below. min L=.lamda./4=0.125/4=0.03125
(m).apprxeq.30 (mm) [Formula 1]
[0047] Note that min L is made equal to a quarter of the effective
wavelength, or .lamda./4, because it is the minimum length
necessary for reproducing the original waveform, taking the
influence of reflections and other factors due to mismatched
impedances into consideration.
[0048] In other words, the data transmission wire patterns 4, 5 are
required to have a minimal length expressed by formula below in
order to measure the impedances thereof by means of a TDR unit. min
L.gtoreq.(applicable transmission frequency.times.3)/4
[0049] In this embodiment, a length of 65 mm is selected because it
represents the most table value as shown in Table 1 below.
TABLE-US-00001 TABLE 1 pattern length L (mm) less than 30 30 50 55
60 65 70 90 100 or more measured unmeasurable 52.1 51.5 51.3 51.1
51.1 51.1 51.1 51.1 value (.OMEGA.)
[0050] Meanwhile, as shown in FIGS. 4A and 4B, the wiring pattern
12 that operates as part of the checking pattern 16, the wiring
pattern 25 of the second layer and the wiring pattern 27 of the
fourth layer are electrically connected to each other by way of the
plating layer (not shown) on the inner surfaces of the plurality of
through holes 34 so as to eliminate any inductance component of the
wiring patterns 25, 27. The through holes 34 are arranged at a
pitch as defined below. gap P (mm).ltoreq.(propagation
velocity)/(4.times.thrice of applicable frequency)
.ltoreq.(wavelength at 1.2 GHz in copper)/4 .ltoreq.125 (mm)/4
.ltoreq.31.25 (mm)
[0051] The above described checking patterns 16, 17 are used to
measure the impedances of the data transmission wire patterns 16,
17 of the multilayer type printed-wiring board 1. A TDR (time
domain reflectometer) unit is typically used to observe the
impedances. As shown in FIG. 5, a TDR unit comprises a probe 40
that is provided with signal terminals 41, 41 to be held in contact
with the respective land sections 23, 23 for signals, to which a
voltage is applied, and a GND terminal 42 to be held in contact
with the GND land section 24. From the viewpoint of the checking
patterns 16, 17, the signal terminals 41 are brought into contact
with the respective land sections 23, 23 for signals and the GND
terminal 42 is brought into contact with the GND land section 24
when measuring the impedances. The TDR unit is used to measure the
impedances of the first and second impedance measuring patterns 21,
22 by determining the ratio of the voltage of the incident wave to
that of the reflected wave as shown in FIG. 6.
[0052] Referring to FIG. 3, since the first impedance measuring
pattern 21 and the second impedance measuring pattern 22 of the
multilayer type printed-wiring board 1 are electrically connected
to each other, it is possible to measure both the impedance of the
first impedance measuring pattern 21 arranged in the second layer
and that of the second impedance measuring pattern 22 arranged in
the fourth layer in a single measuring session. In other words, the
TDR unit can measure both the impedance of the first impedance
measuring pattern 21 and that of the second impedance measuring
pattern 22 by counting the elapsed time since the start of the
measuring session.
[0053] Referring to FIG. 6 showing the waveform displayed on the
monitoring screen of the TDR unit, the observed impedance
fluctuates at point A that corresponds to the land sections 23, 23
and then fluctuates again at point B that corresponds to the second
connecting section 21a and the first connecting section 22a
connecting the first impedance measuring pattern 21 and the second
impedance measuring pattern 22. Thereafter, the observed impedance
fluctuates once again at point C that corresponds to the second
connecting section 22b of the second impedance measuring pattern
22. The observed impedance is held to a constant level both in the
interim between point A and point B and in the interim between
point B and point C. Therefore, when the impedance is visually
observed, it is possible to check the impedance of the first
impedance measuring pattern 21 and that of the second impedance
measuring pattern 22 by locating point A, point B and point C where
the impedance fluctuates in the waveform of impedance.
[0054] With the above described multilayer type printed-wiring
board 1, the impedances of the data transmission wire patterns 4, 5
can be controlled in a simple manner because the first impedance
measuring pattern 21 and the second impedance measuring pattern 22
having a width and a height same as those of the data transmission
wire patterns 4, 5 that are arranged in inner layers are located
respectively in the layers same as those of the data transmission
wire patterns 4, 5. Additionally, as shown in FIG. 3, the
impedances of the wiring patterns arranged in different layers can
be measured in a single measuring session to remarkably reduce the
time required for the checking process because the first impedance
measuring pattern 21 and the second impedance measuring pattern 22
are electrically connected to each other by way of the second
connecting section 21b and the first connecting section 22a.
[0055] While the present invention is described above in terms of a
six-layered printed-wiring board 1, the present invention is by no
means limited thereto and may also be applied to a printed-wiring
board as shown in FIG. 7.
[0056] Referring to FIG. 7, the printed-wiring board 50 comprises
two electro-conductive layers and a first wiring pattern 52
operating as a GND layer is arranged on one of the surfaces of
substrate 51 while a second wiring pattern 53 operating as a signal
layer is arranged on the other surface of the substrate 51. With a
printed-wiring board 50 having such a configuration, it may be so
arranged that land sections for signals and a GND land section are
provided at the side of the first wiring pattern 53 and a measuring
probe is provided at the side of the second wiring pattern 52.
* * * * *