U.S. patent application number 11/079708 was filed with the patent office on 2006-04-13 for pin photodiode structure and fabrication process for reducing dielectric delamination.
Invention is credited to Alex Ceruzzi, Xiang Gao, Mark Gottfried, Linlin Liu, Steve Schwed.
Application Number | 20060076589 11/079708 |
Document ID | / |
Family ID | 36144390 |
Filed Date | 2006-04-13 |
United States Patent
Application |
20060076589 |
Kind Code |
A1 |
Gao; Xiang ; et al. |
April 13, 2006 |
PIN photodiode structure and fabrication process for reducing
dielectric delamination
Abstract
A PIN photodiode, and a method of manufacturing a PIN photodiode
that reduces dielectric delamination and increases device
reliability. The process proceeds by forming an first type
electrode layer on the substrate; forming an intrinsic layer of the
first type electrode layer; forming a second type electrode layer
on the intrinsic layer; etching the second type electrode layer to
define a mesa shaped structure; and depositing a passivation
material over the mesa shaped structure.
Inventors: |
Gao; Xiang; (Edison, NJ)
; Ceruzzi; Alex; (Princeton Junction, NJ) ;
Schwed; Steve; (Bridgewater, NJ) ; Liu; Linlin;
(Hillsborough, NJ) ; Gottfried; Mark;
(Hillsborough, NJ) |
Correspondence
Address: |
Casey Toohey;Emcore Corporation
1600 Eubank Blvd. SE
Albuquerque
NM
87123
US
|
Family ID: |
36144390 |
Appl. No.: |
11/079708 |
Filed: |
March 14, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60613099 |
Sep 27, 2004 |
|
|
|
Current U.S.
Class: |
257/292 ;
257/E31.061; 257/E31.12 |
Current CPC
Class: |
H01L 31/02161 20130101;
H01L 31/105 20130101 |
Class at
Publication: |
257/292 |
International
Class: |
H01L 31/113 20060101
H01L031/113 |
Claims
1. A PIN photodiode comprising: a substrate; a first type electrode
layer disposed on the substrate; an intrinsic layer, including a
first lower region having a first length, and a second upper region
having a second length, smaller than the first length, disposed
over a portion of the first-type electrode layer; a second type
electrode layer disposed over at least a portion of the intrinsic
layer so as to form a mesa shaped structure; and a passivation
layer disposed over the mesa shaped structure.
2. A photodiode as defined in claim 1, wherein said lower and upper
regions are substantially circular in shape.
3. A photodiode as defined in claim 1, wherein said lower and upper
regions are annular regions.
4. A photodiode as defined in claim 1, wherein said first type
electrode layer is disposed over substantially the entire upper
surface of said upper region.
5. A photodiode as defined in claim 1, further comprising a contact
layer disposed over a portion of said first type electrode
layer.
6. A photodiode as defined in claim 1, wherein the first type
electrode layer is an n-type cathode layer. A method of
manufacturing a PIN photodiode to reduce dielectric delamination
comprising: providing a substrate: forming an first type electrode
layer on the substrate; forming an intrinsic layer on the first
type electrode layer; forming a second type electrode layer on the
intrinsic layer; etching the second type electrode layer to define
a mesa shaped structure; and depositing a passivation material over
the mesa shaped structure.
7. A PIN photodiode comprising: a semi-insulating substrate; an
n-type electrode layer disposed on the substrate; an intrinsic
layer, including a first lower region having a first lateral
length, and a second upper region having a second lateral length,
smaller than the first length, said intrinsic layer being disposed
over a portion of the n-type cathode layer; a p-type electrode
layer disposed over at least a portion of the intrinsic layer; and
a passivation layer disposed over the p-type electrode layer, the
intrinsic layer, and the n-type electrode layer.
8. A vertical PIN photodiode comprising: a substrate; a first type
electrode layer disposed on the substrate; an intrinsic layer
disposed on the first type electrode layer; a second type electrode
layer disposed over the intrinsic layer; a trench etched through
the electrode and intrinsic layers into the substrate; a layer of
passivation material disposed over the second type electrode layer
and in the trench.
9. The photodiode as defined in claim 8, wherein the passivation
material is composed of polyimide.
10. A method of manufacturing a PIN photodiode to reduce dielectric
delamination comprising: providing a substrate; forming an first
type electrode layer on the substrate; forming an intrinsic layer
on the first type electrode layer; forming a second type electrode
layer on the intrinsic layer; etching the second type electrode
layer to define a mesa shaped structure; and depositing a
passivation material over the mesa shaped structure.
11. The method as defined in claim 10, wherein the step of etching
the second type electrode layer includes etching a portion of the
intrinsic layer.
12. The method as defined in claim 10, wherein the step of etching
the second type electrode layer includes stopping the etching
process before etching a portion of the intrinsic layer.
13. The method as defined in claim 11, wherein the step of etching
the intrinsic layer removes from five to fifteen microns of
sidewall depth.
14. A method of manufacturing a PIN photodiode to reduce the
dielectric delamination comprising; providing a substrate; forming
a first type electrode layer on the substrate; forming an intrinsic
layer on the first type electrode layer; forming a second type
electrode layer on the intrinsic layer; etching a trench through
the second type electrode layer on the intrinsic layer, the first
type electrode layer, and to define an enclosed region forming a
PIN diode; and depositing a passivation material in the trench.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates generally to PIN photodiodes. More
particularly, the invention relates to a PIN photodiode
semiconductor structure diodes used in high temperature, high
humidity environments, and processes for fabrication of such
devices.
[0003] 2. Description of the Related Art
[0004] Fiber optic communications typically employ a modulated
light source, such as a laser, a photodiode light detector, and an
optical fiber interconnecting the laser and the photodiode. The
laser is modulated to emit light pulses that are transmitted over
an optical fiber and received at a remote unit that includes a
photodiode to convert the optical signal into an electrical signal.
In particular PIN diodes are widely used as the photodiodes in the
optical receiver for high speed fiber optics communication.
Traditionally package for these devices involve in hermetic seal in
order for them to survive the high temperature, high humidity
environment (HTHH). The requirement of hermetic sealing leads to
complication of the device design and often results in a relatively
high cost of the final product. The requirement hermetic sealing
sometime can also limit the operational performance of the device,
and not permit it to operate at its optimal speed.
[0005] It is highly desirable to assemble the optical receiver
without hermetic sealing, which in turn requires the discrete PIN
device o be able to survive under harsh operating conditions such
as a temperature of 85 degrees Centigrade and 85% humidity level
for more than 1000 hours. The use of a dielectric layer deposited
on the top of the active region of the device substantially reduces
the surface recombination related operating dark, and can increase
the device lifetime as well. However, the separation or
delamination of the dielectric layer away from the active region
dielectric often occurs under HTHH with reverse biased operating
conditions. In case the delamination bridges both anode and
cathode, the dielectric passivation is broken, leading to the
failure of the device.
[0006] Prior to the present invention, there has not been suitable
means for prevention of delamination of the dielectric sealing
layer in a PIN photodiode.
SUMMARY OF THE INVENTION
1. OBJECTS OF THE INVENTION
[0007] It is an object of the present to provide an improved
semiconductor device structure for a PIN photodiode.
[0008] It is another object of the present invention to provide an
improved hermetically sealed PIN photodiode.
[0009] It is also another object of the present invention to
provide a delamination stopper for PIN photodiodes.
[0010] It is also an object of the present invention to provide a
process to provide a delamination stopper for a PIN photodiode and
thereby provide consistent fabrication and reliability of such
devices.
2. FEATURES OF THE INVENTION
[0011] Briefly, and in general terms, the present invention
provides a method of manufacturing a PIN photodiode that reduces
dielectric delamination by forming an first type electrode layer on
a substrate; forming an intrinsic later on the first type electrode
layer; forming a second type electrode layer on the intrinsic
layer; etching the second type electrode layer to define a mesa
shaped structure; and depositing a passivation material over the
mesa shaped structure.
[0012] The present invention also provides a PIN photodiode with a
first type electrode layer disposed on a substrate; an intrinsic
layer, including a first lower region having a first length, and a
second upper region having a second length, smaller than the first
length, disposed over a portion of the first-type cathode layer,
and a second type electrode layer disposed over at least a portion
of the intrinsic layer so as to form a mesa shaped structure. A
passivation or dielectric layer is disposed over the mesa shaped
structure to provide hermetic sealing.
[0013] Another aspect of the present invention is to provide a
method of manufacturing a PIN photodiode by depositing a first type
electrode layer on a substrate; depositing an intrinsic layer on
the first type electrode layer; depositing a second type electrode
layer on the intrinsic layer; etching a trench through the second
type electrode layer, the intrinsic layer, the first type electrode
layer, to define an enclosed region; and depositing a passivation
material in the trench.
[0014] The reduction in dielectric delamination in the PIN diode as
a result of this fabrication process is a substantial improvement
of the PIN diode lifetime, particularly under 85 degrees Centigrade
and 85% humidity conditions. The use of such hermetically sealed
photodiodes in an optical receiver allow such units to operate
under industrial standards for high temperature, high humidity
environments.
[0015] The objects, features, and advantages of this invention will
become apparent upon reading the following specification, when
taken in conjunction with the accompanying drawings. It is intended
that all such additional features and advantages be included
therein with the scope of the present invention, as defined by the
claims.
[0016] The invention can be better understood with reference to the
following drawings. The components in the drawings are not
necessarily to scale, emphasis instead being placed upon clearly
illustrating the principles of the present invention. In the
drawings, like reference numerals designate corresponding parts
throughout the several views.
[0017] FIG. 1A is a cross-sectional view of the lateral PIN
photodiode constructed in accordance with the prior art;
[0018] FIG. 1b is another cross-sectional view of the lateral PIN
photodiode of FIG. 1A;
[0019] FIG. 1c is a top plan view of the lateral PIN photodiode of
FIG. 1a;
[0020] FIG. 2a is a cross-sectional view of a lateral PIN
photodiode constructed in accordance with the present
invention;
[0021] FIG. 2b is another cross-sectional view of the lateral PIN
photodiode of FIG. 2a;
[0022] FIG. 2c is a top plan view of the lateral PIN photodiode of
FIG. 2a;
[0023] FIG. 3a is a cross-sectional view of a lateral PIN
photodiode during the first fabrication step in accordance with the
present invention;
[0024] FIG. 3b is a cross-sectional view of a lateral PIN
photodiode during a subsequent fabrication step in accordance with
the present invention;
[0025] FIG. 3c is a cross-sectional view of a lateral PIN
photodiode during a subsequent fabrication step in accordance with
the present invention;
[0026] FIG. 3d is a cross-sectional view of a lateral PIN
photodiode during a subsequent fabrication step in accordance with
the present invention;
[0027] FIG. 3e is a cross-sectional view of a lateral PIN
photodiode during a subsequent fabrication step in accordance with
the present invention;
[0028] FIG. 3f is a cross-sectional view of a lateral PIN
photodiode during a subsequent fabrication step in accordance with
the present invention;
[0029] FIG. 3g is a cross-sectional view of a lateral PIN
photodiode during a subsequent fabrication step in accordance with
the present invention;
[0030] FIG. 3h is a cross-sectional view of a lateral PIN
photodiode during a subsequent fabrication step in accordance with
the present invention;
[0031] FIG. 3i is a cross-sectional view of a lateral PIN
photodiode during a subsequent fabrication step in accordance with
the present invention;
[0032] FIG. 4 is a cross-sectional view of a vertical PIN
photodiode constructed in accordance with the prior art;
[0033] FIG. 5a is a cross-sectional view of a vertical PIN
photodiode constructed in accordance with the present
invention;
[0034] FIG. 5b is a top plan view of the vertical PIN photodiode of
FIG. 5a.
[0035] The novel features which are considered as characteristics
of the invention are set forth in particular in the appended
claims. The invention itself, however, both as to its construction
and its method of operation, together with additional objects and
advantages thereof, best will be understood from the following
description of specific embodiments when read in connection with
the accompanying drawings.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0036] Details of the present invention will now be described,
including exemplary aspects and embodiments thereof. Referring to
the drawings and the following description, like reference numbers
are used to identify like or functionally similar elements, and are
intended to illustrate major features of exemplary embodiments in a
highly simplified diagrammatic manner. Moreover, the drawings are
not intended to depict every feature of actual embodiments nor the
relative dimensions of the depicted elements, and are not drawn to
scale.
[0037] FIGS. 1a, 1b and 1c depict a lateral PIN diode as known in
the prior art.
[0038] Referring to FIG. 1a, there is shown a fragmentary,
cross-sectional view of a semiconductor structure representing a
lateral PIN photodiode which is depicted with generic first and
second type electrodes. In particular, the photodiode 100 includes
a semi-insulating (SI) substrate 101, and an n-type cathode layer
102 disposed on the substrate. A mesa 103 consisting of an
intrinsic layer 104 is disposed on a portion of the layer 102, and
a p-type anode layer 105 is disposed on the intrinsic layer 104.
The n and p regions 102 and 105 normally are doped to high carrier
concentrations while the intrinsic region 104 typically has a
small, residual n or p type carrier concentration.
[0039] A metal contact 106 is made to the second type electrode,
and a second metal contact 107 is made to the first type electrode.
A dielectric layer 108 is deposited over the active regions of the
device for hermetic sealing.
[0040] FIG. 1b is another cross-sectional view of the lateral PIN
photodiode of FIG. 1a as viewed from a plane ninety degrees from
that of FIG. 1a. Such a view shows a via 109 in the dielectric
layer 108 where the contact 107 makes electrical connection to an
interconnecting trace 110 which extends over the dielectric layer
108 to first electrode bonding pads 111.
[0041] FIG. 1c is a top plan view of the lateral PIN photodiode of
FIG. 1a depicting the planes 1A-1A and 1B-1B from which the
cross-sectional views of FIGS. 1a and 1b respectively are
derived.
[0042] PIN photodiodes such as that shown in FIGS. 1a, 1b and 1c
are negatively biased such that the entire intrinsic region 104 is
depleted and substantially no current flows through the intrinsic
region 104.
[0043] FIGS. 2a, 2b and 2c depict a lateral PIN diode with a
delamination stopper structure according to the present
invention.
[0044] Referring to FIG. 2a, there is shown a fragmentary,
cross-sectional view of a semiconductor structure representing a
lateral PIN photodiode including first and second type electrodes.
In particular, the photodiode 100 includes a semi-insulating (SI)
substrate 101, and an n-type cathode layer 102 disposed on the
substrate. A mesa 103 consisting of a stepped intrinsic layer 104a
and 104b is disposed on a portion of the layer 102, and a p-type
anode layer 105 is disposed over the upper intrinsic layer 104b.
The n and p regions 102 and 105 normally are doped to high carrier
concentrations while the intrinsic region 104 typically has a
small, residual n or p type carrier concentration.
[0045] A metal contact 106 is made to the second type electrode,
and a metal contact 107 is made to the first type electrode. A
dielectric layer 108 is deposited over the active regions of the
device, and in particular over the ledge formed by regions 104a and
104b.
[0046] The horizontal dielectric layer portion 202 prevents the
separation or delamination of the layer 108 from the active
regions. As an illustration, a small gap or delamination 201 is
depicted on the portion of the dielectric layer 202, which is
prevented ??.
[0047] FIG. 2b is another cross-sectional view of the lateral PIN
photodiode as viewed from a plane ninety degrees from that of FIG.
2a. Such view shows a via 109 in the dielectric layer 108 where the
contact 107 makes electrical connection to an interconnecting trace
110 which extends over the dielectric layer 108 to first electrode
bonding pad 111.
[0048] FIG. 2c is a top plan view of the lateral PIN photodiode of
FIG. 2a depicting the planes 2A-2A and 2B-2B from which the cross
sectional views of FIGS. 2a and 2b are derived. More particularly,
the figure depicts the annular delamination stopper region 202 that
lies over the intrinsic layer 104a, showing the delamination 201
being confined in extent.
[0049] Referring next to FIGS. 3a through 3i, there is shown a
progressive sequence of fragmentary, cross-sectional views of a
semiconductor structure during the fabrication of a lateral PIN
photodiode structure.
[0050] FIG. 3f is a cross-sectional view of the lateral PIN
photodiode during a subsequent fabrication step in accordance with
the present invention in which an annular portion of the lower
region 104a has been etched away using the mask layer 302. The
semi-insulating substrate 101 is now shown in this and subsequent
figures.
[0051] FIG. 3g is a cross-sectional view of the lateral PIN
photodiode during a subsequent fabrication step in accordance with
the present invention after the deposition of the annular electrode
106 which contacts the second type electrode 102.
[0052] FIG. 3h is a cross-sectional view of the lateral PIN
photodiode during a subsequent fabrication step in accordance with
the present invention after deposition of a dielectric layer 108
over the entire structure.
[0053] FIG. 3i is a cross-sectional view of the lateral PIN
photodiode after etching a via 109 in the dielectric layer 108 and
deposition of a metal contact layer 110 to make electrical contact
with the annual contact metal layer 107. The view of FIG. 3i
corresponds to that of FIG. 2b above.
[0054] FIG. 4 is a cross-sectional view of a vertical PIN
photodiode 400 constructed in accordance with the prior art. The
electrical characteristics of the device are similar to that of the
device of FIG. 1 in which the semi-insulating substrate 101 has
been replaced by a conductive substrate 401, and the second
electrode contact metal is no longer required to be applied to the
surface of the second electrode layer; but is applied to the bottom
surface 402 of the substrate 401.
[0055] FIG. 5a shows a fragmentary, cross-sectional view of a
semiconductor structure of a vertical PIN photodiode structure
according to the present invention. In particular, the photodiode
500 includes a n.sup.+ conductive substrate 401, an n-contact metal
402 deposited on the lower surface of the substrate 401 for forming
a first contact, and an n-type epitaxial layer 102 deposited on the
upper surface of the substrate 401. An intrinsic layer 104 is then
deposited on the surface of the layer 102, and a p-type anode layer
105 is deposited on the upper surface of the intrinsic layer 104.
An annular p-metal contact 107 is provided on a portion of the
upper surface of the p-type anode layer 405 to make electrical
contact therewith using known lithography and etching techniques. A
trench 403a extending at least partially into the substrate 401 is
then etched around the periphery of the PIN photodiode, as more
particularly shown in the top view of FIG. 5b. A dielectric layer
108 is deposited over the active regions and into the trench 403a.
A via 109 is etched in the dielectric where contact 107 makes
electrical connection to an interconnecting trace 110 to first
electrode bonding pads 111.
[0056] FIG. 5b is a top plan view of the vertical PIN photodiode of
FIG. 5a, depicting the plane 5A-5A from which the cross-sectional
view of FIG. 5a is derived.
[0057] It will be understood that each of the elements described
above, or two or more together, also may find a useful application
in other types of constructions differing from the types described
above.
[0058] While the invention has been illustrated and described as
embodied in a device and method for making PIN photodiode with a
delamination stopper, it is not intended to be limited to the
details shown, since various modifications and structural changes
may be made without departing in any way from the spirit of the
present invention.
[0059] Without further analysis, the foregoing will so fully reveal
the gist of the present invention that others can, by applying
current knowledge, readily adapt it for various applications
without omitting features that, from the standpoint of prior art,
fairly constitute essential characteristics of the generic or
specific aspects of this invention and, therefore, such adaptations
should and are intended to be comprehended within the meaning and
range of equivalence of the following claims.
* * * * *