U.S. patent application number 11/285639 was filed with the patent office on 2006-04-06 for method for fabricating a storage capacitor.
This patent application is currently assigned to Infineon Technologies AG. Invention is credited to Annette Sanger, Dirk Schumann, Bernhard Sell.
Application Number | 20060073659 11/285639 |
Document ID | / |
Family ID | 7675534 |
Filed Date | 2006-04-06 |
United States Patent
Application |
20060073659 |
Kind Code |
A1 |
Sell; Bernhard ; et
al. |
April 6, 2006 |
Method for fabricating a storage capacitor
Abstract
The present invention relates to a novel method for fabricating
a storage capacitor designed as a trench or a stacked capacitor and
is used in particular in a DRAM memory cell. The method includes
steps of forming a lower, metallic capacitor electrode, a storage
dielectric and an upper capacitor electrode. The lower, metallic
capacitor electrode is formed in a self-aligned manner on a silicon
base material in such a way that uncovered silicon regions are
first produced at locations at which the lower capacitor electrode
will be formed, and then metal silicide is selectively formed on
the uncovered silicon regions.
Inventors: |
Sell; Bernhard; (Portland,
OR) ; Sanger; Annette; (Dresden, DE) ;
Schumann; Dirk; (Schonfliess, DE) |
Correspondence
Address: |
LERNER GREENBERG STEMER LLP
P O BOX 2480
HOLLYWOOD
FL
33022-2480
US
|
Assignee: |
Infineon Technologies AG
|
Family ID: |
7675534 |
Appl. No.: |
11/285639 |
Filed: |
November 22, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10650055 |
Aug 26, 2003 |
6998307 |
|
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11285639 |
Nov 22, 2005 |
|
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PCT/DE02/00436 |
Feb 6, 2002 |
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10650055 |
Aug 26, 2003 |
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Current U.S.
Class: |
438/256 ;
257/E21.011; 257/E21.165; 257/E21.274; 257/E21.651; 257/E27.088;
438/399; 438/682 |
Current CPC
Class: |
H01L 21/28518 20130101;
H01L 21/31604 20130101; H01L 27/10861 20130101; H01L 21/02271
20130101; H01L 27/10814 20130101; H01L 28/60 20130101; H01L 21/0217
20130101; H01L 21/02164 20130101 |
Class at
Publication: |
438/256 ;
438/682; 438/399 |
International
Class: |
H01L 21/8242 20060101
H01L021/8242 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 26, 2001 |
DE |
101 09 218.0 |
Claims
1. A method for producing a storage capacitor for an integrated
memory cell, wherein the method comprises the following sequence of
steps: a) providing a semiconductor substrate having uncovered
silicon regions, b) depositing a metal over a surface of the
semiconductor substrate including the uncovered silicon regions, c)
performing a heat treatment step, thereby forming a metal silicide
in a self-aligned manner at an interface surface between the metal
and the silicon regions, d) etching metal deposited in step b)
which in step c) did not react to form metal silicide, selectively
to the metal silicide formed in step c), e) depositing a dielectric
layer on the metal silicide and f) depositing a conductive layer on
the dielectric layer.
2. The method according to claim 1, wherein, between the steps d)
and e), a further heat treatment step is performed, thereby
restructuring the metal silicide.
3. The method according to claim 1, wherein in step a) a
semiconductor substrate is provided which comprises a main surface
in which a trench is etched, wherein the uncovered silicon regions
are trench walls in a lower region of the trench.
4. The method according to claim 1, wherein in step c) the heat
treatment step is performed such that only part of the thickness of
the metal deposited on the silicon regions reacts to form the metal
silicide and wherein another part of metal is removed in step
d).
5. The method according to claim 3, wherein in step a) a
semiconductor substrate is provided which further comprises a
covering material, the covering material at least covering trench
walls in an upper region of the trench.
6. The method according to claim 1, wherein, between the steps a)
and b), a step of doping the uncovered silicon regions is
performed.
7. The method according to claim 6, wherein the uncovered silicon
regions are doped by depositing a doped silicate glass layer
thereon and by effecting out diffusion of dopants from the doped
silicate glass layer by means of an additional heat treatment
step.
8. The method according to claim 5, wherein in step b) the metal is
deposited on the uncovered silicon regions and on the covering
material and wherein metal deposited on the covering material is
maintained during step c) and is removed in step d).
9. The method according to claim 5, wherein the covering material
includes a spacer layer formed of a nitride, preferably of silicon
nitride.
10. The method according to claim 1, wherein in step b) tungsten is
deposited and wherein in step c) tungsten silicide is formed at an
interface surface between tungsten and the silicon regions.
11. The method according to claim 3, wherein in step f) the trench
is filled with a polysilicon filling.
12. The method according to claim 1, wherein a trench capacitor is
formed, the silicon regions being substrate material forming a
first capacitor electrode and the polysilicon filling forming a
second capacitor electrode.
13. The method according to claim 5, wherein the covering material
covering the trench walls in the upper region of the trench is
maintained during steps b) to f) so as to form an isolation collar
of the trench capacitor.
14. The method according to claim 1, wherein the semiconductor
substrate is a silicon-on-insulator-substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional application of application Ser. No.
10/650,055, filed Aug. 26, 2003; which was a continuing
application, under 35 U.S.C. .sctn.120, of International
application PCT/DE02/00436, filed Feb. 6, 2002; the application
also claims the priority, under 35 U.S.C. .sctn.119, of German
patent application DE 101 09 218.0, filed Feb. 26, 2001; the prior
applications are herewith incorporated by reference in their
entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to fabricating a storage
capacitor for use in a DRAM (dynamic random access memory) memory
cell, in which the lower capacitor is designed as a metallic
electrode.
[0004] In dynamic random access memory cell configurations, what
are known as single-transistor memory cells are almost exclusively
used. A single-transistor memory cell includes a read transistor
and a storage capacitor. The information is stored in the storage
capacitor in the form of an electric charge, which represents a
logic 0 or a logic 1. Actuating the read transistor via a word line
allows this information to be read via a bit line. The storage
capacitor must have a minimum capacitance for reliably storing the
charge and, at the same time, for enabling differentiation between
the information item that has been read. The lower limit for the
capacitance of the storage capacitor is currently considered to be
25 fF.
[0005] Since the storage density increases from memory generation
to memory generation, the surface area required by the
single-transistor memory cell must be reduced from generation to
generation. At the same time, the minimum capacitance of the
storage capacitor has to be retained.
[0006] Up to the 1 Mbit generation, both the read transistor and
the storage capacitor have been produced as planar components.
Beyond the 4 Mbit memory generation, the area taken up by the
memory cell was reduced further by using a three-dimensional
configuration of the read transistor and the storage capacitor. One
possibility is to produce the storage capacitor in a trench (See
for example K. Yamada et al., Proc. Intern. Electronic Devices and
Materials IEDM 85, pp. 702 ff.). In this case, a diffusion region
that adjoins the wall of the trench and a doped polysilicon filling
configured in the trench act as electrodes for the storage
capacitor. Therefore, the electrodes of the storage capacitor are
configured along the surface of the trench. In this way, the
effective surface area of the storage capacitor, on which the
capacitance is dependent, is increased with respect to the space
taken up by the storage capacitor on the surface of the substrate.
This effective surface area corresponds to the cross section of the
trench. Reducing the cross section of the trench enables the
packing density to be increased further. However, limits are
imposed on the extent to which the depth of the trench can be
increased, for technological reasons.
[0007] In an alternative capacitor design, the storage capacitor is
formed as a stack on the selection transistor.
[0008] U.S. Pat. No. 5,760,434 discloses a method for fabricating a
DRAM memory cell with a stacked capacitor, in which, after the
selection transistor has been formed and a polysilicon connecting
structure for the active regions of the transistor has been
produced, the resulting surface is planarized, for example using
BPSG, and then contact holes are etched down to the connecting
structures. Then, polysilicon is deposited on the entire surface,
i.e. including outside the contact holes, followed, for example, by
the deposition of tungsten. The formation of silicide is caused by
a subsequent heat treatment step. Then, the unreacted metal is
removed by a selective etching process. The tungsten silicide that
is formed outside the contact holes is subsequently removed by
chemical mechanical polishing.
[0009] U.S. Pat. No. 5,262,343 describes a method for fabricating a
stacked capacitor, in which a polysilicon layer is patterned
photolithographically and, after removing the photoresist material,
a metal such as, for example, platinum, chromium, cobalt or others
is deposited on the polysilicon and is subsequently subjected to a
heat treatment in order to form the metal silicide.
[0010] U.S. Pat. No. 5,905,279 discloses a memory cell having a
storage capacitor configured in a trench and a selection
transistor, in which the storage capacitor has a lower capacitor
electrode that adjoins a wall of the trench, a capacitor
dielectric, and an upper capacitor electrode that includes a
conductive layer, in particular, made from WSi, TiSi, W, Ti or
TiN.
[0011] Published European Patent Application EP 495 991 A1
describes a method for fabricating a ferroelectric memory, in which
the ferroelectric capacitor is designed as a planar capacitor.
According to a preferred embodiment, the lower capacitor electrode
is PtSi or TiSi and is formed only above the contact hole above the
source region.
[0012] A method for the self-aligned formation of titanium silicide
to produce planar structures, such as for example, a gate
electrode, is also known from IEEE Journal Solid-State Circuits,
Vol. SC-20, No. 1, 1985, pages 61 to 69.
[0013] Moreover, it is proposed in the published PCT application WO
01/17014 A1, which is a later publication, to design the lower
capacitor electrode, which is in a memory cell with a selection
transistor and trench capacitor, as a metallic electrode. The
metallic electrode is formed by using a CVD (chemical vapor
deposition) process to deposit tungsten silicide over the entire
surface in the trench which, in the upper region, is lined with a
silicon nitride spacer layer. Then, through the deposition of
photoresist in the trench, the lower part of the trench is provided
with a resist filling, which is used as an etching mask in a
subsequent step for etching the tungsten silicide. Then, the
photoresist filling is removed and the capacitor and then the
memory cell are completed in a known way.
[0014] International publication WO 01/20681, which is likewise a
later publication, describes a method for fabricating a trench
capacitor, in which the lower capacitor electrode is designed in
such a way that it is not only configured in the lower trench
region but also extends along the insulation collar.
SUMMARY OF THE INVENTION
[0015] It is accordingly an object of the invention to provide a
method for fabricating a storage capacitor which overcomes the
above-mentioned disadvantages of the prior art methods of this
general type.
[0016] According to the present invention, the object is achieved
by a method for fabricating a storage capacitor having a vertical
structure with respect to a main surface of a substrate, in
particular for use in a DRAM memory cell. A lower, metallic
capacitor electrode, a storage dielectric and an upper capacitor
electrode are formed in or on the main surface of the substrate.
The lower, metallic capacitor electrode is formed in a self-aligned
manner on a silicon base material in such a manner that, first of
all, uncovered silicon regions are produced at the locations at
which the lower capacitor electrode is to be formed, and then metal
silicide is formed selectively on the uncovered silicon regions.
The step of selectively forming metal silicide on the uncovered
silicon regions includes the step of selectively depositing the
metal silicide on the uncovered silicon regions from the vapor
phase.
[0017] In particular, the object is achieved by a method for
fabricating a memory cell having a storage capacitor designed as a
trench capacitor and a selection transistor. The method includes
the following steps: etching a trench into a main surface of a
semiconductor substrate; carrying out the method described
immediately above, with the storage capacitor configured at least
partially in the trench and the lower, metallic capacitor electrode
adjoining a wall of the trench; and forming the selection
transistor with a source electrode, a drain electrode, a conductive
channel and a gate electrode. The upper capacitor electrode is
connected in an electrically conductive manner to the source or
drain electrode of the selection transistor.
[0018] Furthermore, the object is achieved by a method for
fabricating a memory cell having a storage capacitor designed as a
stacked capacitor and a selection transistor. The method includes
forming a selection transistor with a source electrode, a drain
electrode, a conductive channel and a gate electrode on a main
surface of a semiconductor substrate, and performing the steps
involved in the method described above, so that the lower capacitor
electrode is formed on an electrically conductive connecting
structure made from polysilicon, which connects the lower capacitor
electrode to the source or drain electrode of the selection
transistor, on the resulting surface.
[0019] In this context, a storage capacitor having a vertical
structure with respect to a main surface of a substrate is
essentially a non-planar capacitor, for example, a trench capacitor
or a stacked capacitor. More precisely, a capacitor of this type
has electrodes that do not extend exclusively parallel to the
substrate surface, but rather also has components which are
perpendicular to the substrate surface. In particular, the lower
capacitor electrode has a vertical component. The ratio of the
vertical component to the parallel component is greater than 1.
[0020] Trench capacitors typically have an aspect ratio of depth
(vertical component) to width (parallel component) of between 20:1
and approximately 60:1. Stacked capacitors typically have an aspect
ratio of 5:1 to 20:1.
[0021] The object of the invention is also achieved by a method for
fabricating a trench capacitor, in particular for use in a DRAM
memory cell. The method includes the steps of etching a trench into
a main surface of a silicon substrate, producing uncovered silicon
regions by applying a covering material to the trench regions on
which the lower capacitor electrode should not be formed, and
forming the lower metallic capacitor electrode in a self-aligned
manner by selectively forming metal silicide on the uncovered
silicon regions. The storage capacitor is configured at least
partially in the trench and the lower, metallic capacitor electrode
adjoins a wall of the trench. The method also includes providing a
storage dielectric and an upper capacitor electrode.
[0022] The method for fabricating a storage capacitor is
substantially based on the fact that the lower capacitor electrode
of the storage capacitor is formed in a self-aligned fashion. More
precisely, in the method, the lower capacitor electrode is formed
from a metal silicide selectively on uncovered silicon regions. In
this context, the term "uncovered silicon regions" covers all types
of silicon, in particular, monocrystalline silicon and
polycrystalline silicon (polysilicon), but also, by way of example,
amorphous silicon. According to the present invention, uncovered
silicon regions can be produced in particular as a result of
covering the regions, which are on a silicon base material on which
the lower capacitor electrode should not be formed, with a covering
material, for example, Si.sub.3N.sub.4 or SiO.sub.2 or a
combination of these materials.
[0023] Alternatively, a structured Polysilicon layer can be applied
to a non-silicon base material, for example, by first applying the
polysilicon all over the surface area and subsequently by removing
the layer, for example, by etching or by chemical-mechanical
polishing those parts on which a lower capacitor electrode should
not be formed. The non-silicon base material encompasses all
materials except for silicon, for example, monocrystalline silicon,
polysilicon, and amorphous silicon. The non-silicon base material
itself can quite possibly contain silicon, such as, silicon dioxide
or silicon nitride.
[0024] The following advantages can be derived from the inventive
method: [0025] The self-aligned formation of the metal silicide
layer on uncovered silicon regions is less complicated than the
method described above, in which the metal silicide layer is
applied to the entire surface and is then selectively etched.
Particularly if the covering material used to cover the silicon
regions at which a metal silicide layer is not subsequently to be
produced later acts as an insulation collar of the storage
capacitor or as a diffusion barrier, the self-aligned formation of
the metal silicide layer does not require any additional process
steps for patterning. [0026] In the conventional method, it is
difficult to ensure that the metal silicide layer is removed
selectively in the region of the silicon nitride spacer while being
entirely retained in the lower region of the trench, so that there
is no uncovered silicon in contact with the capacitor dielectric.
In contrast, if metal silicide is formed in a self-aligned form, it
is ensured that all of the uncovered silicon regions are covered by
a layer of the metal silicide. This is very important to minimize
leakage currents, since such currents would flow via uncovered
silicon regions that are in contact with the capacitor dielectric.
If leakage currents are minimized, conversely, the layer thickness
of the capacitor dielectric can be reduced once again, with the
result that the capacitance of the capacitor is increased. [0027]
Since in the conventional method, photoresist fills up the lower
region of the trenches and is then removed, there are problems with
further reducing the feature size. By contrast, the method can be
scaled to smaller sizes without problems. [0028] The method can be
combined with measures for increasing the surface area, such as for
example, the HSG method (roughening of the silicon surface,
hemispherical graining) or mesopore etching. [0029] The electrode
configuration which can be fabricated using the inventive method is
thermally stable and is able to withstand all of the subsequent
steps involved in the DRAM process which is currently used. [0030]
A particular advantage of the inventive method results if, for the
self-aligned formation of the metal silicide, a metal layer is
deposited or a vapor-phase process using a metal-containing vapor
is carried out. This is because in this case forming the metal
silicide only requires one metal-containing precursor and does not
require a silicon-containing precursor. This results in the
advantage that the deposition behavior of only one precursor has to
be taken into account, so that, first, the edge coverage, which is
of critical importance in particular during the deposition on a
structure that is built up vertically, and, second, the
stoichiometric ratio of the resulting layer can be set in the
desired way. Particularly in the case of capacitor trenches with a
high aspect ratio, conventional deposition methods result in the
drawback that the stoichiometric ratio of the metal silicide layer
is dependent on the depth of the trench. This drawback can be
avoided by a deposition method that uses only one precursor.
[0031] According to one embodiment of the present invention, in
which the capacitor is designed as a trench capacitor, to form the
lower, metallic capacitor electrode, first of all, selected regions
of the trench, at which the lower capacitor electrode is not to be
formed, are covered with a covering material, for example, silicon
nitride, silicon dioxide or a combination of these materials.
[0032] It is expedient for a covering material to be applied with a
composition and in a thickness such that it will subsequently act
as an insulating collar of the finished storage capacitor or as a
diffusion barrier. In this case, the fabrication method becomes
particularly simple, since there is no need for any additional
steps for patterning the silicon base material.
[0033] According to another embodiment of the present invention, in
which the capacitor is designed as a stacked capacitor, polysilicon
is applied selectively only at those locations on the surface at
which the lower capacitor electrode is also subsequently to be
fabricated. In this case too, the fabrication method is simplified
by the fact that no additional steps for patterning the silicon
base material are required.
[0034] Then, metal silicide is formed selectively on the uncovered
silicon regions.
[0035] This can be effected, for example, using a method which is
also known as a salicide method (self-aligned silicide). For this
purpose, a metal layer, for example tungsten, titanium, tantalum,
molybdenum, cobalt, nickel, niobium-platinum, palladium or a rare
earth, is deposited. Then, a heat treatment step is carried out,
for example, depending on the metal used, in a nitrogen atmosphere
at a temperature of 600 to 1000.degree. C. During this heat
treatment step, the deposited metal reacts with the silicon below
it to form metal silicide, while the metal that has been deposited
on the covering material does not react. In a subsequent selective
etching step, the unreacted metal is etched away and the metal
silicide remains on the silicon regions.
[0036] According to a preferred embodiment of the present
invention, the heat treatment step can be carried out in such a way
that not all the metal layer is converted into a silicide all the
way through. In this case, the heat treatment step is carried out
at a suitably, low temperature, so that the formation of silicide
proceeds relatively slowly, and the duration of the heat treatment
is set in such a way that the metal layer does not completely form
a silicide all the way through.
[0037] This embodiment has the additional advantage that it is
possible to compensate for an inhomogeneity during the deposition
of metal, since at the locations at which the metal has been
deposited with a relatively great layer thickness, the unconverted
metal is removed during the subsequent step. This measure
advantageously makes it possible to produce very thin metal
electrodes with minimal capacitance losses.
[0038] However, the selective formation of metal silicide may also
take place through the selective deposition of metal silicide.
[0039] By way of example, given accurate setting of parameters, it
is possible to bring about a selective reaction between a
metal-containing gas, for example, WF.sub.6, and the uncovered
silicon using a vapor-phase method with the metal-containing gas.
In this case, the uncovered silicon is etched away slightly at the
surface and, during the deposition method, undergoes a reaction
with the metal-containing gas, resulting in the formation, inter
alia, of a metal silicide layer.
[0040] Alternatively, however, it is also possible for the metal
silicide layer to be formed selectively on the uncovered silicon
regions by a CVD method using a silicon-containing gas, for
example, SiH.sub.4 or SiH.sub.2Cl.sub.2, and a metal-containing
gas, for example, WF.sub.6, TaCl.sub.5 or TiCl.sub.4, under
suitable conditions.
[0041] The methods for the selective deposition of a metal silicide
are advantageous to the extent that there is no need for a
subsequent heat treatment step. However, the deposition conditions,
in particular the pressure and temperature, have to be set very
accurately, and consequently the process window is reduced in size
and it is questionable to what extent these methods can be used in
industrial chip production.
[0042] According to the present invention, the substrate in which
the memory cell is formed may be an ordinary silicon substrate or
an SOI substrate (silicon on insulator or silicon on insulator
substrate). The use of an SOI substrate is advantageous in that the
procedure can be further simplified, since the buried silicon
dioxide layer acts as an etching stop layer. In particular, when
using an SOI substrate, there is no need for a sufficiently thick
(approx. 20 nm) insulating collar to be deposited in the upper
trench region, with the result that, when using a silicon
substrate, the trench opening is greatly narrowed, making the
procedure correspondingly more difficult.
[0043] According to the present invention, the effective capacitor
area and therefore the capacitance of the storage capacitor can be
increased by the fact that, after the step for producing uncovered
silicon regions, measures which increase the surface area are
carried out at these regions. By way of example, it is possible to
etch mesopores, or to perform a method for crystallizing a
previously applied amorphous silicon layer by applying
crystallization nuclei, followed by a heat treatment. Naturally, it
is also possible to carry out any other method that increases the
surface area prior to applying the metal layer or metal silicide
layer.
[0044] Other features which are considered as characteristic for
the invention are set forth in the appended claims.
[0045] Although the invention is illustrated and described herein
as embodied in a method for fabricating a storage capacitor, it is
nevertheless not intended to be limited to the details shown, since
various modifications and structural changes may be made therein
without departing from the spirit of the invention and within the
scope and range of equivalents of the claims.
[0046] The construction and method of operation of the invention,
however, together with additional objects and advantages thereof
will be best understood from the following description of specific
embodiments when read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0047] FIGS. 1-7 are cross-sectional views of a silicon substrate
for illustrating the steps of a first embodiment of the method for
fabricating the lower electrode of a memory cell;
[0048] FIGS. 8-14 are cross-sectional views of a silicon substrate
for illustrating the steps of a second embodiment of the method for
fabricating the lower electrode of a memory cell;
[0049] FIGS. 15-18 are cross-sectional views of a silicon substrate
for illustrating the steps of a third embodiment of the method for
fabricating the lower electrode of a memory cell; and
[0050] FIG. 19 shows the layout in an 8F.sup.2 cell
architecture.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0051] Referring now to the figures of the drawing in detail and
first, particularly, to FIG. 1 thereof, there is shown a silicon
substrate 1 with a main surface 2. A 5 nm thick SiO.sub.2 layer 3
and a 200 nm thick Si.sub.3N.sub.4 layer 4 are applied to the main
surface 2. Then, a 1000 nm thick BSG, layer (not shown) is applied
as hard mask material.
[0052] Using a mask produced by photolithography (not shown), the
BSG layer, the Si.sub.3N.sub.4 layer 4 and the SiO.sub.2 layer 3
are patterned in a plasma etching process using CF.sub.4/CHF.sub.3,
so that a hard mask is formed. After removing the mask produced by
photolithography, trenches 5 are etched into the main surface 1 in
a further plasma etching process using HBr/NF.sub.3 and the hard
mask as an etching mask. Then, the BSG layer is removed by a wet
etch using H.sub.2SO.sub.4/HF.
[0053] The depth of the trenches 5 is, for example, 5 .mu.m, their
width is 100.times.250 nm and they are spaced apart from one
another by 100 nm.
[0054] Next, a 10 nm thick SiO.sub.2 layer 6, which may also be
doped, for example by in-situ doping, is deposited. The deposited
SiO.sub.2 layer 6 covers at least the walls of the trenches 5.
Depositing a 200 nm thick polysilicon layer, chemically
mechanically polishing down to the surface of the Si.sub.3N.sub.4
layer 4, and etching back the polysilicon layer using SF.sub.6
results in the production of a polysilicon filling 7 in each of the
trenches 5. The surface of this polysilicon filling is configured
1000 nm below the main surface 2 (See FIG. 1). If appropriate, the
chemical mechanical polishing can be dispensed with. The
polysilicon filling 7 is used as a sacrificial layer for the
subsequent Si.sub.3N.sub.4 spacer deposition. Next, the SiO.sub.2
layer 6 on the walls of the trenches 5 is etched isotropically.
[0055] Then, a CVD process is used to deposit a 20 nm thick spacer
layer 9 that includes silicon nitride and/or silicon dioxide. This
spacer layer is then etched in an anisotropic plasma etching
process using CHF.sub.3. The spacer layer 9 that has just been
deposited is used as a covering material in the step for
selectively forming metal silicide on uncovered silicon regions. In
the finished memory cell, it is used to switch off the parasitic
transistor that would otherwise form at this location, and
therefore acts as the insulating collar.
[0056] Then, SF.sub.6 is used to etch polysilicon selectively with
respect to Si.sub.3N.sub.4 and SiO.sub.2. In the process, the
polysilicon filling 7 is removed completely from each of the
trenches 5. The part of the SiO.sub.2 layer 6 that has now been
uncovered is removed by etching using NH.sub.4F/HF (See FIG.
2).
[0057] If appropriate to widen the lower regions of the trenches 5,
i.e. in the region remote from the main surface 2, silicon is then
etched selectively with respect to the spacer layer. This is
effected, for example, by an isotropic etching step using ammonia,
in which silicon is etched selectively with respect to
Si.sub.3N.sub.4. The etching time is such that 20 nm of silicon is
etched. In this way, the, cross section is widened by 40 nm in the
lower region of the trenches 5. As a result, the capacitor area and
therefore the capacitance of the capacitor can be increased
further.
[0058] The drawings illustrate the process sequence with unwidened
trenches.
[0059] Then, if this has not already been effected by the doped
oxide, the silicon substrate is doped. This can be achieved, for
example, by depositing an arsenic doped silicate glass layer in a
layer thickness of 50 nm and a TEOS-SiO.sub.2 layer in a thickness
of 20 nm, followed by a heat treatment step at 1000.degree. C., 120
seconds, resulting in the diffusion out of the arsenic-doped
silicate glass layer, and the formation of an n.sup.+-doped region
11 in the silicon substrate 1. Alternatively, it is also possible
to carry out vapor-phase doping, for example, using the following
parameters: 900.degree. C., 399 Pa tributylarsine (TBA) (33 per
cent), 12 min.
[0060] The n.sup.+-doped region reduces the size of the depletion
zone, with the result that the capacitance of the capacitor is
increased further. When a metallic bottom electrode is used, this
doped layer is used to fabricate an ohmic contact between the
substrate and the metal.
[0061] Then, a 10 nm thick tungsten layer 12 is deposited over the
entire surface, for example using a CVD method (See FIG. 3).
[0062] In a subsequent heat treatment step at 600 to 800.degree. C.
in a nitrogen atmosphere (N.sub.2-RTP, rapid thermal annealing),
the self-aligned tungsten silicide is formed. More specifically,
tungsten silicide 13 is formed only at the locations at which the
tungsten has been deposited directly on the silicon, while the
metal which has been deposited directly on the nitride does not
react with the substrate. This is illustrated in FIG. 4. In this
step, a slight widening of the capacitor trenches results from the
fact that, for the formation of tungsten silicide, silicon is
consumed at the walls of the trenches.
[0063] According to a preferred embodiment, this heat treatment
step can be set in such a way that not all of the tungsten forms a
silicide all the way through. Consequently, as described above, it
is possible to produce particularly thin metal electrodes. In
addition, it is possible to compensate for inhomogeneities in the
layer thickness of the metal.
[0064] Finally, the tungsten is etched selectively with respect to
the tungsten silicide. This can be achieved, for example, by wet
etching in H.sub.2O/NH.sub.4OH/H.sub.2O.sub.2 (See FIG. 5).
[0065] This step does not attack the part of the tungsten layer
which was deposited on the uncovered silicon and which reacted
therewith during the heat treatment step to form tungsten silicide,
while the part of the tungsten layer which was deposited on the
silicon nitride or silicon dioxide and also, if appropriate, the
unreacted part of the tungsten layer deposited on the silicon is
removed. Accordingly, after this selective etching step, what
remains is a self-aligned tungsten silicide layer which covers the
previously uncovered silicon regions. This ensures that, after the
subsequent deposition of the dielectric, there are no uncovered
silicon regions in direct contact with the dielectric, with the
result that the leakage currents are minimized.
[0066] Naturally, the methods which have been described in more
detail above can also be used as alternative methods for the
self-aligned formation of metal silicide.
[0067] If appropriate, a second heat treatment step at 960.degree.
C. in a nitrogen atmosphre can then be carried out thereafter
(N.sub.2-RTP (rapid thermal annealing)). This step leads to
restructuring of the WSi.sub.x which is formed, and free tungsten
and silicon bonds are saturated by nitrogen.
[0068] Then a 5 nm thick dielectric layer 14, which contains
SiO.sub.2 and Si.sub.3N.sub.4 and also, if appropriate, silicon
oxynitride, is deposited as a capacitor dielectric. This layer
sequence can be produced by steps for depositing nitride and for
thermal oxidation, during which defects in the layer below are
annealed. Alternatively, the dielectric layer 14 contains
Al.sub.2O.sub.3 (aluminum oxide), TiO.sub.2 (titanium dioxide),
Ta.sub.2O.sub.5 (tantalum oxide). Then, a 200 nm thick in-situ
doped polysilicon layer 15 is deposited, as shown in FIG. 6.
Chemical mechanical polishing removes the polysilicon layer 15 down
to the surface of the Si.sub.3N.sub.4 layer 4.
[0069] Then, the standard DRAM process is carried out, by means of
which the upper capacitor electrode is suitably patterned and is
connected to the source/drain region of a selection transistor.
[0070] This can be achieved, for example, by etching the
polysilicon filling 15 to approximately 100 nm below the main
surface 2. Then an Si.sub.3N.sub.4 etch is performed using
HF/ethylene glycol, in which 10 nm of Si.sub.3N.sub.4 is etched,
and an etch using NH.sub.4F/HF is performed, by which SiO.sub.2 and
dielectric material are etched. After sacrificial oxidation to form
a screen oxide (not shown), an implantation step is carried out, in
which an n.sup.+-doped region 16 is formed in the side wall of each
trench 5 in the region of the main surface 2. As shown in FIG. 7,
space which has remained clear above the polysilicon filling 15 in
the respective trench 5 is filled with a polysilicon filling 10 by
deposition of in-situ doped polysilicon and back-etching of the
polysilicon using SF.sub.6. In the finished storage capacitor, the
polysilicon filling 15 acts as an upper capacitor electrode. The
polysilicon filling 10 acts as a connection structure between the
n.sup.+-doped region 16 and the polysilicon filling 15, which acts
as an upper capacitor electrode.
[0071] Next, insulating structures 8 are produced, which surround
the active regions and thereby define these regions. For this
purpose, a mask is formed, which defines the active regions (not
shown). The insulating structures 8 are completed by
non-selectively plasma etching silicon, silicon nitride, SiO.sub.2
and polysilicon using CHF.sub.3/N.sub.2/NF.sub.3. The etching time
is set in such a way that 200 nm of polysilicon is etched by
removing the resist mask by an O.sub.2/N.sub.2 by wet-chemical
etching of 3 mm of the dielectric layer, by oxidation and the
deposition of a 5 nm thick Si.sub.3N.sub.4 layer and by the
deposition of a 250 nm thick SiO.sub.2 layer in a TEOS process and
by a subsequent chemical mechanical polishing. Then, the
Si.sub.3N.sub.4 layer 4 is removed by etching in hot
H.sub.3PO.sub.4 and the SiO.sub.2 layer 3 is removed by etching in
dilute hydrofluoric acid.
[0072] Next, a screen oxide is formed by sacrificial oxidation.
This step uses implantation stages and masks produced by
photolithography in order to form n-doped wells, p-doped wells and
to carry out threshold voltage implantations in the regions of the
periphery and of the selection transistors of the cell array.
Furthermore a high-energy ion implantation is carried, out in order
to dope the substrate region that is remote from the main surface
2. In this way, an n.sup.+-doped region, which connects adjacent
lower capacitor electrodes 13 to one another, is formed (known as a
buried-well implant).
[0073] Next the transistor is completed using generally known
method steps, by in each case defining the gate oxide and the gate
electrodes 18, corresponding interconnects and the source and drain
electrode 17.
[0074] Then, the memory cell is completed in a known way by the
formation of further wiring planes.
[0075] The memory cell configuration, the layout of which is
illustrated by way of example for an 8-F.sup.2 cell architecture in
FIG. 19, has, for each memory cell, a storage capacitor configured
in one of the trenches 5 and a planar selection transistor. Each
memory cell takes up 8F.sup.2, where F is the minimum feature size
in the corresponding technology. The bit lines BL run in strip form
and run parallel to one another.
[0076] The width of the bit line BL in each case amounts to F and
the distance between the bit lines likewise amounts to F. The word
lines WL, which likewise have a width of F and are spaced apart by
F, run perpendicular to this direction. Beneath the bit lines BL
there are active regions A. Two word lines WL cross above each
active region. The active regions A are in each case configured
offset with respect to one another beneath adjacent bit lines BL.
In the center of the active regions A there is a bit line contact
ELK that allows an electrical connection between the respective bit
line EL and the active region A. The trenches 5 are configured
beneath the word line WL. The gate electrode 26 of the associated
selection transistor is in each case configured within the active
regions at the intersection point between one of the bit lines BL
and one of the word lines WL.
[0077] The active regions A in each case extend between two
trenches 5. They include two selection transistors that are
connected to the associated bit line BL via a common bit line
contact BLK. Depending on which of the word lines WL is actuated,
the information item is read from the storage capacitor that is
configured in one or other of the trenches 5.
[0078] According to a further exemplary embodiment, as illustrated
in FIG. 8, an SOI substrate 41, i.e. a silicon substrate with a
buried SiO.sub.2 layer 46, is used. An SiO.sub.2 layer 43 in a
thickness of 5 nm and, an Si.sub.3N.sub.4 layer 44 in a thickness
of 200 nm are applied to a main surface 42 of the SOI substrate 41.
Above this, a BSG layer (not shown) is deposited in a thickness of
1000 nm, then an Si.sub.3N.sub.4 layer (not shown) in a thickness
of 200 nm and a polysilicon layer (not shown) in a thickness of 350
nm, in each case is deposited as a hard mask material. The
polysilicon layer, the silicon nitride layer, the BSG layer and the
nitride layer are etched by plasma etching using CHF.sub.3/O.sub.2
and a mask (not shown) that is patterned by photolithography and
defines the configuration of the storage capacitors. Then, the
active Si layer 47 is etched by plasma etching using HBr/NF.sub.3
and the buried oxide layer 46 is etched by plasma etching using
CHF.sub.3/O.sub.2. The parameters of this etching step are such
that the trenches are only etched as far as the lower end of the
buried oxide layer 46.
[0079] After removing the BSG hard mask, a 5 nm thick
Si.sub.3N.sub.4 layer 49 is deposited as spacer material. Since in
this embodiment the parasitic transistor is avoided by the buried
SiO.sub.2 layer, the Si.sub.3N.sub.4 layer in this case is not used
to disconnect this parasitic transistor. Rather, its role is to
prevent the diffusion of dopants during a subsequent step for
doping the substrate by doping from the vapor phase or from the
doped SiO.sub.2 layer in the upper capacitor region (active region
47). To achieve this, a thickness of 5 nm is sufficient. Then, the
capacitor trenches 45 are etched down to a depth of 5 .mu.m by
plasma etching using HEr/NF.sub.3, as illustrated in FIG. 9.
[0080] The etching of the capacitor trenches may in this case take
place in such a manner that the lower regions of the trenches 45
are widened, i.e. in the region that is remote from the main
surface 42. By way of example, the cross section of the lower
region of the trenches 45 can be widened by about 40 nm. In this
way, the capacitor area and therefore the capacitance of the
capacitor can be increased further.
[0081] The drawings illustrate the process sequence with unwidened
trenches.
[0082] Afterwards, the silicon substrate is doped. This can be
achieved, for example, by depositing an arsenic-doped silicate
glass layer in a layer thickness of 50 nm and a TEOS-SiO.sub.2
layer in a thickness of 20 nm, followed by a heat treatment step at
1000.degree. C, 120 seconds, with the result that an n.sup.+-doped
region 58 is formed in the silicon substrate 41 by diffusion out of
the arsenic-doped silicate glass layer. Alternatively, it is also
possible to carry out vapor phase doping, for example with the
following parameters: 900.degree. C., 399 Pa tributylarsine (TBA)
(33 percent), 12 min.
[0083] The n.sup.+-doped region 58 reduces the size of the
depletion zone, with the result that the capacitance of the
capacitor is increased further. When using a metallic bottom
electrode, this doped layer is used to produce an ohmic contact
between substrate and metal.
[0084] Next, a 10 nm thick tungsten layer 50 is deposited over the
entire surface, for example using a CVD method (See FIG. 10). The
self-aligned tungsten silicide is formed in a subsequent heat
treatment step at 600 to 800.degree. C. in a nitrogen atmosphere
(N.sub.2-RTP, rapid thermal annealing). More specifically, tungsten
silicide 48 forms only at the locations at which the tungsten has
been deposited directly on the silicon, while the metal which has
been deposited directly on the nitride does not react with the
substrate. This is illustrated in FIG. 11. A slight widening of the
capacitor trenches results in this step from the fact that silicon
is consumed at the walls of the trenches for the formation of
tungsten silicide.
[0085] According to a preferred embodiment, this heat treatment
step can be set in such a way that not all the tungsten forms a
silicide all the way through. Consequently, as described above, it
is possible to produce particularly thin metal electrodes. In
addition, it is possible to compensate for inhomogeneities in the
layer thickness of the metal.
[0086] Finally, the tungsten is etched selectively with respect to
the tungsten silicide 48, This can be achieved, for example, by wet
etching in H.sub.2O/NH.sub.4OH/H.sub.2O.sub.2 (See FIG. 12).
[0087] This step does not attack the part of the tungsten layer
which had been deposited on the uncovered silicon and reacted
therewith to form tungsten silicide during the heat treatment step,
while the part of the tungsten layer which has been deposited on
the silicon nitride or silicon dioxide and, if appropriate, the
unreacted part of the tungsten layer deposited on the silicon is
removed. Accordingly, what remains after this selective etching
step is a self-aligned tungsten silicide layer that covers the
previously uncovered silicon regions.
[0088] If appropriate, a second heat treatment step can then be
carried out at 960.degree. C. in a nitrogen atmosphere
(N.sub.2-RTP, rapid thermal annealing). This step restructures the
WSi.sub.x formed and causes free tungsten and silicon bonds to be
saturated by nitrogen.
[0089] Next, a 5 nm thick dielectric layer 51, which contains
SiO.sub.2 and Si.sub.3N.sub.4 and also, if appropriate, silicon
oxynitride, is deposited as a capacitor dielectric. Alternatively,
the dielectric layer 51 contains Al.sub.2O.sub.3 (aluminum oxide),
TiO.sub.2 (titanium dioxide), Ta.sub.2O.sub.5 (tantalum oxide).
Then, a 200 nm thick in-situ doped polysilicon layer 52 is
deposited, as shown in FIG. 13. The polysilicon layer 52 is removed
down to the surface of the Si.sub.3N.sub.4 layer 44 by chemical
mechanical polishing.
[0090] Then, the standard DRAM process is carried out to suitably
pattern the upper capacitor electrode and connect it to the source
or drain electrode 56 of a selection transistor.
[0091] This can be achieved, for example, by etching the
polysilicon filling 52 to approximately 100 nm below the main
surface 42. There follows, an Si.sub.3N.sub.4 etch using
HF/ethylene glycol, during which 10 nm of Si3N4 is etched, and an
etch using NH.sub.4F/HF, which is used to etch SiO.sub.2 and
dielectric material. After a sacrificial oxidation step to form a
screen oxide (not shown), an implantation is carried out, in which
an n.sup.+-doped region 53 is formed in the side wall of each
trench 45 near the main surface 42. As shown in FIG. 14, space in
the respective trench 45, which remains clear above the polysilicon
filling 52, is filled with a polysilicon filling 54 by the
deposition of in-situ doped polysilicon and etching back the
polysilicon using SF.sub.6.
[0092] In the finished storage capacitor, the polysilicon filling
52 acts as an upper capacitor electrode. The polysilicon filling 54
acts as a connection structure between the n.sup.+-doped region 53
and the polysilicon filling 52 that acts as the upper capacitor
electrode.
[0093] Then, insulation structures 55 are produced, which surround
the active regions and thereby define these regions. For this
purpose, a mask which defines the active regions (not shown) is
formed. The insulation structures 55 are completed by non-selective
plasma etching of silicon, silicon nitride, SiO.sub.2 and
polysilicon using CHF.sub.3/N.sub.2/NF.sub.3. The etching time is
set in such a way that 200 nm of polysilicon is etched by removing
the resist mask used in this etching using O.sub.2/N.sub.2, by
wet-chemical etching of 3 nm of the dielectric layer, by oxidation
and the deposition of a 5 nm thick Si.sub.3N.sub.4 layer, and by
the deposition of a 250 nm thick SiO.sub.2 layer using a TEOS
process and a subsequent chemical mechanical polishing. Then, the
Si.sub.3N.sub.4 layer 44 is removed by etching in hot
H.sub.3PO.sub.4 and the SiO.sub.2 layer 43 is removed by etching in
dilute hydrofluoric acid.
[0094] Next, a screen oxide is formed by sacrificial oxidation.
Implantations and masks that are produced by photolithography are
used to form n-doped wells, p-doped wells and to carry out
threshold voltage implantations in the region of the periphery and
the selection transistors of the cell array. Furthermore, a
high-energy ion implantation is carried out in order to dope the
substrate region that is remote from the main surface 42. In this
way, an n.sup.+-doped region that connects adjacent lower capacitor
electrodes 48 to one another is formed.
[0095] Next, the transistor is completed using generally known
method steps involving defining in each case the gate oxide and the
gate electrodes 57, corresponding interconnects, and the source and
drain electrode 56.
[0096] Then, the memory cell is completed in a known way by forming
further wiring planes.
[0097] According to the present invention, the method for
fabricating the lower capacitor electrode can also be applied to a
stacked capacitor of a DRAM memory cell. Unlike the fabrication
methods described above, in this case the lower capacitor electrode
is not formed ,in a trench formed in a silicon material, but rather
on the surface of a polysilicon contact structure which connects
the source/drain region of the selection transistor to the lower
capacitor electrode.
[0098] According to the third embodiment of the present invention,
structures are produced on a silicon substrate in accordance with
the standard DRAM process for stacked capacitors. More
specifically, first of all, as illustrated in FIG. 15, generally
known methods are used to define the active regions in a main
surface 62 of a silicon substrate 61, as a result of insulating
structures 63 being formed by etching isolation trenches and
filling the isolation trenches with a thin Si.sub.3N.sub.4 layer
and SiO.sub.2. Then, to fabricate the word lines, first of all a
thin SiO.sub.2 layer is produced as gate oxide by thermal
oxidation, then, to fabricate the gate electrodes 65, a polysilicon
layer, a tungsten silicide layer and 200 to 300 nm of
Si.sub.3N.sub.4 are deposited over the entire surface and are
suitably patterned. Next, thermal oxidation is used to apply an
SiO.sub.2 layer and, moreover, a nitride deposition method is used
to apply an Si.sub.3N.sub.4 layer as a spacer layer, and these
layers are then patterned, so that the lateral flanks of the gate
electrodes 65 are covered with these layers.
[0099] In accordance with what is known as the folded-bit line
architecture, the middle word line illustrated in FIG. 15 serves as
what is known as a passing word line, i.e. as a word line for the
gate electrode of the memory cell located in front of or behind the
plane of the drawing.
[0100] Next, the source and drain electrodes 64 are formed in a
self-aligned manner by ion implantation using the gate electrodes
65 as implantation masks.
[0101] Then, the spaces between the word lines are filled by the
deposition of BSG or BPSG and a subsequent heat treatment, during
which the BSG 72 or BPSG flows. A TEOS method is used to apply
SiO.sub.2 (not shown) to the resulting surface. Contact holes are
etched through the SiO.sub.2 and the BSG 72, selectively with
respect to Si.sub.3N.sub.4, down to the source/drain region at the
locations at which the contact structures 66 between lower
capacitor electrode 67 and source or drain electrode 64 of the
selection transistor are to be formed.
[0102] Then, an in-situ doped polysilicon layer 66 is applied in a
thickness which is such that the lower part of the contact holes,
which extend between adjacent word lines, is completely filled with
polysilicon, while the upper part of the contact holes, which
extend through the SiO.sub.2 layer, is lined with a thin film of
polysilicon, i.e. hollow cylinders or cups are formed at this
location. The polysilicon that has been deposited on the SiO.sub.2
surface is removed by chemical mechanical polishing, and then the
SiO.sub.2 is etched away at the surface. The result is the
structure shown in FIG. 15.
[0103] Then, by way of example, a CVD method is used to deposit a
thin layer of tungsten over the entire surface.
[0104] The self-aligned tungsten silicide 67 is formed in a
subsequent heat treatment step at 600 to 800.degree. C. in a
nitrogen atmosphere (N.sub.2-RTP, rapid thermal annealing). More
specifically, tungsten silicide is formed only at the locations at
which the tungsten has been deposited directly on the silicon,
while the metal which has been deposited directly on the nitride or
the spaces filled with SSG does not react with the substrate.
[0105] According to a preferred embodiment, this heat treatment
step can be set in such a way that not all the tungsten forms a
silicide all the way through. This makes it possible, as described
above, to produce particularly thin metal electrodes.
[0106] Finally, the tungsten is etched selectively with respect to
tungsten silicide. This can be achieved, for example, by wet
etching in H.sub.2O/NH.sub.4OH/H.sub.2O.sub.2 (See FIG. 16).
[0107] This step does not attack the part of the tungsten layer
which had been deposited on the uncovered silicon and reacted
therewith to form tungsten silicide during the heat treatment step,
while the part of the tungsten layer which has been deposited on
the silicon nitride or BSG, and, if appropriate, the unreacted part
of the tungsten layer deposited on the silicon is removed.
Accordingly what remains after this etching step is a self-aligned
tungsten silicide layer 67 which covers the silicon regions
previously applied selectively.
[0108] If appropriate, a second heat treatment step can then be
carried out at approximately 800.degree. C. in a nitrogen
atmosphere (N.sub.2-RTP, rapid thermal annealing). This step
restructures the WSi.sub.x formed and causes free tungsten and
silicon bonds to be saturated by nitrogen.
[0109] Next, a 5 nm thick dielectric layer 68, which contains
SiO.sub.2 and Si.sub.3N.sub.4 and also, if appropriate, silicon
oxynitride, is deposited as capacitor dielectric. Alternatively,
the dielectric layer 68 contains Al.sub.2O.sub.3 (aluminium oxide),
TiO.sub.2 (titanium dioxide), Ta.sub.2O.sub.5 (tantalum oxide).
Then, a tungsten silicide layer is deposited as upper capacitor
electrode 69, as shown in FIG. 17. The thickness of the tungsten
silicide layer may be such that the cup which has been lined with
the lower capacitor electrode and dielectric is completely filled,
i.e. the thickness of the deposited layer is approximately 50 to
100 nm.
[0110] After patterning the dielectric layer and the upper
capacitor electrode using known methods, further insulating layers
are produced, bit line contacts 70 are fabricated and then the bit
lines 71 are defined.
[0111] The method described in accordance with the third embodiment
is advantageous over the conventional method for forming stacked
capacitors in that the connecting structure made from polysilicon
is suitably patterned prior to the deposition of the metal, so that
uncovered silicon regions are present only at the locations at
which the lower capacitor electrode is to be formed. Accordingly,
metal silicide is only formed or deposited at these locations, so
that it is no longer necessary for any metal silicide to be removed
during the subsequent steps. As a result, the method for
fabricating the lower capacitor electrode can be simplified
considerably.
* * * * *