U.S. patent application number 11/262278 was filed with the patent office on 2006-03-09 for processing methods of forming an electrically conductive plug to a node location.
Invention is credited to Alan R. Reinberg.
Application Number | 20060049526 11/262278 |
Document ID | / |
Family ID | 25199235 |
Filed Date | 2006-03-09 |
United States Patent
Application |
20060049526 |
Kind Code |
A1 |
Reinberg; Alan R. |
March 9, 2006 |
Processing methods of forming an electrically conductive plug to a
node location
Abstract
Methods of forming electrical connections with an integrated
circuitry substrate node location are described. According to one
aspect of the invention, a substrate node location is laterally
surrounded with insulating material and left outwardly exposed.
Conductive material is deposited over the exposed node location.
Subsequently, a photomaskless etch of the conductive material is
conducted to a degree sufficient to leave a plug of conductive
material over the node location. In a preferred implementation, the
insulating material with which such node location is surrounded
constitutes insulating material portions which are provided
relative to conductive lines which are formed over the substrate.
In another preferred implementation, such conductive lines form a
grid of insulating material which, in turn, defines the node
location. According to a preferred aspect of the invention, a
plurality of insulated conductive lines are formed over a
substrate. At least some of the conductive lines constitute word
lines and at least some of the conductive lines constitute bit
lines. The lines are preferably formed to define and laterally
surround an active area substrate location. The substrate location
is preferably surrounded by at least four of the lines. Conductive
material is deposited over the substrate and the conductive lines
and in electrical contact with the node location. The conductive
material is then removed to a degree sufficient to form an isolated
plug of conductive material over the node location and between the
four conductive lines.
Inventors: |
Reinberg; Alan R.; (Boise,
ID) |
Correspondence
Address: |
WELLS ST. JOHN P.S.
601 W. FIRST AVENUE, SUITE 1300
SPOKANE
WA
99201
US
|
Family ID: |
25199235 |
Appl. No.: |
11/262278 |
Filed: |
October 28, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10884584 |
Jul 1, 2004 |
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11262278 |
Oct 28, 2005 |
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10382801 |
Mar 5, 2003 |
6777289 |
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10884584 |
Jul 1, 2004 |
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09251219 |
Feb 16, 1999 |
6551876 |
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10382801 |
Mar 5, 2003 |
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08808603 |
Feb 28, 1997 |
5872048 |
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09251219 |
Feb 16, 1999 |
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Current U.S.
Class: |
257/758 ;
257/202; 257/208; 257/211; 257/760; 257/E21.507; 257/E21.59;
257/E21.649; 257/E21.658 |
Current CPC
Class: |
H01L 27/10888 20130101;
H01L 21/76877 20130101; H01L 27/10855 20130101; H01L 21/76897
20130101; H01L 21/76838 20130101; H01L 21/76895 20130101 |
Class at
Publication: |
257/758 ;
257/211; 257/208; 257/202; 257/760 |
International
Class: |
H01L 23/52 20060101
H01L023/52 |
Claims
1-29. (canceled)
30. A semiconductive structure comprising: a conductive node within
a substrate; a plurality of conductive lines over the substrate and
establishing a lateral boundary around an entirety of the
conductive node; and masking material over the plurality of the
conductive lines and the conductive node, a conductive portion of
at least one of the plurality of the conductive lines being exposed
through the masking material, the conductive portion being adjacent
the conductive node.
31. The structure of claim 30 wherein the plurality of the
conductive lines comprises at least three conductive lines
establishing the lateral boundary.
32. The structure of claim 30 wherein the plurality of the
conductive lines comprises at least four conductive lines
establishing the lateral boundary.
33. The structure of claim 30 wherein the plurality of the
conductive lines comprises only four conductive lines establishing
the lateral boundary.
34. The structure of claim 30 wherein the conductive node comprises
a diffusion region within the substrate.
35. The structure of claim 30 wherein at least a portion of the
substrate comprises semiconductive material, and wherein the
conductive node is located within the semiconductive material of
the substrate.
36. The structure of claim 30 wherein at least a portion of the
substrate comprises semiconductive material, and wherein the
conductive node comprises a diffusion region within the
semiconductive material of the substrate.
37. The structure of claim 30 wherein only one of the plurality of
the conductive lines comprises the exposed conductive portion.
38. The structure of claim 30 wherein the exposed conductive
portion is through an opening extending through an electrically
insulative spacer.
39. The structure of claim 38 wherein the spacer comprises nitride
material.
40. The structure of claim 38 wherein the spacer comprises oxide
material.
41. A semiconductive structure comprising: a plurality of
conductive lines over a substrate and comprising a lateral boundary
around an entirety of a portion of the substrate; a conductive node
within the portion of the substrate; and masking material over the
plurality of the conductive lines and the conductive node, an
opening extending through the masking material to a conductive
portion of at least one of the plurality of the conductive lines,
the conductive portion being adjacent the conductive node.
42. The structure of claim 41 wherein the opening extends through
the masking material to the conductive node.
43. The structure of claim 41 wherein the opening extends through
the masking material to the conductive node, and further comprising
at least a portion of the opening being filled with conductive
material, the conductive material contacting the conductive node
and the conductive portion of the at least one of the plurality of
the conductive lines.
44. The structure of claim 43 wherein the plurality of the
conductive lines comprises respective uppermost surfaces, and
wherein the conductive material comprises an uppermost surface
elevationally below the respective uppermost surfaces of the
plurality of the conductive lines.
45. The structure of claim 43 wherein the conductive material
comprises polysilicon.
46. The structure of claim 43 wherein the conductive material
comprises tungsten.
47. The structure of claim 41 wherein the opening extends
substantially vertically from over the substrate, and wherein a
substantial portion of the opening has a horizontal cross section
comprising a rectangle.
48. The structure of claim 41 wherein the opening extends to the
conductive portion of only one of the plurality of the conductive
lines.
49. The structure of claim 41 wherein the plurality of the
conductive lines comprises a first pair of spaced conductive lines
and a second pair of spaced conductive lines, the first pair
comprising bit lines and the second pair comprising word lines.
Description
TECHNICAL FIELD
[0001] This invention concerns processing methods of forming an
electrically conductive plug to a node location. This invention
also concerns methods of forming an electrical connection with an
integrated circuit memory cell node location.
BACKGROUND OF THE INVENTION
[0002] Fabrication of integrated circuitry typically involves
forming electrical connections to substrate node locations. In the
context of integrated circuit memory devices, such as dynamic
random access memory devices, such electrical connections include
those which are made to and between storage capacitors and
substrate diffusion regions.
[0003] In the past, there have been at least two ways to make such
electrical connections. A first way of forming such electrical
connections involves depositing a thick insulator material, such as
borophosphosilicate glass, over the substrate and then conducting a
self-aligned etch thereof to form a contact opening. The contact
opening, or at least a portion thereof, is subsequently filled with
conductive material. As aspect ratios of such contact openings
increase, it becomes more challenging to form such openings and
electrical connections. A second way of forming such electrical.
connections involves depositing a conductive material over the
entire substrate, patterning and etching such material to define
desired electrical connections, and subsequently forming an
insulating dielectric layer over the substrate. Contact openings
can then be etched through the dielectric layer. Again, challenges
are posed with respect to etching the contact openings through the
dielectric layer.
[0004] This invention grew out of concerns associated with
improving the manner in which electrical connections are made to or
with integrated circuit substrate node locations. This invention
also grew out of concerns associated with improving the manner in
which electrical connections are made with integrated circuit
memory cell node locations.
SUMMARY OF THE INVENTION
[0005] Methods of forming electrical connections with an integrated
circuit substrate node location are described. According to one
aspect of the invention, a substrate node location is laterally
surrounded with insulating material and left outwardly exposed.
Conductive material is deposited over the exposed node location.
Subsequently, a photomaskless etch of the conductive material is
conducted to a degree sufficient to leave a plug of conductive
material over the node location. In a preferred implementation, the
insulating material with which such node location is surrounded
constitutes insulating material portions which are provided
relative to conductive lines which are formed over the substrate.
In another preferred implementation, such conductive lines form a
grid of insulating material which, in turn, defines the node
location. According to a preferred aspect of the invention, a
plurality of insulated conductive lines are formed over a
substrate. At least some of the conductive lines constitute word
lines and at least some of the conductive lines constitute bit
lines. The lines are preferably formed to define and laterally
surround an active area substrate location. The substrate location
is preferably surrounded by at least four of the lines. Conductive
material is deposited over the substrate and the conductive lines
and in electrical contact with the node location. The conductive
material is then removed to a degree sufficient to form an isolated
plug of conductive material over the node location and between the
four conductive lines.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Preferred embodiments of the invention are described below
with reference to the following accompanying drawings.
[0007] FIG. 1 is a top plan view of a semiconductor wafer fragment
at one processing step in accordance with the invention.
[0008] FIG. 2 is a view of the FIG. 1 wafer fragment taken along
line 2-2 in FIG. 1.
[0009] FIG. 3 is a view of the FIG. 1 wafer fragment taken along
line 3-3 in FIG. 1.
[0010] FIG. 4 is a view of a portion of the FIG. 1 wafer fragment
at a processing step subsequent to that shown by FIG. 1.
[0011] FIG. 5 is a view of the FIG. 4 wafer fragment taken along
line 5-5 in FIG. 4.
[0012] FIG. 6 is a view of the FIG. 4 wafer fragment at a
processing step subsequent to that shown by FIG. 4.
[0013] FIG. 7 is a view of a portion of the FIG. 6 wafer fragment
taken along line 7-7 in FIG. 6.
[0014] FIG. 8 is a view of the FIG. 7 wafer fragment at a
processing step subsequent to that shown by FIG. 7.
[0015] FIG. 9 is a view of the FIG. 7 wafer fragment at a
processing step subsequent to that shown by FIG. 8.
[0016] FIG. 10 is a view of the FIG. 7 wafer fragment at a
processing step subsequent to that shown by FIG. 9.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0017] This disclosure of the invention is submitted in furtherance
of the constitutional purposes of the U.S. Patent Laws "to promote
the progress of science and useful arts" (Article 1, Section
8).
[0018] Referring to FIG. 1, a semiconductor wafer fragment is shown
generally at 10 and comprises a semiconductive substrate 12. In the
context of this document, the term "semiconductive substrate" is
defined to mean any construction comprising semiconductive
material, including, but not limited to bulk semiconductive
materials such as a semiconductive wafer (either alone or in
assemblies comprising other materials thereon), and semiconductive
material layers (either alone or in assemblies comprising other
materials). The term "substrate" refers to any supporting
structure, including, but not limited to, the semiconductive
substrates described above. In the preferred embodiment, substrate
12 comprises an integrated circuit memory array area and a
peripheral area. For purposes of the discussion herein, only a
portion of the memory array area is shown.
[0019] A plurality of isolation oxide runners 14 are formed within
substrate 12. One method of forming such runners is by trench and
refill techniques in which substrate portions are etched away and
back-filled with isolation oxide. Subsequent planarization provides
the illustrated isolation oxide runners. Respective pairs of
runners such as pairs 16 define continuous active areas or regions
therebetween, such as respective active areas or regions 18. Active
areas or regions 18 constitute continuous active areas which are
formed within or relative if to substrate 12. A plurality of
laterally spaced apart insulative conductive lines 20, 22, 24, and
26, at least some of which are word lines, are formed over
substrate 12 and disposed generally transverse individual isolation
oxide runners 14. The illustrated conductive lines are formed, in
the preferred embodiment, to have respective insulative or
insulating sidewall spacers (shown in FIG. 2 but not specifically
designated) and insulative or insulating caps (shown in FIG. 2 but
not specifically designated).
[0020] Conductive lines 20, 22, 24, and 26 constitute a first
series of conductive lines which are formed relative to substrate
12. In the illustrated and preferred embodiment, substrate 12
supports integrated circuitry which forms memory cells. Even more
preferably, such memory cells constitute dynamic random access
memory cells. Accordingly, word line pair 22, 24 share an
intervening contact of adjacent pairs. of memory cells, which in
turn share a diffusion region (described below) in substrate 12.
Electrical isolation between the adjacent pairs of memory cells is
provided by intervening conductive isolation lines 20, 26 which are
formed in conjunction with the formation of word lines 22, 24.
Lines 20, 26 in operation are connected with ground or a suitable
negative voltage and effectively substitute for the electrical
isolation formerly provided by field oxide.
[0021] Referring to FIGS. 1-3, conductive lines 20, 22, 24, and 26
have respective conductive line tops 21, 23, 25, and 27. Such line
tops are defined by the insulating or insulative caps mentioned
above. A plurality of laterally spaced apart insulated conductive
memory cell bit lines 28, 30, and 32 are formed elevationally
outwardly of conductive lines 20, 22, 24, and 26 and their
respective conductive line tops, and are disposed generally
transverse relative to the word lines. For purposes of illustration
and clarity, the bit lines are indicated in FIG. 1 as a second
series of parallel lines at least portions of which are disposed
elevationally over the first series lines 20, 22, 24, and 26. In
the illustrated and preferred embodiment, individual bit lines are
formed elevationally over respective individual isolation oxide
runners 14 as best shown in FIG. 2 for bit line 28 in corresponding
extent and shape.
[0022] As formed, the first and second series of conductive lines
collectively constitute a plurality of upstanding devices, with
individual conductive word/isolation lines and bit lines
constituting a grid of insulated lines which are formed relative to
substrate 12.
[0023] Referring to FIGS. 1 and 3, a plurality of node locations
34, 36, and 38 with which electrical connection is desired are
defined by the grid of upstanding devices and between conductive
line pairs 20, 22, and 22, 24, and 24, 26 which are formed
elevationally outwardly thereof. Although only three node locations
are shown for purposes of illustration, other node locations are
formed over the array area defined by substrate 12. In the
illustrated and preferred embodiment, node locations 34, 36, and 38
constitute respective diffusion regions 40, 42, and 44 which are
outwardly exposed. As formed, node locations 34, 36, and 38 also
constitute first substrate locations which are laterally surrounded
with insulating material. In the illustrated example, such
insulating material constitutes insulative portions of first series
conductive lines 20, 22, 24, and 26, and second series conductive
bit lines 28, 30, and 32 which are formed elevationally outwardly
of and generally transverse relative to conductive lines 20, 22,
24, and 26. In the illustrated and preferred embodiment, the
conductive word/isolation and bit lines are formed to define an
adjacent active area substrate location (corresponding to
respective node locations 34, 36, and 38) which is laterally
surrounded by four of the insulated conductive lines. In this
example, two of such lines constitute first series lines, and two
of such lines constitute second series lines.
[0024] In the illustrated example, a mask can and preferably is
utilized to define and expose a plurality of areas 37 (FIG. 1)
proximate respective bit lines 28, 30, and 32. Areas 37 constitute
areas which laterally expose respective sidewall spacers over the
diagrammatically illustrated bit lines 28, 30, and 32. Typically,
such sidewall spacers are formed from an oxide or nitride material.
In a preferred embodiment, the sidewall spacers of conductive lines
20, 22, 24, and 26 comprise a nitride material while those of bit
lines 28, 30, and 32 comprise an oxide material. The exposed
sidewall portions 37 of bit lines 28, 30, and 32 are etched in a
wet etch comprising HF at a substantially higher rate than the
nitride material sidewalls of conductive lines 20, 22, 24, and 26.
Accordingly, such enables contact to be made relative to the bit
lines without appreciably etching any inadvertently exposed
sidewall material of conductive lines 20, 22, 24, and 26.
[0025] Referring to FIGS. 4 and 5, a fragmentary portion of the
FIG. 1 substrate is shown. After node locations 34, 36, and 38 are
surrounded with the preferred insulating material and with the bit
line conductive sidewall portions being effectively exposed,
conductive material 46 is formed or deposited over the grid and the
exposed node locations. Exemplary materials for conductive material
46 are polysilicon, tungsten, and the like. Preferably, such
conductive material is chemical vapor deposited to achieve a degree
of conformal coverage. Accordingly, conductive material 46 is
deposited over the conductive lines and in electrical connection
with the respective node locations as shown in FIG. 5. Conductive
material 46 is also preferably in contact with the exposed portions
of the bit line sidewalls corresponding to areas 37 (FIG. 1),
thereby forming an electrical connection with node location 36,
which, in turn, will form a connection through a word line/gate
with a storage node location described below. In the preferred
embodiment, a desired amount of conductive material can be less
than the height of adjacent conductive lines, but an amount which
is sufficient to fill the spaces between the lines.
[0026] Referring to FIGS. 6 and 7, conductive material 46 is
removed to a degree sufficient to form isolated plugs 48, 50, and
52 of conductive material (FIG. 6) respectively, over node
locations 34, 36, and 38. Plug 52 is shown in its cross-sectional
entirety in FIG. 7. In the illustrated and preferred embodiment, a
photomaskless etch is conducted of conductive material 46 (FIG. 5)
to a degree which is sufficient to remove the conductive material
from elevationally outward of the insulating material constituting
portions of the conductive lines, and to a degree which is
sufficient to leave plugs 48, 50, and 52 over respective node
locations 34, 36, and 38. Accordingly, the photomaskless etch
constitutes an etch which is conducted in the absence of any
photomasking material laterally proximate the node location. Even
more preferably, such etch is conducted in the absence of any
photomasking material over the substrate. The photomaskless etch
desirably permits conductive material to be removed from outside or
outwardly of the illustrated array area without the need for a mask
in or over the array area. The preferred etching of conductive
material 46 constitutes an isotropic etch of the material to a
degree sufficient to completely remove conductive material from
over the conductive word/isolation lines, and to expose the
insulating material portions of lines 24, 26. Exemplary etches
include wet or dry etches, with the latter being preferred.
Further, exemplary dry etch chemistries can include one or more of
the following: CF.sub.4, SF.sub.6, or NF.sub.3. Accordingly, the
conductive material constituting plug 52 is preferably recessed to
elevationally below uppermost surfaces or line tops 25, 27.
[0027] Referring to FIG. 8, a layer 54 is formed over substrate 12.
Preferably, layer 54 comprises an insulating or insulative material
such as borophosphosilicate glass which is formed over the
substrate. An exemplary thickness for layer 54 is 0.5 .mu.m to 1.5
.mu.m.
[0028] Referring to FIG. 9, an opening 56 is etched or otherwise
formed through insulative layer 54 to outwardly expose conductive
material of plug 52 overlying node location 38. Preferably such
opening is anisotropically etched to outwardly expose plug 52.
[0029] Referring to FIG. 10, a second, spaced apart substrate
location 58 is formed elevationally outward of and in electrical
contact with the first substrate location defined by node location
38. In the illustrated and preferred embodiment, the spaced apart
first and second substrate locations constitute part of an
integrated circuitry memory cell and substrate location 58
constitutes a storage capacitor having a storage node 60, a
dielectric layer 62, and cell plate 64. In the illustrated example,
at least a portion of the storage capacitor is disposed
elevationally outwardly, above or over the previously formed bit
lines 28, 30, and 32 (FIG. 1). Accordingly, such constitutes a
capacitor-over-bit-line dynamic random access memory cell. Other
integrated circuit first and second substrate locations are
possible, including ones which are not necessarily associated with
the above described integrated circuit memory cells.
[0030] In compliance with the statute, the invention has been
described in language more or less specific as to structural and
methodical features. It is to be understood, however, that the
invention is not limited to the specific features shown and
described, since the means herein disclosed comprise preferred
forms of putting the invention into effect. The invention is,
therefore, claimed in any of its forms or modifications within the
proper scope of the appended claims appropriately interpreted in
accordance with the doctrine of equivalents.
* * * * *