U.S. patent application number 11/263629 was filed with the patent office on 2006-03-09 for forming ferroelectric polymer memories.
Invention is credited to Ebrahim Andideh, Mark Isenberger, Michael Leeson, Mani Rahnama.
Application Number | 20060048376 11/263629 |
Document ID | / |
Family ID | 29583227 |
Filed Date | 2006-03-09 |
United States Patent
Application |
20060048376 |
Kind Code |
A1 |
Andideh; Ebrahim ; et
al. |
March 9, 2006 |
Forming ferroelectric polymer memories
Abstract
In accordance with some embodiments, a ferroelectric polymer
memory may be formed of a plurality of stacked layers. Each layer
may be separated from the ensuing layer by a polyimide layer. The
polyimide layer may provide reduced layer-to-layer coupling, and
may improve planarization after the lower layer fabrication.
Inventors: |
Andideh; Ebrahim; (Portland,
OR) ; Isenberger; Mark; (Corrales, NM) ;
Leeson; Michael; (Portland, OR) ; Rahnama; Mani;
(Beaverton, OR) |
Correspondence
Address: |
TROP PRUNER & HU, PC
8554 KATY FREEWAY
SUITE 100
HOUSTON
TX
77024
US
|
Family ID: |
29583227 |
Appl. No.: |
11/263629 |
Filed: |
October 31, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10160641 |
May 31, 2002 |
|
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11263629 |
Oct 31, 2005 |
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Current U.S.
Class: |
29/604 ;
257/E21.311; 257/E27.104; 29/847; 427/123 |
Current CPC
Class: |
B82Y 10/00 20130101;
Y10T 29/49156 20150115; H01L 21/32136 20130101; Y10T 29/49069
20150115; H01L 27/11502 20130101 |
Class at
Publication: |
029/604 ;
029/847; 427/123 |
International
Class: |
H01F 41/02 20060101
H01F041/02; B05D 5/12 20060101 B05D005/12 |
Claims
1. A method comprising: coating a first metal layer with
hexamethyldisilazane; forming a layer of polymer over said coating,
said polymer to act as a ferroelectric polymer in a ferroelectric
polymer memory; and plasma etching a second metal layer formed over
said polymer using a gas mixture including helium, said metal
layers and polymer layer to form a first layer of ferroelectric
polymer memory.
2. The method of claim 1 including forming a polyimide layer over
said first layer of ferroelectric polymer memory.
3. The method of claim 2 including forming a second layer of a
ferroelectric polymer memory and forming another polyimide layer
over said second memory layer.
4. The method of claim 1 wherein forming a layer of polymer over
said coating includes forming a copolymer layer including
vinyledene fluoride and trifloroethylene over said coating.
5. The method of claim 4 including spin coating the copolymer in an
organic solvent.
6. The method of claim 5 including evaporating the organic solvent
using heat.
7. The method of claim 1 wherein plasma etching a second metal
layer includes etching said metal layer with a selectivity greater
then 1.25.
8. The method of claim 1 wherein plasma etching a second metal
layer includes etching said metal layer with a selectivity greater
than 2.
9. The method of claim 1 wherein plasma etching a second metal
layer includes using a radio frequency bias from about 20 to about
30 Watts.
10. The method of claim 1 wherein plasma etching a second metal
layer includes using a gas mixture including Cl.sub.2 and
BCL.sub.3.
11. A method comprising: forming a ferroelectric polymer over a
first metal layer, said first metal layer patterned to form metal
bitlines, said ferroelectric polymer to extend over said bitlines
and downward between said bitlines toward an underlying substrate;
and forming a second metal layer over said ferroelectric polymer
layer, said second metal layer to be patterned to form row lines
that extend transverse to said bitlines.
12. The method of claim 11 wherein forming a ferroelectric polymer
over a first metal layer includes forming a ferroelectric copolymer
of vinyledene fluoride and trifluoroethylene over said first metal
layer.
13. The method of claim 11 further including before forming said
ferroelectric polymer, coating said bitlines with
hexamethyldisilazane.
14. The method of claim 13 further including using a solution
including diethylcarbonate to coat said bitlines.
15. The method of claim 13 further including annealing to form a
piezoelectric film.
16. The method of claim 11 wherein said first and second metal
layers and said ferroelectric polymer form a first layer of a
ferroelectric polymer memory.
17. The method of claim 16 further including forming a polyimide
layer over said metal row lines.
18. The method of claim 17 further including forming a second layer
of ferroelectric polymer memory over said polyimide layer, said
second layer of ferroelectric polymer memory including a
ferroelectric polymer formed over metal bitlines and metal row
lines formed over said ferroelectric polymer.
19. The method of claim 18 including forming another polyimide
layer over said second layer of ferroelectric polymer memory.
20. A method comprising: forming a layer of a polymer over a first
metal layer coated with hexamethyldisilazane, said polymer to
enable data storage in a ferroelectric polymer memory; plasma
etching a second metal layer formed over said polymer, said plasma
etching using a gas mixture including helium; and after said
etching, forming a polyimide layer over said second metal
layer.
21. The method of claim 21 including forming a plurality of
bitlines over a semiconductor structure.
22. The method of claim 21 wherein plasma etching includes etching
a plurality of row lines extending generally transverse to said
bitlines.
23. The method of claim 20 including etching said second metal
layer with a selectivity greater than 2.
24. The method of claim 20 wherein plasma etching includes plasma
etching using a radio frequency bias of from about 20 Watts to
about 30 Watts.
25. The method of claim 20 wherein plasma etching includes plasma
etching using a gas mixture including Cl.sub.2 and BCL.sub.3.
26. The method of claim 20 wherein forming a layer of a polymer
includes forming a copolymer including vinyledene fluoride and
trifluroethylene.
27. The method of claim 20 wherein said polymer and said first and
second metal layers form a first layer of a ferroelectric polymer
memory, and including forming a second layer of ferroelectric
polymer memory over said polyimide layer, the polymer layer of the
second layer of ferroelectric polymer memory formed; over a metal
layer, and a hexamethyldisilazane layer between said polymer layer
and said metal layer of said second layer of ferroelectric polymer
memory.
Description
[0001] This is a continuation of U.S. patent application Ser. No.
10/160,641, filed on May 31, 2002.
BACKGROUND
[0002] This invention relates generally to ferroelectric polymer
memories.
[0003] A ferroelectric polymer memory may be used to store data.
Data may be stored in layers within the memory. The higher the
number of layers, the higher is the capacity of the memory. Each of
the polymer layers include polymer chains with dipole moments. Data
may be stored by changing the polarization of the polymer between
metal lines. No transistors are needed for storage.
[0004] As a result, ferroelectric polymer memories are non-volatile
memories with relatively fast read and write speeds. For example,
microsecond initial reads may be possible with write speeds
comparable to those of flash memories.
[0005] Generally, in polymer memories, the same material is used
for the interlayer dielectric between the various polymer layers
and for passivation layers. This results in a relatively thick film
to avoid ferroelectric coupling. Moreover, the presence of fluorine
in these materials introduces outgasing and degrades reliability.
Another approach is to use photoresist, but this material is not
stable for long-term operation of devices and it is a reliability
liability.
[0006] Thus, there is a need for better ways to separate the layers
in multiple layer, stacked polymer memories.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is an enlarged cross-sectional view of one embodiment
of the present invention;
[0008] FIG. 2 is an enlarged cross-sectional view of the embodiment
as shown in FIG. 1 after further processing in one embodiment of
the present invention;
[0009] FIG. 3 is an enlarged cross-sectional view of the embodiment
shown in FIG. 2 after further processing in one embodiment of the
present invention;
[0010] FIG. 4 is an enlarged perspective view of one embodiment of
the present invention prior to patterning the row lines 16;
[0011] FIG. 5 is an enlarged perspective view after patterning the
row lines in accordance with one embodiment of the present
invention;
[0012] FIG. 6 is an enlarged cross-sectional view of another
embodiment of the present invention; and
[0013] FIG. 7 is an enlarged cross-sectional view of the embodiment
shown in FIG. 6 after additional processing.
DETAILED DESCRIPTION
[0014] Referring to FIG. 1, a first layer 20 of a multi-layer
ferroelectric polymer memory includes a semiconductor substrate 10.
A plurality of metal bitlines 12 run into the page. A polymer layer
14 may overlap the metal bitlines 12, extending over the bitlines
12 and down to the substrate 12 at locations between proximate
metal bitlines 12. Finally, over the polymer layer 14 is a
plurality of metal row lines 16 (only one of which is shown in FIG.
1) that extend transversely to the bitlines 12. Thus, the
polarization of the polymer layer 14 may be changed using the
overlying row lines 16 and the underlying bitlines 12 to store data
in the polymer layer 14 at the intersections of row lines 16 and
bitlines 12.
[0015] The polymer layer 14 may be formed of a copolymer of
vinyledene fluoride (VDF) and trifluoroethylene (TFE) in one
embodiment of the present invention. Before coating the wafer with
the layer 14, the wafer may be treated with hexamethyldisilazane
(HMDS) in a vapor prime oven on a conventional photoresist spin
track as indicated in FIG. 6. In one embodiment, the oven may be
100 degrees Celsius. Then the wafer may be spin coated with the
VDF/TFE copolymer in diethylcarbonate (DEC) and heated to evaporate
the DEC.
[0016] The HMDS vapor, indicated at V in FIG. 6, may be dispensed
with a nitrogen gas purge for sixty seconds in one embodiment, to
form the coating 26. The wafer may be cooled to room temperature
and then coated with the copolymer/DEC solution. The wafer may be
annealed to form a piezoelectric film, in some embodiments, that
acts as the polymer layer 14 as shown in FIG. 7. The HMDS treatment
may provide a consistent, dry, contamination-free substrate on
which to spin coat the VDF/TFE copolymer.
[0017] The layer 20 may be replicated a number of times to produce
a stack of memory layers 20 that are capable of increasing the
amount of data stored by the polymer memory. To this end, as shown
in FIG. 2, a polyimide layer 18 may be formed over the metal row
lines 16.
[0018] The polyimide layer 18 is a very low dielectric constant
material that reduces the layer-to-layer coupling between different
polymer memory layers 20. It also improves planarization after
fabrication of a lower layer 20. The thickness of the polyimide
layer 18 may be optimized for planarity and electrical isolation.
Because polyimide can be formed at low temperatures, it may be
integrated into the memory fabrication process without an excessive
thermal burden.
[0019] Referring to FIG. 3, over the layer 20, a second layer 22
may be formed. The layer 22 may be formed on top of the polyimide
layer 18 and may include metal bitlines 12a, a polymer layer 14a,
and metal row lines 16a. A second polyimide layer 18a may be formed
over the layer 22 to facilitate the stacking of still subsequent
memory layers (not shown). If no subsequent layers are to be
provided, the layer 18a acts as a passivation layer.
[0020] Referring to FIG. 4, a layer 16 may be deposited for
subsequent patterning to form the row lines 16. In accordance with
one embodiment of the present invention, a gas mixture may be
utilized to etch metal on polymer with improved etch sensitivity
and good uniformity. In one embodiment, helium may be included in
an etching gas mixture made up of chlorine gas (Cl.sub.2) and
BCL.sub.3.
[0021] As a result of the etching, the structure shown in FIG. 5,
with the defined row lines 16, is created with good sensitivity to
the underlying polymer layer 14. In some embodiments, the metal to
polymer etch selectivity is above 1:1.
[0022] Conventional metal patterning on polymer uses gas mixtures
of BCL.sub.3 and Cl.sub.2 at high radio frequency bias power to
produce an anisotropic metal profile. By lowering the radio
frequency bias the extent of bombardment may be reduced. For
example, radio frequency bias power may be less than 50 Watts and
advantageously from about 20 to about 30 Watts in some embodiments.
In addition, helium gas may be added to improve the metal etch
uniformity and to reduce heavy bombardment on the wafer.
[0023] In some embodiments, a radio frequency plasma etcher having
a magnetron current of 200 milliamps, and a radio frequency bias of
25 Watts. A BCL.sub.3 gas flow rate at 35 standard cubic
centimeters per minute (sccm), Cl.sub.2 gas flow rate at 35 sccm,
and helium flow rate at 100 sccm may be used. The aluminum etch
rate is then 159.6 nm. per minute with a ferroelectric polymer etch
rate of 57.2 nm. per minute resulting in a selectivity of 2.8. In
general, selectivity greater than 1.25 is advantageous and
selectivity greater than 2 may be particularly advantageous in some
embodiments.
[0024] While the present invention has been described with respect
to a limited number of embodiments, those skilled in the art will
appreciate numerous modifications and variations therefrom. It is
intended that the appended claims cover all such modifications and
variations as fall within the true spirit and scope of this present
invention.
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