U.S. patent application number 11/206002 was filed with the patent office on 2006-02-02 for magnetic memory device using soi substrate and method of manufacturing the same.
Invention is credited to Yoshiaki Asao.
Application Number | 20060023498 11/206002 |
Document ID | / |
Family ID | 19156173 |
Filed Date | 2006-02-02 |
United States Patent
Application |
20060023498 |
Kind Code |
A1 |
Asao; Yoshiaki |
February 2, 2006 |
Magnetic memory device using SOI substrate and method of
manufacturing the same
Abstract
A magnetic memory device includes an SOI substrate having a
first semiconductor layer, a first insulating film formed on the
first semiconductor layer, and a second semiconductor layer formed
on the first insulating film, an element isolation insulating film
formed selectively in the second semiconductor layer extending from
a surface of the second semiconductor layer with a depth reaching
the first insulating film, a switching element formed in the second
semiconductor layer, a magneto-resistive element connected to the
switching element, a first wiring extending in a first direction at
a distance below the magneto-resistive element, and a second wiring
formed on the magneto-resistive element and extending in a second
direction different from the first direction.
Inventors: |
Asao; Yoshiaki;
(Yokohama-shi, JP) |
Correspondence
Address: |
OBLON, SPIVAK, MCCLELLAND, MAIER & NEUSTADT, P.C.
1940 DUKE STREET
ALEXANDRIA
VA
22314
US
|
Family ID: |
19156173 |
Appl. No.: |
11/206002 |
Filed: |
August 18, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10288366 |
Nov 6, 2002 |
6946712 |
|
|
11206002 |
Aug 18, 2005 |
|
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Current U.S.
Class: |
365/171 ;
257/E31.122 |
Current CPC
Class: |
H01L 31/02164 20130101;
H01L 31/18 20130101 |
Class at
Publication: |
365/171 |
International
Class: |
G11C 11/14 20060101
G11C011/14 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 7, 2001 |
JP |
2001-342289 |
Claims
1-10. (canceled)
11. A magnetic memory device comprising: an SOI substrate having a
first semiconductor layer, a first insulating film formed on the
first semiconductor layer, and a second semiconductor layer formed
on the first insulating film; an element isolation insulating film
formed selectively in the second semiconductor layer and extending
from a surface of the second semiconductor layer with a depth
reaching the first insulating film; a diode formed in the second
semiconductor layer; a magneto-resistive element connected to the
switching element; a first wiring extending in a first direction at
a distance below the magneto-resistive element; and a second wiring
formed on the magneto-resistive element and extending in a second
direction different from the first direction, wherein the diode
comprises: a gate electrode formed on the second semiconductor
layer with a gate insulating film interposed; a first diffusion
layer of a first conductivity type that is formed in a portion of
the second semiconductor layer, which is located near one end of
the gate electrode, the first diffusion layer being connected to
the magneto-resistive element; and a second diffusion layer of a
second conductivity type that is formed in a portion of the second
semiconductor layer, which is located near the other end of the
gate electrode, wherein a potential to be applied to the gate
electrode is variable.
12. A magnetic memory device comprising: an SOI substrate having a
first semiconductor layer a first insulating film formed on the
first semiconductor layer, and a second semiconductor layer formed
on the first insulating film; an element isolation insulating film
formed selectively in the second semiconductor layer and extending
from a surface of the second semiconductor layer with a depth
reaching the first insulating film; a diode formed in the second
semiconductor layer; a magneto-resistive element connected to the
switching element; a first wiring extending in a first direction at
a distance below the magneto-resistive element; and a second wiring
formed on the magneto-resistive element and extending in a second
direction different from the first direction, wherein the diode
comprises: a gate electrode formed on the second semiconductor
layer with a gate insulating film interposed; a first diffusion
layer of a first conductivity type that is formed in a portion of
the second semiconductor layer, which is located near one end of
the gate electrode, the first diffusion layer being connected to
the magneto-resistive element; and a second diffusion layer of a
second conductivity type that is formed in a portion of the second
semiconductor layer, which is located near the other end of the
gate electrode, wherein the second diffusion layer is provided
spaced apart from the first diffusion layer. wherein the second
semiconductor layer lying between the first diffusion layer and the
second diffusion layer is a third diffusion layer of the first
conductivity type or the second conductivity type, wherein a
negative voltage is applied to the gate electrode in a case where
the third diffusion layer is of a P type, and a positive voltage is
applied to the gate electrode in a case where the third diffusion
layer is of an N type.
13. A magnetic memory device comprising: an SOI substrate having a
first semiconductor layer a first insulating film formed on the
first semiconductor layer, and a second semiconductor layer formed
on the first insulating film; an element isolation insulating film
formed selectively in the second semiconductor layer and extending
from a surface of the second semiconductor layer with a depth
reaching the first insulating film; a switching element formed in
the second semiconductor layer; a magneto-resistive element
connected to the switching element; a first wiring extending in a
first direction at a distance below the magneto-resistive element;
and a second wiring formed on the magneto-resistive element and
extending in a second direction different from the first direction
further comprising a peripheral circuit region formed using a bulk
substrate, located at a periphery of a memory cell array region
including the magneto-resistive element and the switching element,
and having a peripheral circuit controlling the switching
element.
14. A magnetic memory device according to claim 13, wherein a
surface of the bulk substrate is substantially on a level with a
surface of the first semiconductor layer.
15. A magnetic memory device according to claim 13, further
comprising: an epitaxial growth layer formed on the bulk substrate,
the epitaxial growth layer having a surface that is on a level with
a surface of the second semiconductor layer; and a second
insulating film formed between the epitaxial growth layer and the
second semiconductor layer.
16. A magnetic memory device comprising: an SOI substrate having a
first semiconductor layer, a first insulating film formed on the
first semiconductor layer, and a second semiconductor layer formed
on the first insulating film; an element isolation insulating film
formed selectively in the second semiconductor layer extending from
a surface of the second semiconductor layer with a depth reaching
the first insulating film; a first switching element formed in the
SOI substrate and having one end and the other end; a second
switching element formed in the SOI substrate and having one end
and the other end; a first wiring connected to said one end of the
first switching element; a second wiring connected to said one end
of the second switching element; a third wiring connected to said
other end of the first switching element and said other end of the
second switching element; and a magneto-resistive element connected
to the third wiring.
17. A magnetic memory device according to claim 16, wherein a
direction of magnetization of the magneto-resistive element is
inclined 45.degree. with respect to a direction of extension of the
third wiring.
18. A magnetic memory device according to claim 16, wherein a gate
electrode of the first switching element is a word line for data
write and data read-out.
19. A magnetic memory device according to claim 16, wherein a gate
electrode of the second switching element is a word line for data
write.
20. A magnetic memory device according to claim 16, further
comprising a third switching element connected to the
magneto-resistive element.
21. A magnetic memory device according to claim 20, wherein a gate
electrode of the third switching element is a word line for data
read-out.
22. A magnetic memory device according to claim 16, wherein the
magneto-resistive element is connected to a ground.
23. A magnetic memory device according to claim 16, wherein each of
the first and second switching elements is a transistor or a
diode.
24. A magnetic memory device according to claim 20, wherein the
third switching element is a transistor or a diode.
25. A magnetic memory device according to claim 16, wherein when
data is written in the magneto-resistive element, the first and
second switching elements are turned on to let a current flow
between the first and second wirings.
26. A magnetic memory device according to claim 25, further
comprising a third switching element connected to the
magneto-resistive element, wherein the third switching element is
turned off when the data is written.
27. A magnetic memory device according to claim 16, wherein when
data is read out from the magneto-resistive element, the first
switching element is turned on and the second switching element is
turned off to let a current flow from the first wiring to the
magneto-resistive element.
28. A magnetic memory device according to claim 27, further
comprising a third switching element connected to the
magneto-resistive element, wherein the third switching element is
turned on when the data is read out.
29-48. (canceled)
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional application of U.S. Ser.
No. 10/288,366 filed Nov. 6, 2002, which is based upon and claims
the benefit of priority from the prior Japanese Patent Application
No. 2001-342289, filed Nov. 7, 2001, the entire contents of which
are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates generally to a magnetic memory
device and a method of manufacturing the memory device. This
invention relates more particularly to a magnetic random access
memory (MRAM) wherein a memory cell is formed using a magnetic
tunnel junction (MTJ) element that stores information "1" or "0" on
the basis of a tunnel magneto-resistive (TMR) effect.
[0004] 2. Description of the Related Art
[0005] In these years, many kinds of memories that store
information based on new principles have been proposed. One of them
is a magnetic random access memory (MRAM) using a tunneling
magneto-resistive (TMR) effect. The MRAM is disclosed, for example,
in ISSCC2000 Technical Digest, p. 128, Roy Scheuerlein et al., "A
10 ns Read and Write Non-Volatile Memory Array Using a Magnetic
Tunnel Junction and FET Switch in each Cell."
[0006] FIGS. 15A, 15B and 15C are cross-sectional views of a
magnetic tunnel junction (MTJ) element of a prior-art magnetic
memory device. The MTJ element used as a memory element of the MRAM
will now be described.
[0007] As is shown in FIG. 15A, an MTJ element 31 has such a
structure that an insulating layer (tunnel junction layer) 42 is
interposed between two magnetic layers (ferromagnetic layers) 41
and 43. In the MRAM, the MTJ element 31 stores information "1" or
"0". The information "1" or "0" is determined, depending on whether
the directions of magnetization of the two magnetic layers 41 and
43 in the MTJ element 31 are parallel or anti-parallel. The term
"parallel" in this context means that the directions of
magnetization of two magnetic layers 41 and 43 are the same, and
"anti-parallel" means that the directions of magnetization of two
magnetic layers 41 and 43 are opposite to each other.
[0008] Specifically, when the directions of magnetization of two
magnetic layers 41 and 43 are parallel, as shown in FIG. 15B, the
tunnel resistance of the insulating layer 42 interposed between the
two magnetic layers 41 and 43 takes a minimum value. This state
corresponds to, for example, "1". On-the other hand, when the
directions of magnetization of two magnetic layers 41 and 43 are
anti-parallel, as shown in FIG. 15C, the tunnel resistance of the
insulating layer 42 interposed between the two magnetic layers 41
and 43 takes a maximum value. This state corresponds to, for
example, "0".
[0009] Normally, an anti-ferromagnetic layer 103 is provided on one
of the two magnetic layers 41 and 43. The anti-ferromagnetic layer
103 is a member for fixing the direction of magnetization of one
magnetic layer 41, thus permitting easy rewriting of information by
merely changing the direction of magnetization of the other
magnetic layer 43 alone.
[0010] FIG. 16 shows MTJ elements arranged in a matrix in a
prior-art magnetic memory device. FIG. 17 shows asteroid curves in
the prior-art magnetic memory device. FIG. 18 shows MTJ curves in
the prior-art magnetic memory device. The principle of the write
operation for the MTJ element will now be described in brief.
[0011] As is shown in FIG. 16, MTJ elements 31 are arranged at
intersections between write word lines 28 and bit lines (data
select lines) 32, which are arranged to cross each other. A data
write operation is performed by supplying a current to each of the
write word lines 28 and bit lines 32 and setting the directions of
magnetization of the MTJ elements 31 in a parallel state or an
anti-parallel state, making use of magnetic fields produced by the
current flowing in both lines 28 and 32.
[0012] For example, in the data write mode, the bit lines 32 are
supplied with only a current I1 that flows in one direction, and
the write word lines 28 are supplied with a current I2 that flows
in one direction or a current I3 that flows in the other direction
in accordance with data to be written. When the write word line 28
is supplied with the current I2 that flows in the one direction,
the direction of magnetization of the MTJ element 31 is parallel
("1" state). On the other hand, when the write word line 28 is
supplied with the current I3 that flows in the other direction, the
direction of magnetization of the MTJ element 31 is anti-parallel
("0" state).
[0013] How the direction of magnetization of the MTJ element 31 is
changed will now be described. When a current is supplied to a
selected write word line 28, a magnetic field Hx occurs in a
longitudinal direction, i.e. an Easy-Axis direction, of the MTJ
element 31. When a current is supplied to a selected bit line 32, a
magnetic field Hy occurs in a transverse direction, i.e. a
Hard-Axis direction, of the MTJ element 31. As a result, a
composite magnetic field of the Easy-Axis magnetic field Hx and
Hard-Axis magnetic field Hy acts on the MTJ element 31 located at
the intersection of the selected write word line 28 and selected
bit line 32.
[0014] In a case where the magnitude of the composite magnetic
field of the Easy-Axis magnetic field Hx and Hard-Axis magnetic
field Hy is in an outside region (hatched region) of asteroid
curves indicated by solid lines in FIG. 17, the direction of
magnetization of the magnetic layer 43 can be reversed. On the
other hand, when the magnitude of the composite magnetic field of
the Easy-Axis magnetic field Hx and Hard-Axis magnetic field Hy is
in an inside region (blank region) of the asteroid curves, the
direction of magnetization of the magnetic layer 43 cannot be
reversed.
[0015] In addition, as indicated by solid and broken lines in FIG.
18, the magnitude of the Easy-Axis magnetic field Hx, which is
necessary for varying the resistance value of the MTJ element 31,
varies depending on the magnitude of the Hard-Axis magnetic field
Hy. Making use of this phenomenon, the direction of magnetization
of only the MTJ element 31 located at the intersection of the
selected write word line 28 and selected bit line 32, among the
arrayed memory cells, is altered, and thus the resistance value of
the MTJ element 31 can be varied.
[0016] A variation ratio in resistance value of the MTJ element 31
is expressed by an MR (Magneto-Resistive) ratio. For example, if
the magnetic field Hx is produced in the Easy-Axis direction, the
resistance value of the MTJ element 31 varies, e.g. about 17%,
compared to the state before the production of magnetic field Hx.
In this case, the MR ratio is 17%. The MR ratio varies depending on
the properties of the magnetic layer. At present, MTJ elements with
an MR ratio of about 50% have successfully been obtained.
[0017] As has been described above, the direction of magnetization
of the MTJ element 31 is controlled by varying each of the
magnitudes of Easy-Axis magnetic field Hx and Hard-Axis magnetic
field Hy and by varying the magnitude of the composite magnetic
field of the fields Hx and Hy. In this manner, a state in which the
direction of magnetization of the MTJ element 31 is parallel or a
state in which the direction of magnetization of the MTJ element 31
is anti-parallel is created, and information "1" or "0" is
stored.
[0018] FIG. 19 is a cross-sectional view of a prior-art magnetic
memory device having a transistor. FIG. 20 is a cross-sectional
view of a prior-art magnetic memory device having a diode. An
operation of reading out information from the MTJ element will be
described below.
[0019] Data read-out is effected by supplying a current to a
selected MTJ element 31 and detecting the resistance value of the
MTJ element 31. The resistance value is varied by applying a
magnetic field to the MTJ element 31. The varied resistance value
is read out by the following method.
[0020] In the example shown in FIG. 19, a MOSFET 64 is used as a
switching element for data read-out. As is shown in FIG. 19, an MTJ
element 31 is connected in series to a source/drain diffusion layer
63 of the MOSFET 64 in one cell. If the gate of the MOSFET 64,
which is a chosen one, is turned on, a current path is formed
through the following elements in the named order: a bit line 32,
MTJ element 31, a lower electrode 30, a contact 29, second wiring
28, a contact 27, first wiring 26, a contact 25, and source/drain
diffusion layer 63. Thus, the resistance value of the MTJ element
31, which is connected to the turned-on MOSFET 64, can be read
out.
[0021] In the example of FIG. 20, a diode 73 is used as a switching
element for data read-out. As is shown in FIG. 20, an MTJ element
31 is connected in series to a diode 73 within a cell, the diode 73
comprising a P.sup.+ first diffusion layer 71 and an N.sup.- second
diffusion layer 72. By adjusting a bias voltage so as to cause a
current to flow to the diode 73, which is a chosen one, the
resistance value of the MTJ element 31 connected to the diode 73
can be read out.
[0022] If the resistance value, which has been read out as
described above, is low, it is determined that information "1" has
been written. If the resistance value is high, it is determined
that information "0" has been written.
[0023] In the prior-art magnetic memory device, the switching
element is formed in a bulk substrate 61. In the magnetic memory
device using the diode 73 as the switching device, as shown in FIG.
20, the N.sup.- second diffusion layer 72 is formed to be shallower
than the bottom surface of a element isolation region 65 and the
P.sup.+ first diffusion layer 71 is formed in a surface portion of
the N.sup.- second diffusion layer 72, thereby ensuring electrical
isolation between the present cell and adjacent cells. Hence, when
the diode 73 is to be formed using the bulk substrate 61, it is
necessary to form a very shallow P.sup.+ first diffusion layer 71.
However, to form a shallow P.sup.+ first diffusion layer 71 is
difficult because of limitations in the process, and thus it is
difficult to obtain uniform diode characteristics.
BRIEF SUMMARY OF THE INVENTION
[0024] According to a first aspect of the present invention, there
is provided a magnetic memory device comprising: an SOI substrate
having a first semiconductor layer, a first insulating film formed
on the first semiconductor layer, and a second semiconductor layer
formed on the first insulating film; an element isolation
insulating film formed selectively in the second semiconductor
layer extending from a surface of the second semiconductor layer
with a depth reaching the first insulating film; a switching
element formed in the second semiconductor layer; a
magneto-resistive element connected to the switching element; a
first wiring extending in a first direction at a distance below the
magneto-resistive element; and a second wiring formed on the
magneto-resistive element and extending in a second direction
different from the first direction.
[0025] According to a second aspect of the invention, there is
provided a method of manufacturing a magnetic memory device,
comprising: forming an SOI substrate having a first semiconductor
layer, a first insulating film formed on the first semiconductor
layer, and a second semiconductor layer formed on the first
insulating film; forming an element isolation insulating film
selectively in the second semiconductor layer, the element
isolation insulating film extending from a surface of the second
semiconductor layer with a depth reaching the first insulating
film; forming a switching element in the second semiconductor
layer; forming a first wiring extending in a first direction;
forming a magneto-resistive element connected to the switching
element at a distance above the first wiring; and forming a second
wiring on the magneto-resistive element, the second wiring
extending in a second direction different from the first
direction.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0026] FIG. 1 is a cross-sectional view of a magnetic memory device
according to a first embodiment of the present invention;
[0027] FIG. 2 is a circuit diagram of the magnetic memory device
according to the first embodiment of the invention;
[0028] FIG. 3A and FIG. 3B are cross-sectional views showing an MTJ
element of a single tunnel junction structure according to each of
embodiments of the present invention;
[0029] FIG. 4A and FIG. 4B are cross-sectional views showing an MTJ
element of a double tunnel junction structure according to each of
embodiments of the present invention;
[0030] FIGS. 5, 6 and 7 are cross-sectional views illustrating
fabrication steps of the magnetic memory device according to the
first embodiment of the invention;
[0031] FIG. 8 is a circuit diagram showing a magnetic memory device
according to a second embodiment of the invention;
[0032] FIGS. 9A and 9B are cross-sectional views showing a magnetic
memory device according to a third embodiment of the invention;
[0033] FIGS. 10A, 10B and 10C are cross-sectional views
illustrating fabrication steps of a first method for fabricating
the magnetic memory device according to the third embodiment of the
invention;
[0034] FIGS. 11A, 11B, 11C, 11D, 11E and 11F are cross-sectional
views illustrating fabrication steps of a second method for
fabricating the magnetic memory device according to the third
embodiment of the invention;
[0035] FIG. 12 is a plan view of a magnetic memory device according
to a fourth embodiment of the invention;
[0036] FIG. 13A is a cross-sectional view of the magnetic memory
device, taken along line XIIIA-XIIIA in FIG. 12;
[0037] FIG. 13B is a cross-sectional view of the magnetic memory
device, taken along line XIIIB-XIIIB in FIG. 12;
[0038] FIG. 14 is a circuit diagram of the magnetic memory device
according to the fourth embodiment of the invention;
[0039] FIGS. 15A, 15B and 15C are cross-sectional views showing a
prior-art MTJ element;
[0040] FIG. 16 shows MTJ elements arranged in a matrix in the
prior-art magnetic memory device;
[0041] FIG. 17 shows asteroid curves relating to the prior-art
magnetic memory device;
[0042] FIG. 18 shows MTJ curves relating to the prior-art magnetic
memory device;
[0043] FIG. 19 is a cross-sectional view of a prior-art magnetic
memory device having a transistor; and
[0044] FIG. 20 is a cross-sectional view of a prior-art magnetic
memory device having a diode.
DETAILED DESCRIPTION OF THE INVENTION
[0045] Embodiments of the present invention relate to magnetic
random access memories (MRAMs) using as memory elements magnetic
tunnel junction (MTJ) elements that make use of a tunneling
magneto-resistive effect.
[0046] Embodiments of the invention will now be described with
reference to the accompanying drawings. In the following
descriptions referring to all Figures, common parts are denoted by
like reference numerals.
First Embodiment
[0047] In a first embodiment of the invention, a diode is formed
using an SOI (Silicon On Insulator) substrate, and a potential of a
gate electrode is fixed.
[0048] FIG. 1 is a cross-sectional view of a magnetic memory device
according to the first embodiment of the invention. FIG. 2 is a
circuit diagram schematically showing the magnetic memory device
according to the first embodiment of the invention.
[0049] As is shown in FIGS. 1 and 2, the magnetic memory device
according to the first embodiment employs an SOI substrate 14
comprising first and second semiconductor layers 11 and 12, and a
buried oxide film 13 formed between the first and second
semiconductor layers 11 and 12. In the SOI substrate 14, element
isolation regions 15 of, e.g. an STI (Shallow Trench Isolation)
structure are selectively formed from a surface of the second
semiconductor layer 12 to a depth reaching the buried oxide film
13. The second semiconductor layer 12 surrounded by the buried
oxide film 13 and element isolation regions 15 is formed in each
cell. A gate electrode 17 is selectively formed over the second
semiconductor layer 12 surrounded by these insulating films 13 and
15, with a gate insulating film 16 interposed. The gate electrode
17 is fixed at a predetermined potential, e.g. a ground potential.
A P.sup.+ first diffusion layer 19 is formed in that portion of the
second semiconductor layer 12, which is near one end of the gate
electrode 17, and an N.sup.+ second diffusion layer 21 is formed in
that portion of the second semiconductor layer 12, which is near
the other end of the gate electrode 17. Thus, a so-called
gate-control-type diode 10 is formed on the SOI substrate 14.
[0050] An MTJ element 31 is connected in series to the first
diffusion layer 19 of diode 10 via first to fourth contacts 23a,
25, 27 and 29, first to third wirings 24a, 26 and 28a and a lower
electrode 30. A bit line 32 is connected to the MTJ element 31. A
write word line 28b formed of the third wiring is provided at a
distance below the MTJ element 31.
[0051] A first contact 23b and a first wiring 24b are connected to
the second diffusion layer 21 of diode 10. The first wiring 24b is
connected to a peripheral circuit (not shown).
[0052] The MTJ element 31 comprises at least three layers, i.e., a
magnetically fixed layer (magnetic layer) 41 whose magnetization
direction is fixed, a tunnel junction layer (nonmagnetic layer) 42,
and a magnetic recording layer (magnetic layer) 43 whose
magnetization direction is reversible. This MTJ element 31 can have
either a single tunnel junction structure comprising a single
tunnel junction layer 42, or a double tunnel junction structure
comprising two tunnel junction layers. Examples of the single and
double tunnel junction structures will be described below.
[0053] An MTJ element 31 with the single tunnel junction structure,
as shown in FIG. 3A, has a magnetically fixed layer 41, a tunnel
junction layer 42 formed on this magnetically fixed layer 41, and a
magnetic recording layer 43. The magnetically fixed layer 41 is
formed by stacking a template layer 101, an initial ferromagnetic
layer 102, an anti-ferromagnetic layer 103, and a reference
ferromagnetic layer 104 in this order. The magnetic recording layer
43 is formed by stacking a free ferromagnetic layer 105 and a
contact layer 106 in this order on the tunnel junction layer
42.
[0054] An MTJ element 31 with the single tunnel junction structure,
as shown in FIG. 3B, has a magnetically fixed layer 41, a tunnel
junction layer 42 formed on this magnetically fixed layer 41, and a
magnetic recording layer 43. The magnetically fixed layer 41 is
formed by stacking a template layer 101, an initial ferromagnetic
layer 102, an anti-ferromagnetic layer 103, a ferromagnetic layer
104', a nonmagnetic layer 107, and a ferromagnetic layer 104'' in
this order. The magnetic recording layer 43 is formed by stacking a
ferromagnetic layer 105', a nonmagnetic layer 107, a ferromagnetic
layer 105'', and a contact layer 106 in this order on the tunnel
junction layer 42.
[0055] This MTJ element 31 shown in FIG. 3B has a three-layered
structure made up of the ferromagnetic layer 104', the nonmagnetic
layer 107, and the ferromagnetic layer 104'' in the magnetically
fixed layer 41, and another three-layered structure made up of the
ferromagnetic layer 105', the nonmagnetic layer 107, and the
ferromagnetic layer 105'' in the magnetic recording layer 43.
Accordingly, compared to the MTJ element 31 shown in FIG. 3A, this
MTJ element 31 shown in FIG. 3B can more suppress the generation of
magnetic poles inside the ferromagnetic layers and provide a cell
structure more suited to micropatterning.
[0056] An MTJ element 31 with the double tunnel junction structure,
as shown in FIG. 4A, has a first magnetically fixed layer 41a, a
first tunnel junction layer 42a formed on this first magnetically
fixed layer 41a, a magnetic recording layer 43 formed on this first
tunnel junction layer 42a, a second tunnel junction layer 42b
formed on this magnetic recording layer 43, and a second
magnetically fixed layer 41b. The first magnetically fixed layer
41a is formed by stacking a template layer 101, an initial
ferromagnetic layer 102, an anti-ferromagnetic layer 103, and a
reference ferromagnetic layer 104 in this order. The second
magnetically fixed layer 41b is formed by stacking a reference
ferromagnetic layer 104, an anti-ferromagnetic layer 103, an
initial ferromagnetic layer 102, and a contact layer 106 in this
order on the second tunnel junction layer 42b.
[0057] An MTJ element 31 with the double tunnel junction structure,
as shown in FIG. 4B, has a first magnetically fixed layer 41a, a
first tunnel junction layer 42a formed on this first magnetically
fixed layer 41a, a magnetic recording layer 43, a second tunnel
junction layer 42b formed on this magnetic recording layer 43, and
a second magnetically fixed layer 41b. The first magnetically fixed
layer 41a is formed by stacking a template layer 101, an initial
ferromagnetic layer 102, an anti-ferromagnetic layer 103, and a
reference ferromagnetic layer 104 in this order. The magnetic
recording layer 43 is formed by stacking a ferromagnetic layer 43',
a nonmagnetic layer 107, and a ferromagnetic layer 43'' in this
order on the first tunnel junction layer 42a. The second
magnetically fixed layer 41b is formed by stacking a reference
ferromagnetic layer 104', a nonmagnetic layer 107, a ferromagnetic
layer 104'', an anti-ferromagnetic layer 103, an initial
ferromagnetic layer 102, and a contact layer 106 in this order on
the second tunnel junction layer 42b.
[0058] This MTJ element 31 shown in FIG. 4B has a three-layered
structure made up of the ferromagnetic layer 43', the nonmagnetic
layer 107, and the ferromagnetic layer 43'' forming the magnetic
recording layer 43, and another three-layered structure made up of
the ferromagnetic layer 104', the nonmagnetic layer 107, and the
ferromagnetic layer 104'' in the second magnetically fixed layer
41b. Accordingly, compared to the MTJ element 31 shown in FIG. 4A,
this MTJ element 31 shown in FIG. 4B can more suppress the
generation of magnetic poles inside the ferromagnetic layers and
provide a cell structure more suited to micropatterning.
[0059] The double tunnel junction structure MTJ element 31 suffers
less deterioration in the MR (Magneto Resistive) ratio (variation
in resistance between "1" and "0" states) than the single tunnel
junction structure MTJ element 31, when the same external bias is
applied. Hence, the double tunnel junction structure MTJ element 31
can operate at a higher bias than the single tunnel junction
structure MTJ element 31. This is advantageous in reading out data
from a cell.
[0060] The single or double tunnel junction structure MTJ element
31 as described above is formed using the following materials.
[0061] Preferred examples of the material of the magnetically fixed
layers 41, 41a, and 41b and the magnetic recording layer 43 are Fe,
Co, Ni, and their alloys, magnetite having a large spin
polarizability, oxides such as CrO.sub.2 and RXMnO.sub.3-y (R; rare
earth element, X; Ca, Ba, or Sr), and Heusler alloys such as NiMnSb
and PtMnSb. Nonmagnetic elements such as Ag, Cu, Au, Al, Mg, Si,
Bi, Ta, B, C, O, N, Pd, Pt, Zr, Ir, W, Mo, and Nb can also be more
or less contained in these magnetic substances, provided that
ferromagnetism is not lost.
[0062] As the material of the anti-ferromagnetic layer 103 forming
part of these magnetically fixed layers 41, 41a, and 41b, it is
preferable to use Fe--Mn, Pt--Mn, Pt--Cr--Mn, Ni--Mn, Ir--Mn, NiO,
or Fe.sub.2O.sub.3.
[0063] As the material of the tunnel junction layers 42, 42a, and
42b, it is possible to use various dielectric substances such as
Al.sub.2O.sub.3, SiO.sub.2, MgO, AlN, Bi.sub.2O.sub.3, MgF.sub.2,
CaF.sub.2, SrTiO.sub.2, and AlLaO.sub.3. Oxygen, nitrogen, and
fluorine deficiencies may be present in these dielectric
substances.
[0064] FIGS. 5, 6 and 7 are cross-sectional views illustrating
fabrication steps of the magnetic memory device according to the
first embodiment of the invention. A process of manufacturing the
magnetic memory device according to the first embodiment will now
be described.
[0065] As is shown in FIG. 5, an SOI substrate 14 is prepared. The
SOI substrate 14 comprises, for example, a P type first
semiconductor layer 11, a second semiconductor layer 12 and a
buried oxide film 13 formed of, e.g. a silicon oxide film. Device
isolation regions 15 of an STI (Shallow Trench Isolation) structure
are selectively formed from a surface of the second semiconductor
layer 12 to a depth reaching the buried oxide film 13. Then, ion
implantation and thermal diffusion is effected in the second
semiconductor layer 12, and thus the second semiconductor layer 12
of, e.g. P type, is formed. Alternatively, the second semiconductor
layer 12 may be of N type. A gate electrode 17 is selectively
formed on the second semiconductor layer 12, with a gate insulating
film 16 interposed.
[0066] Subsequently, as shown in FIG. 6, a photoresist 18 is coated
on the gate electrode 17 and second semiconductor layer 12, and the
photoresist 18 is patterned as desired. Using the photoresist 18 as
a mask, ion implantation and thermal diffusion are effected in the
second semiconductor layer 12. Thereby, a P.sup.+ type first
diffusion layer 19 is formed in that region of the second
semiconductor layer 12, which is located near one end of the gate
electrode 17. The photoresist 18 is then removed.
[0067] As is shown in FIG. 7, a photoresist 20 is coated on the
gate electrode 17 and second semiconductor layer 12, and the
photoresist 20 is patterned as desired. Using the photoresist 20 as
a mask, ion implantation and thermal diffusion are effected in the
second semiconductor layer 12. Thereby, a N.sup.+ type second
diffusion layer 21 is formed in that region of the second
semiconductor layer 12, which is located near the other end of the
gate electrode 17. Thereafter, the photoresist 20 is removed.
[0068] Following the above steps, an insulating film 22 is formed
on the gate electrode 17, second semi-conductor layer 12 and
element isolation regions 15, as shown in FIG. 1. Using publicly
known art, first to fourth contacts 23a, 23b, 25, 27 and 29 and
first to third wirings 24a, 24b, 26, 28a and 28b are formed within
the insulating film 22. The first to fourth contacts 23a, 25, 27
and 29 and first to third wirings 24a, 26 and 28a are connected to
the first diffusion layer 19. The first contact 23b and first
wiring 24b are connected to the second diffusion layer 21. The
third wiring 28b functions as write word line. A lower electrode 30
is provided on the fourth contact 29. An MTJ element 31 is formed
on that part of the write word line 28b, which is located above the
write word line 28b. A bit line 32 is formed on the MTJ element
31.
[0069] Either the first diffusion layer 19 or the second diffusion
layer 21 may be first formed. Thus, alternatively, the second
diffusion layer 21 may be first formed.
[0070] According to the first embodiment, the diode 10 is formed
using the SOI substrate 14. Thus, the second semiconductor layer 12
is surrounded by the buried oxide film 13 (located below the second
semiconductor layer 12) and the element isolation regions 15 in
each cell. Hence, each cell is electrically isolated from adjacent
cells by the buried oxide film 13 and element isolation regions 15.
Therefore, unlike the prior art, there is no need to adjust the
depth of the first and second diffusion layers 19 and 21 for
electrical isolation from adjacent cells, and a variance in diode
characteristics can be suppressed.
[0071] In the case where the diode 10 is formed using the SOI
substrate 14, the first and second diffusion layers 19 and 21 do
not extend to adjacent cells while the ion implantation and thermal
diffusion are being carried out in forming these first and second
diffusion layers 19 and 21. Therefore, there is no need to keep a
long distance between adjacent cells, and thus the memory cell size
can be reduced.
[0072] It is preferable that the first and second diffusion layers
19 and 21 be formed with a predetermined distance X kept
therebetween. If the first and second diffusion layers 19 and 21
are formed to contact each other, a PN junction would be created at
the interface thereof and a leak current would flow. The distance X
between the first and second diffusion layers 19 and 21 may be, for
example, equal to a width Y of the gate electrode 17. If reduction
in area occupied by the memory cell region is taken into account,
it is preferable that the distance X be about 1/2 of the width Y of
gate electrode 17. In order to make the distance X between the
first and second diffusion layers 19 and 21 less than the width Y
of the gate electrode 17, as mentioned above, the following method
can be adopted: to form the first and second diffusion layers 19
and 21 before forming a side-wall insulating film on a side wall of
the gate electrode 17 by adjusting the time for heat treatment, and
then to form the side-wall insulating film on the side wall of the
gate electrode 17.
[0073] In the first embodiment, the second semiconductor layer 12
is of the P type. Alternatively, it may be of the N type. It should
suffice if the impurity concentration in the second semiconductor
layer 12 is set to be lower than that in the first diffusion layer
19 or second diffusion layer 21.
Second Embodiment
[0074] In a second embodiment of the present invention, the
potential of the gate electrode formed on the SOI substrate is made
variable. As regards the second embodiment, only differences from
the first embodiment will be described.
[0075] FIG. 8 is a circuit diagram of a magnetic memory device
according to the second embodiment of the invention. As is shown in
FIG. 8, the second embodiment differs from the first embodiment in
that the potential of the gate electrode is made variable.
Specifically, where the second semiconductor layer 12, which will
serve as a channel region, is a P type diffusion layer, a negative
gate voltage is applied to the gate electrode 17. On the other
hand, where the second semiconductor layer 12, which will serve as
a channel region, is an N type diffusion layer, a positive gate
voltage is applied to the gate electrode 17. The reason why the
potential of the gate electrode 17 is made variable will be
explained below.
[0076] The first embodiment employs a diode 10 with a diode
structure, which is generally called a "gate control" diode
structure. The I-V characteristics of the diode 10 will vary
depending on the gate voltage. This phenomenon is caused by an
interface level that is present under the gate electrode 17.
Normally, a depletion layer is created under the gate electrode 17
in accordance with a voltage applied to the gate electrode 17. In
this case, if an interface level is present in the depletion layer,
the interface level functions as a center of junction and a reverse
bias current is caused to flow. In general terms, the higher the
gate voltage on the positive side, the greater the width of the
depletion layer and the higher the reverse bias current.
[0077] In the case where the second semiconductor layer 12, which
will function as the channel region under the gate electrode 17, is
the P type diffusion layer, as shown in FIG. 1 (the first
embodiment), a PN junction between the N.sup.+ type second
diffusion layer 21 and the P type second semiconductor layer 12
will be a problem. In order to prevent the occurrence of a reverse
bias current due to the interface level, it should suffice to set
the gate voltage to have a negative value. On the other hand, where
the second semiconductor layer 12, which will function as the
channel region under the gate electrode 17, is the N type diffusion
layer, it should suffice if the gate voltage is set to have a
positive value. In the second embodiment, in order to prevent the
occurrence of a reverse bias current due to the interface level,
the potential of the gate electrode 17 is made variable in this
manner.
[0078] According to the second embodiment, the same advantages as
with the first embodiment can be obtained.
[0079] Furthermore, the gate voltage to be applied to the gate
electrode 17 is selectively set to have a positive value or a
negative value in accordance with the conductivity type of the
second semiconductor layer 12 functioning as the channel region.
Thereby, the occurrence of the reverse bias current due to the
interface level can be prevented.
Third Embodiment
[0080] A third embodiment of the invention relates to a structure
wherein an SOI substrate is used for the memory cell array region
and a bulk substrate is used for the peripheral circuit region. As
regards the third embodiment, only differences from the first
embodiment will be explained.
[0081] FIGS. 9A and 9B are cross-sectional views showing a magnetic
memory device according to a third embodiment of the invention. As
is shown in FIG. 9, in the magnetic memory device according to the
third embodiment, the SOI substrate 14 is not used for both the
memory cell array region and peripheral circuit region. A bulk
substrate 51 is used for the peripheral circuit region alone.
Specifically, in the memory cell array region, like the first
embodiment, the diode 10 is formed using the SOI substrate 14. On
the other hand, in the peripheral circuit region, the bulk
substrate 51 is used and a peripheral transistor 52 is formed on
the bulk substrate 51.
[0082] As shown in FIG. 9A, the surface of the bulk substrate 51 is
substantially on a level with the surface of the first
semiconductor layer 11 of SOI substrate 14. Accordingly, there is a
stepped portion at a boundary between the memory cell array region
and peripheral circuit region, and the level of the gate electrode
17 in the memory cell array region differs from that of a gate
electrode 53 in the peripheral circuit region.
[0083] As shown in FIG. 9B, the surface of the bulk substrate 51 is
substantially on a level with the surface of the second
semiconductor layer 12 of SOI substrate 14. Accordingly, there is
not the stepped portion at the boundary between the memory cell
array region and peripheral circuit region, and the gate electrode
17 in the memory cell array region is substantially on a level with
the gate electrode 53 in the peripheral circuit region.
[0084] FIGS. 10A through 11C are cross-sectional views illustrating
fabrication steps of the magnetic memory device according to the
third embodiment of the invention. Two methods for fabricating the
SOI substrate in the memory cell array region alone will now be
described.
[0085] The steps of a first method will first be described
referring to FIGS. 10A, 10B and 10C. As is shown in FIG. 10A, a
silicon oxide film 2 serving as a mask layer is provided on, e.g. a
P type silicon substrate 1 in the memory cell array region and
peripheral circuit region. A photoresist 3 is formed on the silicon
oxide film 2, and it is patterned so as to remain only in the
memory cell array region. Next, as shown in FIG. 10B, using the
photoresist 3 as a mask, the silicon oxide film 2 is selectively
etched, following which the photoresist 3 is removed. Using the
silicon oxide film 2 as a mask, O.sup.+ ions, for instance, are
implanted only in the peripheral circuit region. Thereafter, the
silicon oxide film 2 is removed. Then, as shown in FIG. 10C, a
buried oxide film 13 is formed in the memory cell array region
alone by annealing. Thus, the SOI substrate 14 is formed.
[0086] The steps of a second method will now be described referring
to FIGS. 11A, 11B and 11C. As is shown in FIG. 11A, an SOI
substrate 14 is formed, which comprises first and second
semiconductor layers 11 and 12 and a buried oxide film 13 formed
between the first and second first and second semiconductor layers
11 and 12. A photoresist 3 is formed on the second semiconductor
layer 12, and it is patterned to remain only in the memory cell
array region. Using the photoresist 3 as a mask, as shown in FIG.
11B, the second semiconductor layer 12 and buried oxide film 13 in
the peripheral circuit region are etched. Then, as shown in FIG.
11C, the photoresist 3 is removed. The SOI substrate 14 is thus
left only in the memory cell array region.
[0087] Following the step of FIG. 11C, the stepped portion between
the memory cell array region and peripheral circuit region may be
eliminated by the following method. For example, as shown in FIG.
11D, a silicon nitride film 4 is deposited on the entire surface of
the memory cell array region and peripheral circuit region, and
only that portion of the silicon nitride film 4, which lies on the
peripheral circuit region, is removed by a lithography technique.
Then, as shown in FIG. 11E, Si on the exposed surface is
selectively grown up to a level substantially corresponding to the
surface level of the second semiconductor layer 12 by means of
selective epitaxial growth (SEG). Thereby, an epitaxial growth
layer 5 is formed in the peripheral circuit region. The silicon
nitride film 4 on the second semiconductor layer 12 is removed, as
shown in FIG. 11F.
[0088] According to the third embodiment, the following advantage
as well as the advantages of the first embodiment can be
obtained.
[0089] In general, a body contact needs to be added to a transistor
in a CMOS circuit formed on the SOI substrate 14. The provision of
the body contact will disadvantageously increase the chip area. In
the third embodiment, however, the SOI substrate 14 is used for the
memory cell array region, but the bulk substrate 51 is used for the
peripheral circuit region. As a result, there is no need to add a
body contact to the peripheral transistor 52, and the chip area can
be reduced, compared to the case where the SOI substrate is used
for both the memory cell array region and peripheral circuit
region.
[0090] The voltage to be applied to the gate electrode of the
memory cell array region according to the third embodiment may be
made variable, similarly with the second embodiment. In this case,
the same advantages as with second and third embodiments can be
obtained.
Fourth Embodiment
[0091] In the first to third embodiments, double-axis data write
using write word lines and bit lines is performed. By contrast, in
a fourth embodiment, single-axis data write using bit lines alone
is performed.
[0092] FIG. 12 is a plan view of a magnetic memory device according
to the fourth embodiment of the invention. FIG. 13A is a
cross-sectional view of the magnetic memory device, taken along
line XIIIA-XIIIA in FIG. 12. FIG. 13B is a cross-sectional view of
the magnetic memory device, taken along line XIIIB-XIIIB in FIG.
12. FIG. 14 is a circuit diagram of the magnetic memory device
according to the fourth embodiment of the invention. As regards the
fourth embodiment, only differences in structure from the first
embodiment will be described.
[0093] As is shown in FIGS. 12, 13A, 13B and 14, a memory cell in
the magnetic memory device according to the fourth embodiment is
composed of an MTJ element, transistors Tr1 and Tr2 for data write,
a transistor Tr3 for data read-out, and bit lines BL1, BL2 and
BLC1.
[0094] Specifically, two transistors Tr1 and Tr2, which are
switching elements for data write, are formed on the SOI substrate
14.
[0095] The gate electrode of the transistor Tr1 functions as a data
read-out/write word line WL1. One of the diffusion layers of the
transistor Tr1 is connected to the bit-line connection wiring BLC1
via a metal wiring ML1, a contact C1, etc. The other diffusion
layer of transistor Tr1 is connected to the bit line BL1 via a
metal wiring ML3, a contact C3, etc.
[0096] The gate electrode of the transistor Tr2 functions as a
write word line WWL1. One of the diffusion layers of the transistor
Tr2 is connected to the bit-line connection wiring BLC1 via the
metal wiring ML2, contact C2, etc. The other diffusion layer of
transistor Tr2 is connected to the bit line BL2 via a metal wiring
ML5, a contact C5, etc.
[0097] The MTJ element is connected at one end to the bit-line
connection wiring BLC1, and at the other end to a ground (GND)
line. The transistor Tr3, which is a switching element for data
read-out, may be connected to the MTJ element.
[0098] In this embodiment, a single write wiring is used. Thus, the
direction of magnetization is made easily reversible by shifting
the angle of intersection between the direction of extension of the
bit-line connection wiring BLC1, which is the write wiring, and the
magnetization direction of the MTJ element, by a certain degree
(e.g. 45.degree.) from 90.degree..
[0099] In the single-axis data write magnetic memory device, as
described above, the data write/read operations are performed as
follows.
[0100] When data is to be written in the MTJ element, the word line
WL1 and write word line WWL1, which are the gate electrodes of the
transistors Tr1 and Tr2 of the selected cell, are turned on. A
write current is let to flow from the bit line BL1 to the bit line
BL2, or vice versa. A magnetic field produced by the write current
changes the magnetization direction of the recording layer of the
MTJ element. The direction of current may be chosen in accordance
with the magnetization direction to be changed. During the write
operation, the transistor Tr3 connected to the common GND line is
turned off, thereby to prevent the write current from flowing to
the MTJ element.
[0101] On the other hand, when data is to be read out of the MTJ
element, the word line WL1 of the transistor Trl of the selected
cell is turned on, and all the write word lines WWL1, 2, . . . ,
are turned off. A read-out current is let to flow from the bit line
BL1 to the ground GND via the MTJ element, and the data is read by
a sense amplifier connected to the bit line BL1. During the
read-out operation, the transistor Tr3 connected to the common GND
line is turned on.
[0102] According to the fourth embodiment, the following advantage,
as well as the advantages of the first embodiment, can be
obtained.
[0103] In the case of the structure for double-axis data write
using write word lines and bit lines, a plurality of bit lines and
word lines are provided in a matrix and MTJ elements are disposed
at intersections of the bit lines and word lines. In the write
operation, data write is effected not only on one MTJ element
located at the intersection of the selected bit line and selected
word line, but also on an MTJ element located below the selected
bit line or above the selected word line. In short, in the case of
the double-axis data write, there is a possibility of erroneous
write in a semi-selected cell.
[0104] By contrast, in the fourth embodiment, the transistors Tr1
and Tr2 are arranged so that a current may flow to only the bit
lines BL1 and BL2 in the data write operation. Hence, a write
current does not flow to cells other than the selected cell, and
there is no semi-selected cell. Therefore, a disturb defect (data
retention defect) in a semi-selected cell can be prevented.
[0105] In the first to third embodiments, the diode is used as a
switching element, but the diode may be replaced with a transistor.
In the fourth embodiment, diodes may be substituted for the
transistors Tr1, Tr2 and Tr3.
[0106] In the first to fourth embodiments, the MTJ element is used
as a memory element. Alternatively, the MTJ element may be replaced
with a GMR (Giant Magneto-Resistive) element comprising two
magnetic layers and a conductive layer interposed therebetween.
[0107] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
* * * * *