U.S. patent application number 10/897067 was filed with the patent office on 2006-01-26 for method of manufacturing a plurality of electronic assemblies.
Invention is credited to John J. Beatty, Jason A. Garcia.
Application Number | 20060019468 10/897067 |
Document ID | / |
Family ID | 35657781 |
Filed Date | 2006-01-26 |
United States Patent
Application |
20060019468 |
Kind Code |
A1 |
Beatty; John J. ; et
al. |
January 26, 2006 |
Method of manufacturing a plurality of electronic assemblies
Abstract
A method of manufacturing a plurality of electronic devices is
provided. Each one of a plurality of first conductive terminals on
a plurality of integrated circuits formed on a device wafer is
connected to a respective one of a plurality of second conductive
terminals on a carrier wafer, thereby forming a combination wafer
assembly. The combination wafer assembly is singulated between the
integrated circuits to form separate electronic assemblies. Each
electronic assembly has a respective die from a separated portion
of the device wafer and a carrier substrate from a separated
portion of the carrier wafer. The process of fabricating electronic
assemblies is simplified and costs are reduced because the dies are
connected to the carrier substrate at wafer level, i.e. before
singulation. The combination wafer assembly also allows for an
underfill material to be introduced and to cured at wafer level and
for thinning of the device wafer at wafer level without requiring a
separate supporting substrate. Alignment between the device wafer
and the carrier wafer can be tested by conducting a current through
first and second conductors in the device and carrier wafers,
respectively.
Inventors: |
Beatty; John J.; (Chandler,
AZ) ; Garcia; Jason A.; (Chandler, AZ) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
12400 WILSHIRE BOULEVARD
SEVENTH FLOOR
LOS ANGELES
CA
90025-1030
US
|
Family ID: |
35657781 |
Appl. No.: |
10/897067 |
Filed: |
July 21, 2004 |
Current U.S.
Class: |
438/464 ;
257/E21.503; 257/E21.705; 257/E25.013; 438/113; 438/114;
438/460 |
Current CPC
Class: |
H01L 21/563 20130101;
H01L 2224/73204 20130101; H01L 25/0657 20130101; H01L 2924/19041
20130101; H01L 23/3114 20130101; H01L 25/50 20130101; H01L
2225/06513 20130101 |
Class at
Publication: |
438/464 ;
438/460; 438/113; 438/114 |
International
Class: |
H01L 21/78 20060101
H01L021/78; H01L 21/48 20060101 H01L021/48; H01L 21/50 20060101
H01L021/50 |
Claims
1. A method of manufacturing a of plurality of electronic
assemblies, comprising: connecting each one of a plurality of first
conductive terminals on a plurality of integrated circuits formed
on a device wafer to a respective one of a plurality of second
conductive terminals on a carrier wafer to form a combination wafer
assembly; and singulating the combination wafer assembly between
the integrated circuits to form the electronic assemblies, each
electronic assembly having a respective die from a separated
portion of the device wafer and a carrier substrate from a
separated portion of the carrier wafer.
2. The method of claim 1, further comprising: introducing an
underfill material that is located between the device wafer and the
carrier wafer before singulating the combination wafer assembly;
and curing the underfill material.
3. The method of claim 2, wherein the underfill material is
introduced into a space between the device wafer and carrier wafer
after connecting the first conductive terminals to the second
conductive terminals.
4. The method of claim 3, wherein the underfill material is
introduced into the space at above atmospheric pressure.
5. The method of claim 4, further comprising: placing the
combination wafer assembly in a jig; and providing the underfill
material through at least a first passage in the jig.
6. The method of claim 4, further comprising: heating the underfill
material before introducing the underfill material into the
space.
7. The method of claim 2 wherein the underfill material is cured
before singulating the combination wafer assembly.
8. The method of claim 1, further comprising: thinning the device
wafer before singulating the combination wafer assembly.
9. The method of claim 8, further comprising: introducing an
underfill material that is located between the device wafer and the
carrier wafer before singulating the combination wafer assembly;
and curing the underfill material.
10. The method of claim 8, wherein the carrier wafer is made of
ceramic.
11. The method of claim 1, further comprising: testing a current
through at least one pair, the pair including a first conductive
terminal and a second conductive terminal before singulating the
combination wafer assembly.
12. The method of claim 11, wherein current is provided through a
first conductor extending through the device wafer and through a
second conductor extending through that carrier wafer.
13. A method of manufacturing a plurality of electronic assemblies,
comprising: introducing an underfill material between a device
wafer and a carrier wafer that form a combination wafer assembly;
curing the underfill material; and singulating the combination
wafer assembly between integrated circuits formed on the device
wafer to form the electronic assemblies, each electronic assembly
having a respective die from a separated portion of the device
wafer and a respective carrier substrate from a separated portion
of the carrier wafer, and a respective portion of the underfill
material between the respective die and the respective carrier
substrate.
14. The method of claim 13, wherein the underfill material is cured
before singulating the combination wafer assembly.
15. The method of claim 13, wherein the underfill material is
introduced between the device wafer and carrier wafer at above
atmospheric pressure.
16. A combination wafer assembly, comprising: a device wafer; a
plurality of integrated circuits formed on the device wafer; a
plurality of first conductive terminals on the integrated circuits;
a carrier wafer; and a plurality of second conductive terminals on
the carrier wafer, each being connected to a respective one of the
first conductive terminals.
17. The combination wafer assembly of claim 16, wherein the
integrated circuits are identical to one another.
18. The combination wafer assembly of claim 16, further comprising:
a plurality of interconnection elements connecting each one of the
first conductive terminals to each one of the second conductive
terminals; and an underfill material in a space between the device
wafer and the carrier wafer and between the interconnection
elements, the underfill material having been cured.
Description
BACKGROUND OF THE INVENTION
[0001] 1). Field of the Invention
[0002] This invention relates generally to a method of
manufacturing a plurality of electronic assemblies, and more
specifically to improvements in fabrication at water level.
[0003] 2). Discussion of Related Art
[0004] Integrated circuits are usually manufactured in and on
semiconductor wafers. Such an integrated circuit has millions of
tiny electronic components such as transistors, capacitors, and
diodes that are interconnected with conductive lines, plugs, and
vias.
[0005] One wafer typically has an array of identical circuits
formed thereon. The wafer was is then "singulated" or "diced" by
directing a blade through scribe streets between the integrated
circuits, thereby separating the wafer into the individual dice.
Each die is then separately mounted to a respective carrier
substrate for purposes of providing structural rigidity to the die
and to provide power, ground, and signals to and from the die.
[0006] A plurality of conductive terminals are formed on the
integrated circuits before the wafer is singulated. Such terminals
are typically solder bumps that are formed according to a
conventional "controlled collapsed chip connect" (C4) process.
After the wafer is singulated, each one of the bumps is placed on a
respective contact of the carrier substrate. The bumps are then
reflowed so that they are structurally and electrically connected
to the contacts. The process is repeated to connect each die
singulated from the wafer to a separate carrier substrate to form
separate electronic assemblies. Downstream fabrication is then
separately carried out on each separate electronic assembly.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The invention is described by way of examples with reference
to the accompanying drawings, wherein:
[0008] FIG. 1 is a cross-sectional side view of first and second
wafer assemblies that are used for forming a combination wafer
assembly, according to an embodiment of the invention;
[0009] FIG. 2 is a view similar to FIG. 1 after the first and
second wafer assemblies are connected to one another by reflowing
the first and second terminals of respectively the first and second
wafer assemblies with one another to form combined terminals;
[0010] FIG. 3 is a view similar to FIG. 2, further illustrating a
system that is used to introduce an underfill material into a space
between the combined terminals;
[0011] FIG. 4 is a view similar to FIG. 3 of a portion of the
combination wafer, illustrating how alignment between the first and
second wafer assemblies is tested;
[0012] FIG. 5 is a view similar to FIG. 2, further illustrating how
a device wafer of the first wafer assembly is thinned without the
need to laminate the first wafer to a supporting substrate;
[0013] FIG. 6 is a view similar to FIG. 2, further illustrating how
the combination wafer assembly is singulated into a plurality of
electronic assemblies; and
[0014] FIGS. 7A, 7B, and 7C are views similar to FIG. 6, further
illustrating packages that can be made from the electronic
assemblies that are singulated out of the combination wafer as
illustrated in FIG. 6.
DETAILED DESCRIPTION OF THE INVENTION
[0015] A method of manufacturing a plurality of electronic devices
is provided. Each one of a plurality of first conductive terminals
on a plurality of integrated circuits formed on a device wafer is
connected to a respective one of a plurality of second conductive
terminals on a carrier wafer, thereby forming a combination wafer
assembly. The combination wafer assembly is singulated between the
integrated circuits to form separate electronic assemblies. Each
electronic assembly has a respective die from a separated portion
of the device wafer and a carrier substrate from a separated
portion of the carrier wafer. The process of fabricating electronic
assemblies is simplified and costs are reduced because the dies are
connected to the carrier substrate at wafer level, i.e., before
singulation. The combination wafer assembly also allows for an
underfill material to be introduced and to cured at wafer level and
for thinning of the device wafer at wafer level without requiring a
separate supporting substrate. Alignment between the device wafer
and the carrier wafer can be tested by conducting a current through
first and second conductors in the device and carrier wafers,
respectively.
[0016] FIG. 1 of the accompanying drawings illustrates first and
second wafer assemblies 10 and 12 that are used for manufacturing a
combination wafer assembly and a plurality of electronic assemblies
from the combination wafer assembly, according to an embodiment of
the invention.
[0017] The first wafer assembly 10 includes a device wafer 14, a
plurality of integrated circuits 16 formed on the device wafer 14,
and a plurality of conductive first terminals 18 formed on each one
of the integrated circuits 16. The device wafer 14 is made of a
semiconductor material such as silicon. The integrated circuits 16
are typically identical to one another. Each integrated circuit 16
has a multitude of electronic elements such as transistors,
capacitors, diodes, etc., formed in and on the material of the
device wafer 14. Each integrated circuit 16 has a plurality of
alternating dielectric and metal layers formed above one another.
The metal layers are patterned to form metal lines that
interconnect the electronic components to one another. The first
terminals 18 are bumps that are formed on the integrated circuit
and connected through the metal lines, plugs and vias to the
electronic components. The bumps are typically formed according to
a conventional controlled collapsed chip connect (C4) process. The
integrated circuits 16 are separated from one another by scribe
streets 20. A metal guard ring (not shown) typically surrounds each
integrated circuit 16 to protect the respective integrated circuit
16 from delamination during downstream sawing or other
singulation.
[0018] The second wafer assembly 12 includes a carrier wafer 22,
typically of a strong material such as ceramic, and a second
plurality of conductive terminals 24 formed on a lower surface of
the carrier wafer 22. The carrier wafer 22 is typically made of a
ceramic material and has metal lines, plugs, and vias formed in the
ceramic material for purposes of electric communication. The second
terminals 24 are connected to the conductive metal lines, plugs,
and vias. The second terminals 24 are typically made utilizing a C4
process.
[0019] The layout of the second terminals 24 is a mirror image of
the layout of the first terminals 18, and each one of the second
terminals 24 is located directly above a respective one of the
first terminals 18. The second wafer assembly 12 is then lowered
onto the first wafer assembly 10 so that a respective one of the
second terminals 24 is in contact with a respective one of the
first terminals 18. The combination is then heated to a temperature
above a melting temperature of the first terminals 18 and 24, so
that each one of the second terminals 24 reflows together with the
respective one of the first terminals 18. The combination is then
allowed to cool, so that the reflowed terminals again solidify.
[0020] FIG. 2 illustrates a combination wafer assembly 28 that
results after the first and second terminals 18 and 24 of FIG. 1
are reflowed together and allowed to cool. Combined terminals 30
are formed that interconnect the integrated circuits 16 with the
carrier wafer 22. A space 32 is maintained between the integrated
circuits 16 and the carrier wafer 22, and a volume between the
combined terminals 30 is filled with a gas, typically air.
[0021] It can be seen that the integrated circuits 16 are connected
to the carrier wafer 22 without first singulating the first wafer
assembly 10. Wafer-level interconnection simplifies the entire
assembly process, thereby reducing cost. Wafer level
interconnection also allows for downstream manufacture, including
the introduction of underfill material and wafer thinning, to be
carried out at wafer level, thereby further simplifying the entire
process and further reducing cost.
[0022] FIG. 3 illustrates a system 34 that is used to introduce an
underfill material into the space 32 of the combination wafer
assembly 28. The system 34 includes a jig 36, having upper and
lower parts 38 and 39, a reservoir 40 for underfill material 42, a
pump 44, and a heater 46.
[0023] That lower part 39 of the jig 36 has a recess in which the
combination wafer assembly 28 is received. Sidewalls 48 of the
lower part 39 surround the combination wafer assembly 28, in
particular the space 32. First and second passages 50 and 52 are
formed through the sidewalls 48 and into and out of the space 32.
The reservoir 40 is connected through that pump 44 to the first
passage 50 to allow for the underfill material 42 to be pumped by
the pump 44 into the first passage 50. The heater 46 is located in
a position to heat the underfill material before being provided to
the first passage 50.
[0024] The upper part 38 of the jig 36 is located on top of the
combination wafer assembly 28, the upper and lower parts 38 and 39
thereby forming a sealed enclosure around the combination wafer
assembly 28, except for the first and second passages 50 and
52.
[0025] In use, the pump 44 is operated to pump the underfill
material 42 out of the reservoir 40 past the heater 46. The heater
46 then heats the underfill material 42 to lower its viscosity. The
heated underfill material 42 then flows above atmospheric pressure
through the first passage 50 into the space 32. A gas located in
the space 32 is vented through the second passage 52. The process
is continued until the space 32 is entirely filled with the
underfill material 42. It may be possible to provide more inlet
passages than just the first passage 50 and/or more outlet passages
than just the second passage 52, and that the passages can be
placed at select locations to tailor flow through the space 32.
[0026] After the underfill material 42 is introduced at wafer
level, the combination wafer assembly 28 may be removed from the
jig 36. The combination wafer assembly 28, with the underfill
material 42 in the space 32, can then be transported through a
furnace. The underfill material 42 is heated to a select
temperature and for a predetermined period of time to cure the
underfill material 42, also at wafer level.
[0027] FIG. 4 illustrates how alignment between the first and
second wafer assemblies 10 and 12 is tested before the combination
wafer assembly 28 is singulated. First and second conductors 53 and
54 are formed through the device wafer 14 and the carrier wafer 22,
respectively. Both conductors 53 and 54 are connected to one of the
combined terminals 30 if the second wafer assembly 12 has been
properly aligned with the first wafer assembly 10. No current will
conduct if the second wafer assembly 12 is misaligned with respect
to the first wafer assembly 10. A circuit is completed by
connecting the second conductor 54 through a power supply such as a
battery 60, a resistor 62, and a current meter 64 to the first
conductor 53. A current will be displayed on the current meter 64
if the first and second wafer assemblies 10 and 12 are correctly
aligned.
[0028] As illustrated in FIG. 5, the combination wafer assembly 28
also allows for thinning of the device wafer 14 without the need to
laminate the first wafer assembly 10 to a supporting substrate, due
to the strength provided by the ceramic carrier wafer 22. The
carrier wafer 22 is attached to a polishing chuck 70. The polishing
chuck 70 is then used to place the combination wafer assembly 28
with the device wafer 14 contacting a polishing pad 72. The
polishing chuck 70 and polishing pad 72 are then moved, typically
rotated, relative to one another so that a lower surface of that
device wafer 14 moves over an upper surface of the polishing pad
72. An upper surface of the polishing pad 72 is abrasive so that
lower portions of the device wafer 14 are removed. The device wafer
14 is so thinned down. The combination wafer assembly 28 is then
removed from the polishing pad 72 and the polishing chuck 70.
[0029] As illustrated in FIG. 6, the combination wafer assembly 28
is subsequently singulated into individual electronic assemblies
74. A blade 76 is directed in x- and y-directions through the
scribe streets 20 and through the carrier wafer 22. Each electronic
assembly 74 then has a respective die 78 from a respective portion
of the device wafer 14 and one of the integrated circuits 16 on the
respective die 78. Each electronic assembly 74 also has a
respective carrier substrate 79 from a respective portion of the
carrier wafer 22. The combination wafer assembly 28 is thus
singulated after interconnection as illustrated in FIG. 2, the
introduction of an underfill material as illustrated in FIG. 3,
alignment testing as illustrated in FIG. 4, and thinning as
illustrated in FIG. 5.
[0030] FIGS. 7A, 7B, and 7C illustrate various assembly packages 80
that can be made from one of the electronic assemblies 74. Each one
of the packages 80 includes a further substrate 82 that is made
from a laminate of conductive and dielectric layers. In the
embodiments of FIGS. 7A and 7C, the additional substrate 82 is
formed directly on the electronic assembly 74. In the embodiment of
FIG. 7B, additional conductive contacts interconnect the electronic
assembly 74 with the additional substrate 82.
[0031] While certain exemplary embodiments have been described and
shown in the accompanying drawings, it is to be understood that
such embodiments are merely illustrative and not restrictive of the
current invention and that this invention is not restricted to the
specific constructions and arrangements shown and described since
modifications may occur to those ordinarily skilled in the art.
* * * * *