U.S. patent application number 11/209483 was filed with the patent office on 2006-01-26 for nonvolatile semiconductor memory with x8/x16 operation mode using address control.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Oh-Suk Kwon, Hyoung-Woo Lee, June Lee.
Application Number | 20060018180 11/209483 |
Document ID | / |
Family ID | 33516398 |
Filed Date | 2006-01-26 |
United States Patent
Application |
20060018180 |
Kind Code |
A1 |
Lee; Hyoung-Woo ; et
al. |
January 26, 2006 |
Nonvolatile semiconductor memory with x8/x16 operation mode using
address control
Abstract
The present invention relates to a nonvolatile semiconductor
memory, that is, a flash memory and especially to a NAND type flash
memory device capable of selectively controlling data input/output
units by an address control. In the NAND type flash memory device,
a memory cell array is divided into a plurality of blocks, and a
data input/output path is selectively controlled by a predetermined
data rate option and introduced addresses to perform data
input/output operations at a .times.8 or .times.16 speed in one
chip.
Inventors: |
Lee; Hyoung-Woo; (Seoul,
KR) ; Lee; June; (Seoul, KR) ; Kwon;
Oh-Suk; (Kyunggi-do, KR) |
Correspondence
Address: |
MARGER JOHNSON & MCCOLLOM, P.C.
210 SW MORRISON STREET, SUITE 400
PORTLAND
OR
97204
US
|
Assignee: |
Samsung Electronics Co.,
Ltd.
Suwon-Si
KR
|
Family ID: |
33516398 |
Appl. No.: |
11/209483 |
Filed: |
August 22, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10835148 |
Apr 28, 2004 |
6958935 |
|
|
11209483 |
Aug 22, 2005 |
|
|
|
Current U.S.
Class: |
365/230.03 ;
365/185.11; 365/230.08 |
Current CPC
Class: |
G11C 8/10 20130101; G11C
16/10 20130101; G11C 7/1045 20130101; G11C 2207/105 20130101; G11C
16/26 20130101 |
Class at
Publication: |
365/230.03 ;
365/185.11; 365/230.08 |
International
Class: |
G11C 8/00 20060101
G11C008/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 19, 2003 |
KR |
2003-39850 |
Claims
1. A nonvolatile semiconductor memory device including a plurality
of data I/O pins, comprising: a memory cell array divided into a
plurality of blocks; a data rate option selector for generating a
data rate control signal according to a predetermined speed option;
a block selector for generating a plurality of block selection
signals to select a block of the memory cell array in response to a
predetermined block selection address from column addresses
introduced through the I/O pins and the data rate control signal; a
column selection circuit for selecting a data line in response to a
predetermined column selection address from the column addresses,
the block selection signals and the data rate control signal and
for outputting data of the memory cell array to the selected data
line; and a data I/O controller for selecting a data line to input
data to, or output data from, the column selection circuit in
response to the block selection signals and the data rate control
signal.
2. The device of claim 1, wherein the memory cell array is divided
into 4 blocks.
3. The device of claim 1, wherein the nonvolatile semiconductor
memory includes 16 data I/O pins.
4. The device of claim 1, wherein the data I/O pins are selected
according to the data rate control signal.
5. The device of claim 1, wherein the column addresses include
block selection addresses and column selection addresses.
6. The device of claim 5, wherein the block selection addresses are
inputted to the block selector.
7. The device of claim 1, wherein the data rate control signal is a
signal for determining the number of data bits inputted or
outputted according to the data rate option.
8. The device of claim 1, wherein the block selector generates
first through fourth block selection signals for selecting each
block of the memory cell array, and selects blocks of the memory
cell array by a combination of the data rate control signal, the
first through fourth block selection signals and the block
selection addresses.
9. The device of claim 1, wherein each of the blocks of the memory
cell array have a corresponding one of the column selection
circuits each having a respective column decoder circuit and column
predecoder circuit.
10. The device of claim 9, wherein the column predecoder circuit
comprises: a first predecoder circuit for predecoding introduced
column selection addresses to generate one or more latch control
signals; and a second column predecoder circuit for generating one
or more gate control signals in response to predetermined column
selection addresses from the column selection addresses, the block
selections signals and the data rate control signal.
11. The device of claim 10, wherein one or more of the gate control
signals select a data line for inputting/outputting data from/to
the column decoder circuit.
12. The device of claim 9, wherein the column decoder circuit
outputs the data from the memory cell array to the selected data
line in response to one or more the latch control signal and the
gate control signals.
13. The device of claim 1, wherein the data input/output controller
comprises: a first control circuit for selecting a data line to
input/output data in response to the first of the block selection
signals and second of the block selection signals; a second control
circuit for selecting a data line to input/output data in response
to the first block selection signal and the second block selection
signal; and a third control circuit for selecting a data line to
input/output data in response to the data rate control signal, a
third of the block selection signals and a fourth of the block
selection signal.
14. The device of claim 13, wherein the first control circuit
comprises: a first data input circuit for selecting a data line to
input data in response to the first block selection signal and the
second block selection signal; and a first data output circuit for
selecting a data line for outputting data in response to the first
block selection signal.
15. The device of claim 13, wherein the second control circuit
comprises: a second data input circuit for selecting a data line to
input data in response to the first block selection signal and the
second block selection signal; and a second data ouput circuit for
selecting a data line for outputting data in response to the first
block selection signal.
16. The device of claim 13, wherein the third control circuit
comprises: a third data input circuit for selecting a data line to
input data in response to the data rate control signal; and a third
data output circuit for selecting a data line to output data in
response to the data rate control signal, the third block selection
signal and the fourth block selection signal.
17. A nonvolatile semiconductor memory device comprising: a memory
cell array divided into 4 blocks; a data I/O part including 16 data
I/O pins; a column address register for sequentially outputting
column addresses introduced from the data input/output part
according to a synchronization signal; a data rate option selector
for generating one of an .times.8 or .times.16 data rate control
signal according to a preset data rate option; a block selector for
generating first through fourth block selection signals to select a
block in the memory cell array in response to one or more block
selection addresses from the column address register and the data
rate control signal; a column selection circuit for selecting a
data line to input/output data in response to the column selection
addresses from the column address register, the first through
fourth block selection signals and the data rate control signal,
and for outputting the data in the memory to the selected data
line; a first control circuit for selecting a data line to
input/output data in response to the first block selection signal
and the second block selection signal; and a second control circuit
for selecting a data line to input/output data in response to the
data rate control signal, the third block selection signal and the
fourth block selection signal.
18. The device of claim 17, wherein the data rate control signal
determines the number of data bits inputted or outputted according
to the data rate option.
19. The device of claim 17, wherein the first control circuit
comprises: a first data input circuit for selecting a data line to
input data in response to the first block selection signal and the
second block selection signal; and a first data output circuit for
selecting a data line to output data in response to the first block
selection signal.
20. The device of claim 17, wherein the second control circuit
comprises: a second data input circuit for selecting a data line to
input data in response to the data rate control signal; and a
second data output circuit for selecting a data line to output data
in response to the data rate control signal, the third block
selection signal and the fourth block selection signal.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Continuation application of U.S.
patent application Ser. No. 10/835,148, filed on 28 Apr. 2004. This
application claims priority from Korean Patent Application No.
2003-39850, filed on Jun. 19, 2003, the contents of which are
herein incorporated by reference in their entirety for all
purposes.
FIELD OF THE INVENTION
[0002] The present invention generally relates to a flash memory
(i.e., one of non-volatile semiconductor memories) devices and
especially to NAND type flash memory devices capable of selectively
controlling input/output of a data storage unit using
addresses.
BACKGROUND OF THE INVENTION
[0003] A flash memory is capable of maintaining stored data without
an external power supply. In addition, the flash memory can perform
electrical erase and program operations freely even without
additional refresh processes applied to the stored data. Since a
NAND type flash memory has a string structure consisting of a
plurality of flash memory cells connected in serial, the NAND type
flash memory is suitable for a high integration and widely used in
portable electronic apparatuses as a data storage.
[0004] With rapidly increasing use of data requiring large storage
capacity, such as motion pictures, voices and graphics, the NAND
type flash memory having high integration density has been more
widely used.
[0005] The NAND type flash memory is characterized by several
operation methods that draw clear line between flash memories and
other memories apart from cell characteristics. One of the most
critical characteristics for the NAND type flash memory in the
ability to operate in the methods of a command preset and an
address preset.
[0006] According to the command preset method, commands that are
combinations of predetermined bits (e.g., 00 h, 80 h, etc.) are
inputted into a chip through an I/O pin to determine a next
operation. According to the address preset method, an address to
read or write data is inputted into the chip directly before
starting an operation.
[0007] The other memories such as SRAMs start to perform reading or
writing operation of data as soon as an address and a clock for the
operations are introduced. In contrast, the NAND type flash memory
inputs a command to perform and an address into a chip using the
above command preset method and the address preset method, and then
performs the operation of reading or writing data if a clock is
inputted. In the NAND type flash memory, there is clear interval
between the time when data is inputted or outputted and the time
when the address or command is introduced. Therefore, an input pin
for introducing addresses or commands can be used in common with a
data I/O pin.
[0008] FIG. 1 is a block diagram illustrating a conventional
.times.8 NAND type flash memory.
[0009] As shown in FIG. 1, the conventional NAND type flash memory
includes a memory cell array 100, a row selection circuit 101, a
column selection circuit 103, a data latch circuit 102, a control
circuit 104 and a data input/output circuit 105. The memory cell
array 100 is a data storage, and the row selection circuit 101
selects a row of the memory cell array 100 according to row
addresses A12 to A27. The column selection circuit 103 selects a
column of the memory cell array 100 according to column addresses
A0 to A11. The data latch circuit 102 latches the data of the
memory cell array 100. The control circuit 104 controls operations
inputting/outputting the data according to inputted clock signals
nWE, nRE and nCE and control signals ALE, CLE and Command.
[0010] Conventional NAND type flash memory comprises eight data I/O
pins I/O0.about.I/O7 coupled to the data I/O circuit 105, a
plurality of clock signal nWE, nRE, nCE input pins and control
signal ALE, CLE input pins. The data I/O pins I/O0.about.I/O7 are
used for inputting the command and the address A0.about.A27 and for
inputting/outputting data. The clock signal nWE, nRE, nCE input
pins control memory operations, and the control signal ALE, CLE
input pins determine a kind of the data inputted into the data I/O
pins I/O0.about.I/O7. The clock signal nWE is used for a
synchronization of the addresses, commands and data introduced in
the memory. The clock signal nRE is used for a synchronization at
the time of data read out, and the clock signal nCE is used for
selecting an operation of memory chip. The address latch enable
(ALE) signal is a control signal used for identifying the data
transferred through the data I/O pins I/O0.about.I/O7 as an
address. The command latch enable (CLE) signal is a control signal
used for identifying the data transferred through the I/O pins
I/O0.about.I/O7 as a command.
[0011] Conventionally, the command comprises 8-bits, such that the
command may be inputted into the memory in one cycle, but the
address comprises more than 8-bits, such that it is needed more
than one cycle to input all the address as shown in the following
Table 1. TABLE-US-00001 TABLE 1 Cycle I/O 0 I/O 1 I/O 2 I/O 3 I/O 4
I/O 5 I/O 6 I/O 7 1st A0 A1 A2 A3 A4 A5 A6 A7 2nd A8 A9 A10 A11 L L
L L 3rd A12 A13 A14 A15 A16 A17 A18 A19 4th A20 A21 A22 A23 A24 A25
A26 A27
[0012] The address A0.about.A11 in Table 1 is a column address for
selecting a column of a memory cell array, and the address
A12.about.A27 is a row address for selecting a raw. In addition,
the signal introduced through the data I/O pins I/O4.about.I/O7 is
usually set to a low level.
[0013] Meanwhile, if the number of the I/O pins is increased to
sixteen and the device operates at a .times.16 speed, data being
inputted or outputted in parallel becomes doubled and the time
(cycles) for processing the same number of data decreases to half.
Therefore, efficiency of inputting/outputting data can be doubled
over .times.8 operation. The following Table 2 describes inputs of
the address when the memory operates at a .times.16 speed.
TABLE-US-00002 TABLE 2 I/O 8.about. Cycle I/O 0 I/O 1 I/O 2 I/O 3
I/O 4 I/O 5 I/O 6 I/O 7 I/O 15 1st A0 A1 A2 A3 A4 A5 A6 A7 L 2nd A8
A9 A10 L L L L L L 3rd A11 A12 A13 A14 A15 A16 A17 A18 L 4th A19
A20 A21 A22 A23 A24 A25 A26 L
[0014] As described in Table 2, even if the number of I/O pins is
16, only 8 pins I/O 0.about.I/O 7 are used for inputting the
address. The I/O pins I/O 8.about.I/O 15 are used only in
inputting/outputting data and usually set to a low level during the
input of address. One (i.e., I/O 3 in second cycle) of the
addresses used in the case of the .times.16 speed operation
decreases compared to the case of the .times.8 speed operation
because the number of data applied in serial decreases to half its
number.
[0015] As explained above, the .times.16 speed memory has double
efficiency compared to the .times.8 speed memory. However, .times.8
or .times.16 memory is selectively used in a process of fabricating
products according to functions and needs of the products
regardless of the input/output efficiency. Therefore, most
enterprises fabricating memories produce both of .times.8 and
.times.16 memories. However, the .times.8 nonvolatile semiconductor
memory and the x 16 nonvolatile semiconductor memory regime
different fabrication processes. Therefore, the fabrication process
may be inefficient.
SUMMARY OF THE INVENTION
[0016] It is therefore an aspect of embodiments of the invention to
provide a nonvolatile semiconductor memory device for selectively
determining the number of data bits inputted or outputted according
to data rate option in one chip, and being capable of controlling
data rate operation of the memory using addresses.
[0017] In accordance with the present invention, a nonvolatile
semiconductor memory device comprises a memory cell array divided
into a plurality of blocks; a data latch circuit for latching a
cell of a predetermined address with respect to each block in the
memory cell array; a data I/O part including a plurality of I/O
pins; a column address register for outputting addresses introduced
from the data I/O part to a column selection circuit according to a
synchronization signal; a data rate option selector for generating
a data rate control signal according to a predetermined speed
option; a block selector for generating a plurality of block
selection signals to select each block of the memory cell array in
response to a predetermined block selection address from the column
addresses register and the data rate control signal; a column
selection circuit for selecting a data line to input or output data
in response to column selection addresses, the block selection
signals and the data rate control signal; a data I/O controller for
selecting a data line to input or output data from/to the column
selection circuit in response to the block selection signals and
the data rate control signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a block diagram showing a conventional .times.8
speed NAND type flash memory.
[0019] FIG. 2 is a block diagram showing a NAND type flash memory
according to the invention having .times.8 or .times.16 data rate
according to a predetermined data rate option.
[0020] FIG. 3 is a circuit diagram showing a column address
register of FIG. 2.
[0021] FIG. 4A is a circuit diagram showing a data rate option
selector of FIG. 2.
[0022] FIG. 4B is a circuit diagram showing another embodiment of
the data rate option selector of FIG. 2.
[0023] FIG. 5 is a circuit diagram showing a block selector of FIG.
2.
[0024] FIG. 6A is a circuit diagram showing a first used in the
column predecoder circuit.
[0025] FIG. 6B is a circuit diagram showing a second predecoder
circuit in FIG. 2. selection circuit of FIG. 2.
[0026] FIG. 7 is a circuit diagram showing a column decoder circuit
used in the column selection circuit of FIG. 2.
[0027] FIG. 8A is a circuit diagram showing a data input circuit of
first and second control circuit of FIG. 2.
[0028] FIG. 8B is a circuit diagram showing a data output circuit
of first and second control circuit of FIG. 2.
[0029] FIG. 9A is a circuit diagram showing a data input circuit of
third control circuit of FIG. 2.
[0030] FIG. 9B is a circuit diagram showing a data output circuit
of the third control circuit of FIG. 2.
DESCRIPTION OF THE EXEMPLARY EMBODIMENT
[0031] The present invention may be embodied in different forms and
should not be construed as limited to the embodiments set forth
herein. Rather, these embodiments are provided so that this
disclosure will be thorough and complete, and will fully convey the
scope of the invention to those skilled in the art.
[0032] FIG. 2 is a block diagram showing a NAND type flash memory
having input/output of .times.8 or .times.16 data rate according to
a predetermined data rate option.
[0033] The NAND type flash memory comprises a memory cell array
200, a row selection circuit 205, a data latch circuit 210, a data
input/output part 240, a column address register 250, a data rate
option selector 270, a block selector 260, a column selection
circuit 220 and a data input/output controller 230. The memory cell
array 200 comprises total four blocks LSB-L, LSB-R, MSB-L and
MSB-R. The row selection circuit 205 is for selecting a row of the
memory cell array 200. The data latch circuit 210 includes
First-Fourth latching circuits for latching data to each of the
memory cell blocks LSB-L, LSB-R, MSB-L and MSB-R. The data
input/output unit 240 includes 16 I/O pins I/O 0.about.I/O 15. The
column address register 250 stores column addresses introduced from
the I/O pins to output sequentially according to synchronization
signals. A data rate option selector 270 generates data rate
control signal X16en for determining the number of data bits
inputted or outputted according to the predetermined data rate
option. The block selector 260 generates four block selection
signals LEFTen, RIGHTen, LSBen and MSBen for selecting each block
of the memory cell array 200 in response to block selection
addresses (AY<j>, AY<i> and 0<j<i-3) from the
column addresses (AY<0>.about.AY<i>) outputted from the
column address register 250 and a data rate control signal
X16en.
[0034] The column selection circuit 220 determines a data line for
a data input/output in response to column selection addresses
(AY<0>.about.AY<i-1> outputted from the column address
register 250 and, a data rate control signal X16en and block
selection signals LEFTen, RIGHTen, LSBen and MSBen from block
selection 260, and outputs data from the data latch circuit to the
selected data line. The data I/O controller 230 selects a data line
for a data input/output between the column selection circuit 220
and the data I/O unit 240 in response to the block selection
signals LEFTen, RIGHTen, LSBen and MSBen and the data rate control
signal X16en. The structure and operation of column selection
circuit 220 and data I/O controller 230 and further explained below
with reference to Figs.
[0035] As shown in FIG. 2, the memory cell array 200 is roughly
divided into an LSB block LSB and an MSB block MSB, and each of the
blocks LSB and MSB are divided into a left block LSB-L and MSB-L
and a right block LSB-R and MSB-R. The data latch circuit 210 is
connected to each of the blocks.
[0036] The data I/O unit 240 including total 16 I/O pins I/O
0.about.I/O 15 uses only 8 pins I/O 0.about.I/O 7 during data
input/output operating at a .times.8 speed and all the 16 pins I/O
0.about.I/O 15 during data input/output operating at a .times.16
speed. The data I/O unit 240, however, uses only 8 pins I/O
0.about.I/O 7 regardless of the data rates .times.8 or .times.16
during address input.
[0037] FIG. 3 is a circuit diagram showing a column address
register 250 of FIG. 2. As illustrated in FIG. 3, the column
address register 250 includes D-flipflops
DFF<0>.about.DFF<i> as many as the number of introduced
initial column addresses Ai<0>.about.Ai<i>, and counts
one by one according to a synchronized signal nRE or nWE inputted
from the data input/output part 240 to output sequentially.
[0038] FIG. 4A is a circuit diagram showing an embodiment of the
data rate option selector 270 of FIG. 2. In the embodiment
illustrated in FIG. 4A, the data rate option selector 270 generates
a data rate control signal X16en for determining a data rate
inputted or outputted according to bonding states of a pad 401 and
a wire 402, and maintains the data rate control signal X16en
generated through the latch circuit 403. If the pad and wire are
bonded, the data rate control signal X16en becomes a high level and
the flash memory of FIG. 2 operates at .times.16 speed. If the pad
and the wire are not bonded, the data rate control signal X16en
becomes a low level and the flash memory operates at .times.8
speed.
[0039] FIG. 4B is a circuit diagram showing another embodiment of
the data rate option selector 270. In the embodiment of FIG. 4B,
the data rate option selector 270 generates a data rate signal
X16en for determining data rate of input/output according to a
state of a fuse 404, and maintains the data rate control signal
X16en generated through a latch circuit 405. If the fuse 404 is cut
off, the data rate control signal X16en becomes a high level by
inverters connected in serial and the flash memory operates at
.times.16 speed. If the fuse 403 is connected, the data rate
control signal X16en becomes a low level and the flash memory
operates at .times.8 speed.
[0040] FIG. 5 is circuit diagram illustrating an embodiment of the
block selector 260 of FIG. 2. As shown in FIG. 5, the block
selector 260 generates block selection signals MSBen, LSBen, LEFTen
and RIGHTen for selecting each block of the cell array 200 in
response to the block selection address AY<j> and AY<i>
and the data rate control signal X16en by a combination of a
plurality of logic circuits. The following Table 3 describes
outputs of the block selector 260 according to each of the signals
AY<j>, AY<i>, X16en and selection blocks in each case.
TABLE-US-00003 TABLE 3 Selection X16en AY<j> AY<i>
LSBen MSBen LEFTen RIGHTen block low Low low high low high low
LSB-L low Low high high low low high LSB-R low High low low high
high low MSB-L low High high low high low high MSB-R high X low
high high high low MSB-L, LSB-L high X high high high low high
MSB-R, LSB-R
[0041] As described in Table 3, if the memory operates at a
.times.16 speed (i.e., the data rate control signal X16en has a
high level), the block selector 260 generates block selection
signals MSBen=high and LSBen=high to select all the LSB and MSB
blocks, and doesn't care when the inputted first block selection
address AY<j>. The block selector 260 generates block
selection signals LEFTen and RIGHTen for selecting left or right
block of the LSB and MSB blocks according to the second block
selection address AY<i>. For example, AY<i> is a low
level, the left blocks of the memory cell (i.e., MSB-L block and
LSB-L block) are selected. If the second block selection address
AY<i> is a high level, the right blocks (i.e., MSB-R and
LSB-R blocks) are selected. In addition, if the memory operates at
.times.8 speed (i.e., the data rate control signal X16en is a low
level), the block selector 260 generates the block selection
signals according to the block selection addresses AY<j> and
AY<i>, as described in Table 3. Therefore, one of the four
blocks in the memory is selected.
[0042] The column selection circuit 220 in FIG. 2 comprises column
selection circuits including column decoder circuits 222, 224, 226
and 228 and column predecoder circuits 221, 223, 225 and 227. In
addition, each of the column predecoder circuit comprises a first
predecoder circuit and a second predecoder circuit.
[0043] FIG. 6A is a circuit diagram showing an embodiment of the
first predecoder circuit of the present invention. FIG. 6B is a
circuit diagram showing an embodiment of the second predecoder
circuit.
[0044] Referring to FIG. 6A, the first predecoder circuit generates
latch signals YA0.about.YA<2i-2-1> for predecoding the column
selection addresses AY<0>.about.AY<i-3> but AY<j>
to input to the column decoder circuits 222, 224, 226 and 228. The
second predecoder circuit, as shown in FIG. 6B, generates gate
control signals YB 0.about.YB 3 for setting data input/output path
of the column decoder circuit according to the gate selection
addresses AY<i-1> and AY<i-2> from column selection
address, block selection signals MSBen or LSBen and LEFTen or
RIGHTen and the data rate control signal X16en.
[0045] Each block of the memory cell array has an independent
column predecoder circuit illustrated in FIGS. 6A and 6B each
having an identical circuit organization. Referring to FIGS. 6A and
6B, if the LSB-L block of the memory cell array 200 is selected
(LSBen=high, LEFTen=high and the rest of the block selection
signals has a low level) when the memory operates at .times.8
speed, a second predecoder circuit of the column predecoder circuit
to the LSB-L block generates gate control signals YB 0.about.YB 3
according to the introduced gate selection addresses AY<i-2>
and AY<i-1>. A first predecoder circuit for the rest of
blocks LSB-R, MSB-L and MSB-R generates gate control signals YB
0.about.YB 3 that have a low level regardless of the gate selection
addresses by the block selection signals.
[0046] FIG. 7 is a circuit diagram illustrating embodiments of the
column decoder circuits 222, 224, 226 and 228. The blocks of the
memory cell array 200 have independent column decoder circuits 222,
224, 226 and 228 respectively, each having an identical circuit
construction corresponding to those of FIGS. 6A and 6B. Each of the
column decoder circuits 222, 224, 226 and 228 outputs the data
latched by the data latch circuit 210 to a data line selected from
the data lines DLA1.about.DLA4 according to the gate control
signals YB 0.about.YB 3 generated by each of the column predecoder
circuit 221, 223, 225 and 227. If all the low gate control signals
YB 0.about.YB 3 are introduced in the column decoder circuit, the
data line is interrupted by a MOS transistor 30 as not to output
data.
[0047] FIG. 8A is a circuit diagram showing an embodiment of data
input circuit 231a in a first control circuit 231. FIG. 8B is a
circuit diagram showing an embodiment of a data output circuit 231b
in the first control circuit 231. The first control circuit 231
includes the data input circuit 231a and the data output circuit
231b that are illustrated in FIGS. 8A and 8B, respectively.
Referring to FIGS. 8A and 8B, the first control circuit 231 inputs
or outputs data through the data line selected by the block
selector 260 according to left or right block selection signals
LEFTen and RIGHTen. Referring to FIG. 8A, the data input circuit
231a of the first control circuit 231 selects data lines DLA1 and
DLA2 being used according to the left or right block selection
signals LEFTen and RIGHTen. If both the left and write block
selection signals LEFTen and RIGHTEn are enabled (i.e., LEFTen=high
and RIGHTen=high), the data DLA<0>.about.DLA<7>
introduced through a data line A DLA are outputted to all data
lines A1 and A2 (DLA1 and DLA2). Moreover, if only the left block
selection signal LEFTen is enabled (i.e., LEFTen=high and
RIGHTen=low), the data line A2 (DLA2) is set to a low level and the
data DLA<0>.about.DLA<7> inputted through the data line
A (DLA) are inputted only through the data line A1 (DLA1).
[0048] Referring to FIG. 8B, the data output circuit 231b of the
first control circuit 231 selects one of the data line A1 (DLA1)
and the data line A2 (DLA2) according to the left block selection
signal LEFTen and outputs data through the data line A DLA. The
second control circuit 232 may be the same as the fully explained
first control circuit 231 in the circuit organization and
operations thereof and will not be further explained herein.
[0049] FIG. 9A is a circuit diagram showing an embodiment of the
data input circuit 233a in a third control circuit 233 of the
present invention. FIG. 9B is a circuit diagram showing a data
output circuit 233b in the third control circuit 233. The third
control circuit 233 includes the data input circuit 233a and the
data output circuit 233b that are illustrated in FIGS. 9A and 9B.
Referring to FIGS. 9A and 9B, the third control circuit 233 inputs
or outputs data through a data line enabled by the block selector
260. Referring to FIG. 9A, when the memory operates at a .times.16
speed (i.e., X16en=high), data lines DLA and DLB are separated form
each other by the data line control circuit 10 including a MOS
transistor and an inverter, and the data
DI/O<0>.about.DI/O<15> are introduced into the memory
through each of the data lines DLA and DLB in a data input circuit
233a of the third control circuit 233. When the memory operates at
a .times.8 speed (i.e., X16en=low), the two data lines DLA and DLB
are connected by the data line control circuit 10 and the data
inputted through 8 backside data I/O pins I/O 8.about.I/O 15 are
interrupted, such that only the data
DI/O<0>.about.DI/O<7> inputted through 8 front side
data I/O pins I/O 0.about.I/O 7 are inputted equally through the
two data lines DLA and DLB. However, one of the data lines DLA and
DLB is interrupted by the above predecoder circuits 221, 223, 225
and 227 and the column decoder circuits 222, 224, 226 and 228 and
the other line is used for inputting data.
[0050] Referring to FIG. 9B, when the data output circuit 233b of
the third control circuit 233 operates at a .times.16 speed (i.e.,
X16en=high, MSBen=high and LSBen=high), the data lines are
separated into two independent data lines
DI/O<0>.about.DI/O<7> and
DI/O<8>.about.DI/O<15> by the first data line control
circuit 30, and each of the data lines
DI/O<0>.about.DI/O<7> and
DI/O<8>.about.DI/O<15> are connected to the data I/O
pins by the second data line control circuit 20 and the third data
line control circuit 40 to output the 16 different data
DI/O<0>.about.DI/O<15> to the data I/O pins I/O
0.about.I/O 15. When the data output circuit 233b operates at
.times.8 speed (i.e., X16en=low), the two data lines DLA and DLB
are connected to each other by the first data line control circuit
30, and 8 data are outputted only through the data line DLA or DLB
selected according to the block selection signals MSBen and LSBen.
For example, if the LSB block is selected (i.e., LSBen=high and
MSBen=low), the data line A (DLA) is connected to the data I/O pin
by the second data line control circuit 20, the data line B (DLB)
is interrupted by the third data line control circuit 40 to output
only the data introduced through the data line A (DLA) to the I/O
pins. Conversely, if the MSB block is selected (i.e., LSBen=low and
MSBen=high), the data line A (DLA) is interrupted by the data line
control circuits 20, 30 and 40 and the data inputted through the
data line B (DLB) are outputted to the pins.
[0051] According to the present invention, the nonvolatile
semiconductor memory device can operate at .times.8 speed or
.times.16 speed depending on options in one chip and control data
input/output with respect to each operation having different data
rate.
[0052] While this invention has been particularly shown and
described with reference to, the preferred embodiments thereof, it
will be understood by those skilled in the art that various changes
in form and details may be made without departing from the spirit
and scope of this invention.
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