Decoupling capacitor for high frequency noise immunity

Abstract

Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the capacitor includes a substrate, a high K dielectric layer doped with nano crystals disposed on the substrate, and a top plate layer disposed on the high K dielectric layer. According to one embodiment, the high K dielectric layer includes Al.sub.2O.sub.3. According to other embodiments, the nano crystals include gold nano crystals and gold nano crystals. One capacitor embodiment includes a MIS (metal-insulator-silicon) capacitor fabricated on silicon substrate, and another capacitor embodiment includes a MIM (metal-insulator-metal) capacitor fabricated between the interconnect layers above silicon substrate. The structure of the capacitor is useful for reducing a resonance impedance and a resonance frequency for an integrated circuit chip. Other aspects are provided herein.

Description

RELATED APPLICATION(S)

[0001] This application is a divisional of U.S. patent application Ser. No. 10/752,351, filed Jan. 6, 2004; which is a divisional of U.S. patent application Ser. No. 09/944,986 filed on Aug. 30, 2001; each of which is incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

[0002] This invention relates generally to integrated circuits and, more particularly, to decoupling capacitors for reducing resonance frequency and impendence in high-frequency chip designs.

BACKGROUND OF THE INVENTION

[0003] Goals for integrated circuit design include progressively scaling the design to achieve smaller feature sizes, and using faster clock frequencies beyond 1 GHz. Problems encountered in achieving these goals include the increasing voltage droop and the inductive noise of the active switching nodes, and further include the increasing power supply oscillations and the resulting noise that is generated and transmitted across the chip.

[0004] These problems are addressed by incorporating on-chip decoupling capacitors into the integrated circuit design. On-chip decoupling capacitors provide a uniform power supply voltage supply (VDD) to fast switching nodes and offset the voltage droops caused by resistive and inductive losses in the integrated circuit load. As such, as will be described in more detail below, on-chip decoupling capacitors reduce .DELTA.I and .DELTA.V noises in CMOS circuits.

[0005] The resonance impedance (Z.sub.RES) of the chip is directly proportional to the inductive component and inversely proportional to the chip RC as represented by the following equation: Z RES .varies. L ( R C + R DC ) + ( C C + C DC ) . ##EQU1## The values R.sub.C and C.sub.C represent the resistance and capacitance of the chip, respectively. The values R.sub.DC and C.sub.DC represent the resistance and capacitance of the decoupling capacitor, respectively. The resonance frequency (F.sub.RES) of the chip is inversely proportional to the square root of L+C as represented by the following equation: F RES .varies. 1 L + ( C C + C DC ) . ##EQU2## The V.sub.DD oscillation and the V.sub.DD noise can be suppressed by a significant and simultaneous lowering of both Z.sub.RES and F.sub.RES.

[0006] Conventionally, on-chip decoupling capacitors are fabricated using silicon dioxide (SiO.sub.2) capacitance in the form of Metal Oxide Silicon (MOS) capacitors. SiO.sub.2 has a low dielectric constant (K.apprxeq.3.9), i.e. a low capacitance per unit area, such that a relatively large amount of silicon area is required for a given capacitance. Thus, the use of SiO.sub.2 adversely affects both density and yield.

[0007] Conventional capacitors that are constructed with defect-free silicon dioxide are characterized as "loss-less" capacitors because, when used as decoupling capacitors, they provide added capacitance to the chip but provide no resistive component. As such, a separate series resistor is often fabricated with conventional on-chip decoupling capacitors to reduce Z.sub.RES.

[0008] It is desirable for a decoupling capacitor to have a controlled and large value of capacitance per unit area, i.e. a high K value, to provide an effective capacitance (C.sub.DC) in a relatively small area and to have a built-in controlled resistance (R.sub.DC) in order to control the resonance impedance and the resonance frequency. Thus, it is desirable to provide controlled and effective "lossy" decoupling capacitor structures and processes that provide a significantly larger value of capacitance per unit area and overcome high frequency design challenges.

[0009] One known on-chip decoupling capacitor that has an adjustable Z.sub.RES includes two thin layers of SiO.sub.2 between a silicon substrate and a doped polysilicon plate, and further includes a thin layer of "injector" quality silicon-rich-nitride (SRN), which is described below, between the two thin layers of SiO.sub.2. For example, a known capacitive device includes an insulating layer of SiO.sub.2 having a thickness of 25 .ANG., an SRN layer having a thickness of 50 to 85 .ANG., and an SiO.sub.2 layer having a thickness of 15 .ANG.. A known process sequence for forming this device includes growing 25 .ANG. of SiO.sub.2 on a silicon substrate. SRN is deposited to a thickness of 50-85 .ANG. using Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD). A Rapid Thermal Anneal (RTA) in O.sub.2 ambient is performed, and the top oxide and SRN layers are patterned and etched such that the SRN layer is left only over N-well regions in the silicon substrate for subsequent capacitor formation. The bottom oxide is removed to form field effect transistor (FET) gate regions and gate oxide is grown. Polysilicon is deposited, doped and patterned to simultaneously form FET gates and the top plate of the capacitor device.

[0010] The above-described known on-chip decoupling capacitor is limited by the scalability of the SiO.sub.2 film thickness, and requires a large silicon area to provide a significant value of capacitance due to the inherently low dielectric constant of SiO.sub.2. Furthermore, even though superior to conventional oxide, this known on-chip decoupling capacitor has a defect, yield and reliability impact similar to thin SiO.sub.2 gate films.

[0011] Therefore, there is a need in the art to provide a system and method that overcomes these problems. The present invention overcomes the above limits of scalability, yield and reliability and provides design solutions for significantly higher frequency ranges, lower voltages, and smaller feature sizes for future generations of integrated circuit design.

SUMMARY OF THE INVENTION

[0012] The above mentioned problems are addressed by the present subject matter and will be understood by reading and studying the following specification. An on-chip decoupling device and method is provided. A resonance impedance and a resonance frequency for an integrated circuit chip are reduced using a lossy decoupling capacitor that has a large capacitance per unit area (high K value) and a built-in controlled resistance. The lossy decoupling capacitor includes a high K dielectric layer doped with nano crystals. The lossy decoupling capacitor has a number of variables that can be manipulated to provide the desired capacitance and resistance for simultaneously lowering the resonance impedance and resonance frequency for the chip. These variables are also capable of being manipulated for scaling purposes in high clock frequency and high speed switching designs.

[0013] One aspect of the present subject matter is a capacitor insulator structure. One embodiment of the capacitor insulator structure includes a high K dielectric layer and nano crystals. The nano crystals are dispersed through the high K dielectric.

[0014] One aspect of the present subject matter is a capacitor. One embodiment of the capacitor includes a substrate, a high K dielectric layer doped with nano crystals disposed on the substrate, and a top plate layer disposed on the high K dielectric layer. According to one embodiment, the high K dielectric layer includes Al.sub.2O.sub.3. According to other embodiments, the nano crystals include gold nano crystals and silicon nano crystals.

[0015] One capacitor embodiment includes a MIS (metal-insulator-silicon) capacitor fabricated on a silicon substrate, and another capacitor embodiment includes a MIM (metal-insulator-metal) capacitor fabricated at lower temperature between the interconnect layers above a silicon substrate. The MIS capacitor directly consumes the silicon area for fabrication of the capacitors, but potentially requires less processing steps when appropriately integrated with the gate insulator processing. The MIM capacitor does not directly impact silicon area and potentially provides a large area for capacitor fabrication. However, the MIM capacitor potentially impacts the number of required interconnect layers which adds mask level and processing cost.

[0016] One aspect of the present subject matter is an integrated circuit. One embodiment of the integrated circuit includes a power source, an integrated circuit load coupled to the power source, and a lossy decoupling capacitor coupled to the integrated circuit load to lower the resonance impedance and the resonance frequency. The integrated circuit load is characterized by a resonance impedance and a resonance frequency, and includes an inductive load, a resistive load, and a capacitive load. The lossy decoupling capacitor has a large capacitance per unit area (high K value) and a built-in controlled resistance. The lossy decoupling capacitor includes a high K dielectric layer doped with nano crystals disposed on a substrate, and a top plate layer disposed on the high K dielectric layer.

[0017] One aspect of the present subject matter provides a method of reducing a resonance impedance and a resonance frequency for an integrated circuit chip. According to one embodiment of this method, a decoupling capacitor is formed by providing a first plate, a second plate, and a dielectric formed from a layer of alumina (Al.sub.2O.sub.3) doped with nano crystals. The decoupling capacitor is coupled to the integrated circuit.

[0018] These and other aspects, embodiments, advantages, and features will become apparent from the following description of the invention and the referenced drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 is a graph showing refractive index of silicon-rich silicon nitride films versus SiH.sub.2Cl.sub.2/NH.sub.3 flow rate ratio.

[0020] FIG. 2 is a graph showing current density versus applied field for silicon-rich silicon nitride films having different percentages of excess silicon.

[0021] FIG. 3 is a graph showing apparent dielectric constant K versus refractive index for both silicon rich nitride (SRN) and silicon rich oxide (SRO).

[0022] FIG. 4 is a lumped model illustrating the resistive and inductive losses for an integrated circuit.

[0023] FIG. 5 is another model of the electrical behavior for an integrated circuit.

[0024] FIG. 6 is the integrated circuit model of FIG. 7 with a lossy decoupling capacitor.

[0025] FIG. 7 is a schematic for an on-chip decoupling device.

[0026] FIG. 8 illustrates one embodiment of a metal-insulator-silicon (MIS) capacitor formed over an n silicon substrate or an n-well.

[0027] FIG. 9 illustrates another embodiment of a MIS capacitor formed over an n silicon substrate or an n-well.

[0028] FIG. 10 illustrates another embodiment of a MIS capacitor formed over an p silicon substrate or a p-well.

[0029] FIG. 11 illustrates another embodiment of a MIS capacitor formed over an p silicon substrate or a p-well.

[0030] FIG. 12 illustrates one embodiment of a MIS capacitor with a metal top plate.

[0031] FIG. 13 illustrates another embodiment of a MIS capacitor with a metal top plate.

[0032] FIG. 14 illustrates one embodiment of a metal-insulator-metal (MIM) capacitor with gold nano crystals.

[0033] FIG. 15 illustrates another embodiment of a MIM capacitor with silicon nano crystals.

DETAILED DESCRIPTION OF THE INVENTION

[0034] The following detailed description of the invention refers to the accompanying drawings which show, by way of illustration, specific aspects and embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0035] Silicon-rich nitride (SRN), or more particularly, injector SRN was referenced in the Background of the Invention. SRN is a subset of silicon rich insulator (SRI). Another subset of SRI is silicon rich oxide (SRO), or more particularly, injector SRO. FIGS. 1-3, described below, are included to elaborate on the characteristics of SRN, including injector SRI.

[0036] FIG. 1 is a graph showing refractive index of silicon-rich silicon nitride films versus SiH.sub.2Cl.sub.2/NH.sub.3 flow rate ratio (R). This figure is provided herein to illustrate the known relationship between the silicon amount and the refractive index in the film. The graph indicates that the index of refraction increases linearly with increasing silicon content. As such, the index of refraction of the films can be used as an indication of the silicon content of the films.

[0037] FIG. 2 is a graph showing current density versus applied field for silicon-rich silicon nitride films having different percentages of excess silicon. The current density (J) is represented in amperes/cm.sup.2, and log J is plotted against the electric field E (volts/cm) for Si.sub.3N.sub.4 layers having a SiH.sub.2Cl.sub.2NH.sub.3 flow rate ratio R of 0.1, 3, 5, 10, 15 and 31. This figure is provided herein to illustrate the known relationship between the amount of silicon and the conductivity of the film. The plot shows that the Si.sub.3N.sub.4 layers having small additions of silicon (R=3 and 5) exhibit a relatively small conductivity increase over stoichiometric Si.sub.3N.sub.4. The plot further shows that increasing silicon content at or above R=10 substantially increases or enhances the conductivity.

[0038] Silicon-rich nitride films having an R greater than 10 (or, more specifically, having an index of refraction greater than 2.3) are referred to as an injector medium. A silicon-rich Si.sub.3N.sub.4 (SRN) injector provides appreciably enhanced charge conductance without providing significant charge trapping similar to the characteristics of semi-metals.

[0039] Silicon nitride injectors are preferred over silicon oxide injectors because the two-phase nature of the interface is believed to provide a localized electric field distortion and an associated high current. At elevated processing temperature, silicon readily diffuses within silicon oxide and changes the size and geometry of silicon crystals, which disrupts the injection threshold by reducing the localized field distortions. However, silicon does not readily diffuse within Si.sub.3N.sub.4. Furthermore, SRN is chemically passive against chemical solutions as well as an effective barrier against n or p type dopant diffusion; that is, against phosphorus or boron respectively.

[0040] FIG. 3 is a graph showing apparent dielectric constant K versus refractive index for both silicon rich nitride (SRN) and silicon rich oxide (SRO). The SRN and SRO plotted in this graph were provided using a Low Pressure Chemical Vapor Deposition (LPCVD) process. The SRO was fabricated at approximately 680.degree. C., and the fabricated structure included 100 .ANG. oxide and 150 .ANG. SRO. The SRN was fabricated at approximately 770.degree. C., and the fabricated structure included 45 .ANG. oxide and 80 .ANG. SRO. As shown in the graph, the dielectric constant of silicon is around 12. Materials with a higher K than silicon are conventionally termed a high K material, and materials with a lower K than silicon are conventionally termed a low K material. Injector SRN are those that have a refractive index of 2.5 or greater and injector SRO are those that have a refractive index of 1.85 or greater. Injector SRN and injector SRO have apparent dielectric constants that are greater than 12. Injector SRI includes both high K SRO and high K SRN.

[0041] Thus, as illustrated by FIGS. 1-3, injector SRN provides enhanced charge conductance. Controlling the dispersion and amount of silicon in injector SRN controls the resistivity of the film in which the injector SRN is deposited.

[0042] FIG. 4 is a lumped model illustrating the resistive and inductive losses for an integrated circuit. The model includes a power source 410 and an integrated circuit load 412. The power source 410 is represented by both a voltage source 414 and a current source 416. The integrated circuit load 412 has a resistive component 418, an inductive component 420, and a capacitive component 422. These are represented in this model as a lumped resistance, a lumped inductor and a lumped capacitor connected in series. The lumped resistance contributes to signal loss as represented by .DELTA.V.sub.R. The lumped inductor also contributes to signal loss as represented by .DELTA.V.sub.L.

[0043] FIG. 5 is another model of the electrical behavior for an integrated circuit. This model also includes a power source 510 and an integrated circuit load 512. The power source 510 is represented by both a voltage source 514 and a current source 516. The integrated circuit load 512 has a resistive component 518, an inductive component 520, and a capacitive component 522. The resistive component 518 is attributable to the resistance of the chip/substrate. The inductive component 520 is attributable to the inductance in the substrate and interconnect. In this model, the resistive component and capacitive component are connected in series with each other, and are connected in parallel with the inductive component.

[0044] FIG. 6 is the integrated circuit model of FIG. 5 with a lossy decoupling capacitor. The lossy decoupling capacitor 624 is coupled in parallel with the chip capacitive component 622 of the integrated circuit load 612. The model for the lossy decoupling capacitor 624 includes a decoupling capacitor (C.sub.DC) 626 coupled in parallel with a decoupling resistor (R.sub.DC) 628. As provided earlier, increasing C.sub.DC and R.sub.DC lowers the resonance impedance (Z.sub.RES) and the resonance frequency (F.sub.RES) and suppresses the V.sub.DD oscillation and the V.sub.DD noise.

[0045] FIG. 7 is a schematic for an on-chip decoupling device according to the present subject matter. A substrate 730 is provided with isolation regions 732. Control devices 734 are formed between isolation regions 732. Each control device 734 includes a gate 736 and two diffused regions 738 in the substrate 730. A gate insulator 740 separates the gate 736 from the diffused regions 738. An n-well 742 is formed between the two control devices 734. A decoupling capacitor plate 744 is formed over the n-well, and is separated from the n-well by a capacitor insulator structure 746. This capacitor insulator structure 746 provides the characteristics for the lossy decoupling capacitor. According to one embodiment, the fabrication of the insulator structure 746 is integrated with the processing of the gate insulator 740 of the control devices 734.

[0046] There are a number of variables that may be manipulated during the fabrication of the decoupling capacitor to achieve the desired values for the resistive and capacitive component (R.sub.DC and C.sub.DC) of the decoupling capacitor. One of these manipulated variables, as taught by the present subject matter, is the K value of the dielectric used in the capacitor insulator structure 746. Other manipulated variables taught by the present subject matter include the distribution of nano crystals in the capacitor insulator structure 746 and the composition of the nano crystals. The nano crystals control the resistivity of the high K dielectric. Those of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to manipulate these and other variables to achieve the desired R.sub.DC and C.sub.DC for a decoupling capacitor.

[0047] FIG. 8-13 illustrate various embodiments of a MIS (metal-insulator-substrate) capacitor. The gate oxide for the capacitor insulator structure is a high K dielectric containing tailored amounts of nano crystals. According to various embodiments, these nano crystals are uniformly distributed or dispersed in the high K dielectric. According to one embodiment, the high K dielectric includes alumina (Al.sub.2O.sub.3). In one embodiment, silicon or gold nano crystals are uniformly distributed in Al.sub.2O.sub.3 by simultaneous sputtering, by implant, by ion-beam deposition or by vapor phase deposition. In one embodiment, silicon-rich alumina is deposited by chemical vapor deposition (CVD) technique to create a two phase insulator consisting of desired silicon nano crystals uniformly dispersed in Al.sub.2O.sub.3.

[0048] If the capacitor plate is a silicon plate, the insulator is capped with a thin (5 nm, for example) layer of injector SRN which adds an increased resistive component with negligible impact on capacitance. This is because, as was stated above, injector SRN provides appreciably enhanced charge conductance without providing appreciably enhanced charge trapping. Additionally, the injector SRN layer prevents dopant and impurity migration during subsequent high temperature processing. If the capacitor plate is a metal plate, one embodiment provides a thin layer of titanium nitride (TiN) to provide a diffusion barrier between the insulator and the metal interface. One embodiment uses the TiN layer as the top plate of the capacitor.

[0049] According to various embodiments, the capacitance of the decoupling capacitor is further enhanced by doping transition metals into the high K dielectric material. These transition metals include, but are not limited to, hafnium (Hf), tantalum (Ta), zirconium (Zr), and praseodymium (Pr). Additionally, a complex high K dielectric is used as the dielectric for the capacitor, or is doped with the high K dielectric for the capacitor. One such complex high K dielectric is barium strontium titanate ((BaSr) TiO.sub.3) which is also known as BST. Other complex high K dielectrics include, but are not limited to, tantalum pentoxide (Ta.sub.2O.sub.5), titanium dioxide (TiO.sub.2), tantalum nitride (TaN), zirconium oxide (ZrO.sub.2) which is also known as zirconia, and praseodymium oxide (Pr.sub.2O.sub.3).

[0050] FIG. 8 illustrates one embodiment of a MIS capacitor formed over an n silicon substrate or an n-well. According to this embodiment, a layer 850 of gold-doped Al.sub.2O.sub.3 is disposed on the substrate 830 and functions as the capacitor insulator structure 846. Gold-doped Al.sub.2O.sub.3 is Al.sub.2O.sub.3 doped with gold nano crystals. An injector layer 852, such as an injector SRN layer, is disposed on the gold-doped Al.sub.2O.sub.3. The top plate 844 of the capacitor is formed from n+ polysilicon.

[0051] FIG. 9 illustrates another embodiment of a MIS capacitor formed over an n silicon substrate or an n-well. According to this embodiment, a layer 950 of silicon-doped Al.sub.2O.sub.3 is disposed on the substrate 930 and functions as the capacitor insulator structure 946. Silicon-doped Al.sub.2O.sub.3 is Al.sub.2O.sub.3 doped with silicon nano crystals. An injector layer 952, such as an injector SRN layer, is disposed on the silicon-doped Al.sub.2O.sub.3. The top plate 944 of the capacitor is formed from n+ polysilicon.

[0052] FIG. 10 illustrates another embodiment of a MIS capacitor formed over an p silicon substrate or a p-well. According to this embodiment, a layer 1050 of gold-doped Al.sub.2O.sub.3 is disposed on the substrate 1030 and functions as the capacitor insulator structure 1046. An injector layer 1052, such as an injector SRN layer, is disposed on the gold-doped Al.sub.2O.sub.3. The top plate 1044 of the capacitor is formed from p+ polysilicon.

[0053] FIG. 11 illustrates another embodiment of a MIS capacitor formed over an p silicon substrate or a p-well. According to this embodiment, a layer 1150 of silicon-doped Al.sub.2O.sub.3 is disposed on the substrate 1130 and functions as the capacitor insulator structure 1146. An injector layer 1152, such as an injector SRN layer, is disposed on the silicon-doped Al.sub.2O.sub.3. The top plate 1144 of the capacitor is formed from p+ polysilicon.

[0054] FIG. 12 illustrates one embodiment of a MIS capacitor with a metal top plate. According to this embodiment, a layer 1250 of gold-doped Al.sub.2O.sub.3 is disposed on the substrate 1230, and a TiN layer 1254 is disposed thereon. According to another embodiment, a layer 1250 of silicon-doped Al.sub.2O.sub.3 is disposed on the substrate 1230, and a TiN layer 1254 is disposed thereon. The top plate 1244 of the capacitor is formed from a metal.

[0055] FIG. 13 illustrates another embodiment of a MIS capacitor with a metal top plate. According to this embodiment, a layer 1350 of gold-doped Al.sub.2O.sub.3 is disposed on the substrate 1330, and a TiN layer 1354 is disposed thereon. According to another embodiment, a layer 1350 of silicon-doped Al.sub.2O.sub.3 is disposed on the substrate 1330, and a TiN layer 1354 is disposed thereon. The TiN 1354 layer forms the top plate 1344 of the capacitor.

[0056] FIGS. 14-15 illustrate various embodiments of a MIM (metal-insulator-metal) capacitor. According to various embodiments, the MIM capacitor is fabricated on top of silicon and is appropriately connected to the VDD/Gnd nodes, clock trees and active circuits. The insulator is a high K dielectric containing tailored amounts of nano crystals uniformly distributed or dispersed in the high K dielectric. Such insulator is usually fabricated at lower temperature than corresponding MIS options. The techniques used for fabrication include electron cyclotron resonance-plasma enhanced chemical vapor deposition (ECR-PECVD), atomic layer deposition (ALD), sputtering, E-Beam and Ion-Beam deposition of thin films.

[0057] According to one embodiment, the high K dielectric includes Al.sub.2O.sub.3. In one embodiment, ALD aluminum is deposited on top of a tungsten nitride (TiN), a tungsten (W) or tungsten silicide (WSi) electrode and subsequently oxidized in ozone plasma at low temperature. In one embodiment, silicon or gold nano crystals are uniformly distributed in Al.sub.2O.sub.3 by simultaneous sputtering, or by implant, or by vapor phase deposition. In one embodiment, silicon-rich alumina is deposited by CVD technique to create two phase insulator consisting of desired silicon nano crystals uniformly dispersed in Al.sub.2O.sub.3. According to various embodiments, the metal top plate is any metal such as titanium nitride (TiN), copper (Cu) or aluminum (Al).

[0058] According to various embodiments, the capacitance of the decoupling capacitor is further enhanced by doping transition metals into the high K dielectric such as Al.sub.2O.sub.3. These transition metals include, but are not limited to, hafnium (Hf), tantalum (Ta), zirconium (Zr), praseodymium (Pr). Additionally, a complex high K dielectric is used as the dielectric for the capacitor, or is doped with the high K dielectric for the capacitor. One such complex high K dielectric is barium strontium titanate ((BaSr) TiO.sub.3) which is also known as BST. Other complex high K dielectrics include, but are not limited to, tantalum pentoxide (Ta.sub.2O.sub.5), titanium dioxide (TiO.sub.2), tantalum nitride (TaN), zirconium oxide(ZrO.sub.2) also known as zirconia, and praseodymium oxide (Pr.sub.2O.sub.3).

[0059] FIG. 14 illustrates one embodiment of a MIM capacitor with gold nano crystals. According to this embodiment, a first layer 1462 of TiN is disposed on the bottom metal layer 1460, a layer 1450 of gold-doped Al.sub.2O.sub.3 is disposed on the first layer of TiN 1462, a second layer 1444 of TiN is disposed on the layer 1450 of gold-doped Al.sub.2O.sub.3, and a top plate 1444 is formed on the second layer 1444 of TiN. According to various embodiments, the top plate is fabricated from titanium nitride (TiN), copper (Cu), tungsten (W) or aluminum (Al) and the bottom metal layer is fabricated from Cu, W, Al, TiN, or tungsten silicide (WSi).

[0060] FIG. 15 illustrates another embodiment of a MIM capacitor with silicon nano crystals. According to this embodiment, a first layer of TiN 1562 is disposed on the bottom metal layer 1560, a layer 1550 of silicon-doped Al.sub.2O.sub.3 is disposed on the first layer 1562 of TiN, a second layer 1564 of TiN is disposed on the layer 1550 of gold-doped Al.sub.2O.sub.3, and a top plate 1544 is formed on the second layer 1544 of TiN. According to various embodiments, the top plate is fabricated from TiN, Cu, W or Al and the bottom metal layer is fabricated from Cu, W, Al, TiN, or WSi.

[0061] Injector SRN was provided as an example of an injector medium in the above examples. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that other materials may be used as an injector medium. These materials include silicon-rich aluminum nitride and SRO. Al.sub.2O.sub.3 is not an effective diffusion barrier for certain dopants like phosphorus for an n+ gate. The injector media SRN and silicon-rich aluminum nitride function as a diffusion barrier for doped polysilicon gates to prevent phosphorous, for example, from diffusing into Al.sub.2O.sub.3. A diffusion barrier is not needed if a metal gate is used.

[0062] Al.sub.2O.sub.3 was provided as an example of a high K charge blocking medium in the above examples. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that other materials may be used as a high K charge medium. A high K charge medium is a material that has a K greater than the K of silicon. These materials include oxides, nitrides and silicates of tantalum, titanium, zirconium, hafnium and praseodymium. Additionally, these materials may further be doped with complex high K dielectrics such as barium strontium titanate (BST), transition metal, and metal oxides such as tantalum pentoxide (Ta.sub.2O.sub.5), titanium dioxide (TiO.sub.2), tantalum nitride (TaN), zirconium oxide (ZrO.sub.2), and praseodymium oxide (Pr.sub.2O.sub.3). Furthermore, thin films of these materials can be readily fabricated at near room temperature or at low temperature by several techniques including sputtering, ion beam deposition, and electron cyclotron resonance-plasma enhanced chemical vapor deposition (ECR-PECVD).

[0063] One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how the characteristics of these materials provide a number of variables that are capable of being manipulated to achieve the desired characteristics for the decoupling capacitor. That is, one of ordinary skill in the art will understand how to provide design solutions for significantly higher frequency ranges, lower voltages, and smaller feature sizes for future generations of integrated circuit design.

[0064] Furthermore, one of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to incorporate the decoupling capacitor into various integrated circuit designs for various components in a larger electronic system. Such an electronic system includes a processor or arithmetic/logic unit (ALU), a control unit, a memory device unit and an input/output (I/O) device. Generally, such an electronic system will have a native set of instructions that specify operations to be performed on data by the processor and other interactions between te processor, the memory device unit and the I/O devices. The memory device unit contains the data plus a stored list of instructions. The control unit coordinates all operations of the processor, the memory device and the I/O devices by continuously cycling through a set of operations that cause instructions to be fetched from the memory device and executed.

[0065] The figures presented and described in detail above are similarly useful in describing the method aspects of the present subject matter. One of ordinary skill in the art will understand these methods upon reading and comprehending this disclosure.

CONCLUSION

[0066] The present subject matter provides a decoupling capacitor for reducing resonance frequency and impedance in high frequency designs. The capacitor insulator structure of the decoupling capacitor includes a high K dielectric, and nano crystals dispersed through the high K dielectric. The distribution of the nano crystals and the composition of the nano crystals control the resistivity of the high K dielectric. Thus, the capacitor insulator structure provides a decoupling capacitor with a high K to provide an effective C.sub.DC in a relatively small area and with a built-in controlled R.sub.DC to control the resonance impedance and the resonance frequency of an integrated circuit chip. As such, smaller and faster integrate circuit design are achieved.

[0067] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A method, comprising: applying a voltage across a high K dielectric, and controlling conductance through the high K dielectric using a tailored amount of nano crystals uniformly dispersed in the high K dielectric.

2. The method of claim 1, wherein applying a voltage across a high K dielectric includes applying a voltage across alumina (Al.sub.2O.sub.3).

3. The method of claim 1, wherein controlling conductance through the high K dielectric includes using a tailored amount of gold nano crystals uniformly dispersed in the high K dielectric to provide a controlled resistance.

4. The method of claim 1, wherein controlling conductance through the high K dielectric includes using a tailored amount of silver nano crystals uniformly dispersed in the high K dielectric to provide a controlled resistance.

5. The method of claim 1, wherein applying a voltage across a high K dielectric includes applying a voltage across a dielectric selected from the group consisting of: a tantalum oxide, a titanium oxide, a tantalum nitride, a tantalum silicate, a zirconium oxide, a zirconium nitride, a zirconium silicate, a hafnium oxide, a hafnium nitride, a hafnium silicate, a praseodymium oxide, a praseodymium nitride and a praseodymium silicate.

6. The method of claim 5, wherein applying a voltage across a high K dielectric includes applying a voltage across a high K dielectric doped with a complex high K dielectric selected from the group consisting of: barium strontium titanate (BST), a transition metal, and a metal oxide.

7. The method of claim 6, wherein the metal oxide is selected from the group consisting of a tantalum oxide, a zirconium oxide and a praseodymium oxide.

8. The method of claim 1, wherein applying a voltage further comprises applying a potential to a titanium nitride layer in contact with the aluminum oxide layer.

9. The method of claim 8, wherein applying a potential to a titanium nitride layer includes applying a potential to a metal layer in contact with the titanium nitride layer.

10. The method of claim 1, wherein applying a voltage further comprises applying a potential to a silicon rich nitride layer in contact with the aluminum oxide layer.

11. The method of claim 10, wherein applying a potential to a silicon rich nitride layer includes applying a potential to a polysilicon layer in contact with the silicon rich nitride layer.

12. A method, comprising: applying a voltage across an aluminum oxide dielectric layer; and controlling conductance through the aluminum oxide layer to provide a controlled resistance using a tailored amount of gold nano crystals uniformly dispersed in the aluminum oxide layer.

13. The method of claim 12, wherein applying a voltage further comprises applying a potential to a titanium nitride layer in contact with the aluminum oxide layer.

14. The method of claim 13, wherein applying a potential to a titanium nitride layer includes applying a potential to a metal layer in contact with the titanium nitride layer.

15. The method of claim 12, wherein applying a voltage further comprises applying a potential to a silicon rich nitride layer in contact with the aluminum oxide layer.

16. The method of claim 12, wherein applying a potential to a silicon rich nitride layer includes applying a potential to a polysilicon layer in contact with the silicon rich nitride layer.

17. A method, comprising: applying a voltage across an aluminum oxide dielectric layer; and controlling conductance through the aluminum oxide layer to provide a controlled resistance using a tailored amount of silicon nano crystals uniformly dispersed in the aluminum oxide layer.

18. The method of claim 17, wherein applying a voltage further comprises applying a potential to a titanium nitride layer in contact with the aluminum oxide layer.

19. The method of claim 18, wherein applying a potential to a titanium nitride layer includes applying a potential to a metal layer in contact with the titanium nitride layer.

20. The method of claim 17, wherein applying a voltage further comprises applying a potential to a silicon rich nitride layer in contact with the aluminum oxide layer.

21. The method of claim 17, wherein applying a potential to a silicon rich nitride layer includes applying a potential to a polysilicon layer in contact with the silicon rich nitride layer.

22. A method, comprising: reducing a resonance frequency and a resonance impedance for an integrated circuit chip, including applying a voltage across a lossy capacitor coupled to an integrated circuit load; wherein applying a voltage across a lossy capacitor includes: applying a voltage across a high K dielectric, and controlling conductance through the high K dielectric to provide a controlled resistance using a tailored amount of nano crystals uniformly dispersed in the high K dielectric.

23. The method of claim 22, wherein the high K dielectric includes an aluminum oxide.

24. The method of claim 22, wherein the high K dielectric includes a tantalum oxide.

25. The method of claim 22, wherein the high K dielectric includes a titanium oxide.

26. The method of claim 22, wherein the high K dielectric includes a tantalum nitride.

27. The method of claim 22, wherein the high K dielectric includes a tantalum silicate.

28. The method of claim 22, wherein the high K dielectric includes a zirconium oxide.

29. The method of claim 22, wherein the high K dielectric includes a zirconium nitride.

30. The method of claim 22, wherein the high K dielectric includes a zirconium silicate.

31. The method of claim 22, wherein the high K dielectric includes a hafnium oxide.

32. The method of claim 22, wherein the high K dielectric includes a hafnium nitride.

33. The method of claim 22, wherein the high K dielectric includes a hafnium silicate.

34. The method of claim 22, wherein the high K dielectric includes a praseodymium oxide.

35. The method of claim 22, wherein the high K dielectric includes a praseodymium nitride.

36. The method of claim 22, wherein the high K dielectric includes a praseodymium silicate.

37. The method of claim 22, wherein the nano crystals include gold nano crystals.

38. The method of claim 22, wherein the nano crystals include silicon nano crystals.

39. An integrated circuit, comprising: an integrated circuit load; means for applying a voltage across a high K dielectric connected to the integrated circuit load to lower a resonance impedance and a resonance frequency of the integrated circuit; and means for controlling conductance through the high K dielectric using a tailored amount of nano crystals uniformly dispersed in the high K dielectric to lower the resonance impedance.

40. The integrated circuit of claim 39, wherein the high K dielectric includes aluminum oxide and the nano crystals include silicon nano crystals.

41. The integrated circuit of claim 39, wherein the high K dielectric includes aluminum oxide and the nano crystals include gold nano crystals.

42. The integrated circuit of claim 39, wherein the high K dielectric includes a dielectric selected from the group consisting of: a tantalum oxide, a titanium oxide, a tantalum nitride, a tantalum silicate, a zirconium oxide, a zirconium nitride, a zirconium silicate, a hafnium oxide, a hafnium nitride, a hafnium silicate, a praseodymium oxide, a praseodymium nitride and a praseodymium silicate.

43. The integrated circuit of claim 42, wherein the high K dielectric is doped with a complex high K dielectric selected from the group consisting of: barium strontium titanate (BST), a transition metal, and a metal oxide.

44. The integrated circuit of claim 43, wherein the metal oxide is selected from the group consisting of a tantalum oxide, a zirconium oxide and a praseodymium oxide.