U.S. patent application number 11/223369 was filed with the patent office on 2006-01-12 for image composing system and a method thereof.
Invention is credited to Shigeru Muraki, Masato Ogata.
Application Number | 20060007245 11/223369 |
Document ID | / |
Family ID | 29243824 |
Filed Date | 2006-01-12 |
United States Patent
Application |
20060007245 |
Kind Code |
A1 |
Muraki; Shigeru ; et
al. |
January 12, 2006 |
Image composing system and a method thereof
Abstract
The present invention provides an image composing apparatus that
can composite images at high speed and in which the apparatus
configuration can be easily expanded as the number of images to be
composed increases. Sub-images generated by node computers are
synchronized each other by a synchronizing section. Then, each pair
of synchronized sub-image data is composed into a single sub-image
in a first-layer image composing section, comprising a plurality of
image composing circuits each for composing two sub-images, and the
resulting sub-images are composed iteratively through a
second-layer image composing section, a third-layer image composing
section, and so on, that have the same configuration as the
first-layer image composing section.
Inventors: |
Muraki; Shigeru; (Tokyo,
JP) ; Ogata; Masato; (Kamakura-shi, JP) |
Correspondence
Address: |
CHRISTIE, PARKER & HALE, LLP
PO BOX 7068
PASADENA
CA
91109-7068
US
|
Family ID: |
29243824 |
Appl. No.: |
11/223369 |
Filed: |
September 9, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10291854 |
Nov 8, 2002 |
6956585 |
|
|
11223369 |
Sep 9, 2005 |
|
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Current U.S.
Class: |
345/619 |
Current CPC
Class: |
G06T 1/20 20130101 |
Class at
Publication: |
345/619 |
International
Class: |
G09G 5/00 20060101
G09G005/00 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 26, 2002 |
JP |
2002-126952 |
Claims
1. An image composing apparatus for merging a plurality of subspace
images into a single image, comprising: a subspace image input
means for receiving said plurality of subspace images via a
plurality of subspace image transmitting lines in parallel; a
synchronizing means for synchronizing said plurality of subspace
images received at said subspace image input means; and an image
merging means for processing said plurality of subspace images
synchronized by said synchronizing means in parallel to merge said
plurality of subspace images into a single image.
2. An image composing apparatus as claimed in claim 1, wherein said
synchronizing means comprises: a plurality of FIFO memories for
storing said plurality of subspace images and outputting said
stored subspace images in the order in which said subspace images
were stored; and a control means for generating an instruction that
causes said plurality of FIFO memories to output said stored
subspace images in the order in which said subspace images were
stored when a head of a last one of said subspace images arrives at
one of said FIFO memories.
3. An image composing apparatus as claimed in claim 1, wherein said
subspace image merging means merges said plurality of subspace
images based on priorities indicating an occlusion relationship
between said plurality of subspace images.
4. An image composing apparatus as claimed in claim 3, wherein said
priorities are expressed in a form of a binary space-partitioning
tree.
5. An image composing apparatus as claimed in claim 3, wherein said
subspace images respectively include data indicating said
priorities for every frame.
6. An image composing method for merging a plurality of subspace
images into a single image, comprising: a subspace image input step
for receiving said plurality of subspace images via a plurality of
subspace image transmitting lines in parallel; a synchronizing step
for synchronizing said plurality of subspace images received at
said subspace image input step; and an image merging step for
processing said plurality of subspace images synchronized at said
synchronizing step in parallel to merge said plurality of subspace
images into a single image.
7. An image composing method as claimed in claim 6, wherein said
synchronizing step comprises: a FIFO storing step for storing said
plurality of subspace images and outputting said stored subspace
images in the order in which said subspace images were stored; and
a FIFO output step for generating an instruction that causes
outputs of said plurality of subspace images stored at said FIFO
storing step in the order in which said subspace images were stored
when a head of a last one of said subspace images arrives.
8. An image composing method as claimed in claim 6, wherein at said
subspace image merging step, said plurality of subspace images are
merged based on priorities indicating an occlusion relationship
between said plurality of subspace images.
9. An image composing method as claimed in claim 8, wherein said
priorities are expressed in a form of a binary space-partitioning
tree.
10. An image composing method as claimed in claim 8, wherein said
subspace images respectively include data indicating said
priorities for every frame.
Description
CROSS REFERENCE TO RELATED APPLICATION(S)
[0001] This application is a divisional of U.S. application Ser.
No. 10/291,854, filed Nov. 8, 2002, which claims priority of
Japanese patent application number 2002-126952, filed on Apr. 26,
2002, priority of which are claimed herein.
TECHNICAL FIELD OF THE INVENTION
[0002] The present invention relates to an image composing
apparatus and method, and more particularly an image composing
apparatus and method that can compose images at high speed and in
which the apparatus configuration can easily be expanded in
proportion to the number of images to be composed.
PRIOR ART
[0003] To intuitively grasp the results of computer processing, the
results must be presented in visible form. However, as the scale of
processing becomes larger, it becomes difficult to generate
necessary images using a single computer. Therefore, it is often
practiced to compose images using a plurality of computers.
[0004] FIG. 1 is a block diagram of an image composing apparatus
proposed in the prior art, which comprises N node computers
F.sub.1, F.sub.2 . . . F.sub.n and an N.times.N crossbar switch S
for enabling the N node computers F.sub.1, F.sub.2 . . . F.sub.N to
communicate with each other.
[0005] Each of image composing boards C.sub.1, C.sub.2 . . .
C.sub.N which are dedicated cards for composing images, is
connected to a PCI bus on each node computer F.sub.n, and each of
the image composing boards C.sub.1, C.sub.2 . . . C.sub.N are
connected to each other via the crossbar switch S.
[0006] In the image composing apparatus having the above
configuration, the image composing board C.sub.n on one node
computer F.sub.n composites an image generated in itself with an
image generated in the image composing board C.sub.m (m.apprxeq.n)
on another node computer F.sub.m, and the composed image is
transferred to the third node computer F.sub.k via the crossbar
switch S. This process is repeated till a final image is
generated.
[0007] The above image composing apparatus uses a method in which
the images generated by separate node computers are composed
together based on a parameter called "Z value" that denotes an
image composing order. Though the apparatus can respond flexibly to
increasing the number of node computers, it involves following
problems.
[0008] (1) The Z value denoting the depth from a viewpoint must be
added for data of each pixel, but since the Z value must be highly
accurate compared with other information (red component R, green
component G, blue component B, and transparency .alpha.), adding
the Z value almost doubles the number of bits in the image data,
and the amount of image data to be transmitted increases.
[0009] (2) To avoid collisions during transferring image data, a
waiting time is necessary, and this waiting time increases the time
required for transferring image data.
[0010] (3) In order to reduce the image data transferring time, the
hardware configuration must be increased, because the crossbar
switch, for example, should be specially designed to match with
each node computer.
[0011] Therefore, in the above image composing apparatus, when the
number of node computers is increased.
[0012] (1) The scale of the crossbar switch may exceed the
practically feasible scale as it increases as the square of the
number of node computers.
[0013] (2) If the number of node computers is limited to the
practically feasible number, the time required for establishing
synchronization between the images to be composed increases, and an
image composing time increases.
SUMMARY OF THE INVENTION
[0014] The present invention has been devised in view of the above
problems and an object of the invention is to provide an image
composing apparatus and method that can compose images at high
speed and in which the apparatus configuration can be easily
expanded as the number of images to be composed increases.
[0015] According to an image composing apparatus and method of a
first invention, N (2.ltoreq.N) sub-images are merged into a single
image based on an occlusion relationship between the N
sub-images.
[0016] According to an image composing apparatus and method of a
second invention, the occlusion relationship is expressed in the
form of a binary space-partitioning tree.
[0017] According to an image composing apparatus and method of a
third invention, input sub-images are composed to generate an
output sub-image by iteratively composing two sub-images into one
image based on the occlusion relationship between two
sub-images.
[0018] According to an image composing apparatus and method of a
fourth invention, the two sub-image composing process compares
priorities which denote the occlusion relationship between the two
sub-images, and generates a composed image based on the result of
the priority comparison by composing one sub-image which is defined
as a first sub-image with another sub-image which is defined a
second sub-image.
[0019] According to an image composing apparatus and method of a
fifth invention, the two sub-images are composed together in
accordance with the following equation. I .times. .times. ( R , G ,
B ) M = I .times. .times. ( R , G , B ) 1 * I .function. ( .alpha.
) 1 + I .times. .times. ( R , G , B ) 2 I .times. .times. ( .alpha.
) M = I .times. .times. ( .alpha. ) 1 * I .times. .times. ( .alpha.
) 2 ##EQU1## Where I(R,G,B).sub.M are the RGB components of the
composed image, I(R,G,B).sub.1 are the RGB components of the first
sub-image, I(R,G,B).sub.2 are the RGB components of the second
sub-image, I(.alpha.).sub.M is the transparency of the merged
image, I(.alpha.).sub.1 is the transparency of the first sub-image,
and I(.alpha.).sub.2 is the transparency of the second
sub-image.
[0020] According to an image composing apparatus and method of a
sixth invention, the sub-images are synchronized to each other
before merging the sub-images.
[0021] According to an image composing apparatus and method of a
seventh invention, N sub-images are sequentially stored in N FIFO
storing means, and when the head of any one of the N sub-images
arrives at any one of the N FIFO storing means, an instruction to
output the stored sub-images in the order in which the sub-images
were stored is issued to the N FIFO storing means.
[0022] According to an image composing apparatus and method of an
eighth invention, the plurality of sub-image data have frame
structures which contain a priority information at the top of the
frame and a sub-image information at the end of the frame.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIG. 1 is a diagram showing the configuration of a
conventional image composing apparatus.
[0024] FIG. 2 is a diagram showing the configuration of a composed
image generating system using an image composing apparatus
according to the present invention.
[0025] FIG. 3 is a diagram showing the configuration of the image
composing apparatus according to the present invention.
[0026] FIG. 4 is a timing diagram for data transfer between the
image composing apparatus and node computers.
[0027] FIG. 5 is a sub-image output-timing diagram of the node
computers.
[0028] FIG. 6 is a diagram showing the configuration of a
synchronization circuit.
[0029] FIG. 7 is a diagram showing the configuration of a control
signal generating circuit.
[0030] FIG. 8 is a diagram showing the format of sub-image
data.
[0031] FIG. 9 is a bit allocation diagram for time slots.
[0032] FIG. 10 is a diagram for explaining a method of partitioning
space into subspaces.
[0033] FIG. 11 is diagram showing a binary space partitioning tree
representation.
[0034] FIG. 12 is a diagram for explaining an image blending
process.
[0035] FIG. 13 is a diagram showing the configuration of an image
merging circuit.
[0036] FIG. 14 is a diagram showing the configuration of a
multi-layer image composing apparatus.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0037] FIG. 2 is a diagram showing the configuration of a composed
image generating system using an image composing apparatus
according to the present invention. As shown, the composed image
generating system 2 comprises a server 20 which controls the entire
apparatus, a display device (for example, a CRT) 21 which displays
an image, a plurality of nodes (in the present embodiment, eight
nodes) 231 to 238 which generate sub-image signals for a plurality
of subspaces created by dividing the three-dimensional space in
which an analysis model is constructed, and the image composing
apparatus 24 which composes the outputs of the nodes 231 to 238 and
transmits a composed result to the server 20.
[0038] The server 20 comprises a CPU 201, a memory 202 which stores
a program to be executed by the CPU 201 and the result of
processing performed by the CPU 201, a graphics board (GB) 203
which outputs an image signal to the display apparatus 21, and an
interface board (IFB) 204 for interfacing with the image composing
apparatus 24.
[0039] The nodes 231-238 have an identical configuration, and each
node comprises a CPU 23b which performs simulation for the subspace
in which a portion of an analysis target is constructed, a memory
23b which stores a simulation program to be executed by the CPU 23b
and the simulation result performed by the CPU 23b, an image
generating engine board (VGB) 23c which generates an image
representing the result of the simulation for the subspace, and an
interface board (IFB) 23d for interfacing with the image composing
apparatus 24.
[0040] FIG. 3 is a diagram showing the configuration of the image
composing apparatus, according to the present invention, which
comprises a synchronizing section 240, a first-layer image
composing section 241, a second-layer image composing section 242,
a third-layer image composing section 243, and an image combining
circuit 244.
[0041] FIG. 4 is a data transferring timing diagram between the
image composing apparatus and the node computers. As shown, the
image composing apparatus 24 receives a parameter necessary for
image generation from the server and distributes the parameter to
the respective node computers 231-238 every predetermined period,
and each of the node computers 231-238 receives the parameter and
generates a sub-image.
[0042] After generating sub-images, the node computers 231-238
transfer the sub-images to the image composing apparatus 24, which
composes the sub-images output from the node computers 231-238 and
transfers the composed image to the display device 21 though the
server 20.
[0043] Because each of the node computers 231-238 generally works
independently, synchronization of the timings when the sub-images
arrive at the image composing apparatus 24 is not guaranteed.
[0044] FIG. 5 is a sub-image output timing diagram of the node
computers, and this shows a case where the first sub-image of #n
frame is output from the first node computer 231 and the last
sub-image of #n frame is output from the eighth node computer
238.
[0045] In this case, if each of the node computers 231-238 stores
the entire of #n frame, and begins to transfer the #n frame to the
first-layer image composing section 241 after the last part of the
#n frame output from the last node computer (in this example, the
eighth node computer 238) is stored, synchronization among the
sub-images can be achieved.
[0046] However, storing the entire of #n frame requires not only a
large capacity of memory, but also long time to store the entire of
#n frame.
[0047] Therefore, the image composing apparatus of the present
invention accomplishes not only synchronizing among sub-images, but
also shortening the synchronizing time and minimizing the memory
capacity, by providing a synchronizing section 240 at the interface
of the node computers, and beginning to transfer the frame of the
sub-image to the first-layer image composing section 241 at the
timing when the beginning parts of the sub-images frame output from
node computers are aligned.
[0048] As shown in FIG. 3, the synchronizing section 240 in the
image composing apparatus of the present invention comprises a
control signal generating circuit A and four synchronization
circuits B.sub.1-B.sub.4 which have identical configurations.
[0049] FIG. 6 is a diagram showing the configuration of each
synchronization circuit, and FIG. 7 is a diagram showing the
configuration of the control signal generating circuit.
[0050] As shown, the synchronization circuit B.sub.i has two
channels: the first channel comprises a FIFO memory 611 and a
command decoder 612 connected in parallel with the FIFO memory 611,
while the second channel comprises a FIFO memory 621 and a command
decoder 622 connected in parallel with the FIFO memory 621.
[0051] The first channel works as follows. The FIFO memory 611
sequentially stores the pixel data of the sub-image frame output
from the node computer connected to the first channel until READ
READY output from the control signal generating circuit A has been
received, and outputs the pixel data (I.sub.X) in the same order
when they were stored.
[0052] The command decoder 612 extracts a priority set (a channel
enable and a set priority) contained in the sub-image frame output
from the node computer connected to the first channel, and a frame
start command and a status sense contained in the frame data. The
start command is transferred to the control signal generating
circuit A and a 9-bit priority value (P.sub.X) contained in the set
priority is transferred to the first-layer image merging
section.
[0053] The operation of the second channel is the same as that of
the first channel, except that the pixel data output from the FIFO
memory 621 is I.sub.Y and the priority value is P.sub.Y output from
the command decoder.
[0054] FIG. 8 is a diagram showing the format of the sub-image
frame output from each node computer, and FIG. 9 is a bit
allocation diagram for time slots. Each of the frame computers
231-238 outputs a hardware initialization frame to initialize the
image composing apparatus at first, and then sequentially outputs
the sub-image frames.
[0055] The hardware-initializing frame contains a FIFO reset slot
and four dummy slots, and resets the FIFO memory in the
synchronization circuit.
[0056] The image frame comprises the priority set and frame data,
and the priority set contains a channel enable slot and a set
priority slot.
[0057] The channel enable slot indicates that the channel is in
use, and the set priority slot carries the priority given to the
sub-image generated by the node computer.
[0058] The frame data comprises a frame start slot, a status sense
slot, a predetermined number of pixel data slots, and a frame end
slot.
[0059] The frame start slot denotes the beginning of the frame
data, and the frame end slot denotes the end of the frame data.
[0060] Each of the pixel data slots stores the red, green, and blue
components and the transparency (.alpha. value) of each pixel in
the sub-image.
[0061] Each slot consists of 36 bits, which are allocated as shown
in FIG. 9 according to the kind of the slot.
[0062] For example, in the set priority slot, the priority is set
by using the lower 9 bits in No. 0-15 bits, and "4" is set in No.
24-31 bits and "2" in No. 32-35 bits to show that this slot is a
set priority slot.
[0063] Likewise, in the pixel data slot, "1" is set in No. 32-35
bits to show that this slot is a pixel data slot. Further, No.
24-31 bits store the red component, No. 16-23 bits store green
component, No. 8-15 bits store the blue component, and No. 0-7 bits
store the transparency.
[0064] The control signal generating circuit A shown in FIG. 7
comprises eight-input AND gate 7, and the frame start slots
extracted by the command decoders in the respective synchronization
circuits are transferred to the inputs of AND gate 7.
[0065] Then, when the eight frame start slots of #n frame are
detected, a FIFO read signal, that is, the output of the AND gate
7, becomes "ON", whereupon the frame data stored in the FIFO
memories in the synchronization circuits are read out in the same
order when they were stored, and are transferred to the first-layer
image composing section.
[0066] The pixel data are maintained in the FIFO memories until all
of the starting portions of the eight #n frames output from the
node computers 231-238 arrive at the synchronizing section. When
the starting portion of the eighth #n frame arrives at the
synchronizing section, the control signal generating circuit A sets
the FIFO read signal ON, and the data of the eight frames is
simultaneously transferred to the first-layer image merging section
241. The synchronization among the frame data is accomplished.
[0067] Since a single clock controls the image composing apparatus
24, synchronization is guaranteed in the processing after the
first-layer image merging section 241.
[0068] The first-layer image composing section 241 comprises four
image composing circuits C.sub.1-C.sub.4, the second-layer image
merging section 242 comprises two image composing circuits C.sub.5
and C.sub.6, and the third-layer image composing section 243
comprises one image merging circuit C.sub.7. The image composing
circuits C.sub.i (1.ltoreq.i.ltoreq.7) have identical
configurations.
[0069] In the first-layer image composing section 241, the first
image composing circuit C.sub.1 composes the sub-images generated
by the first node computer 241 and the second node computer 242
after being synchronized each other. Likewise, the sub-images
generated by the third node computer 243 and the fourth node
computer 244 are composed in the second image composing circuit
C.sub.2, the sub-images generated by the fifth node computer 245
and the sixth node computer 246 are composed in the third image
composing circuit C.sub.3, and the sub-images generated by the
seventh node computer 247 and the eighth node computer 248 are
composed in the fourth image composing circuit C.sub.4.
[0070] In the second-layer image composing section, the sub-images
output from the first image composing circuit C.sub.1 and the
second image composing circuit C.sub.2 are composed in the fifth
image composing circuit C.sub.5, while the sub-images output from
the third image composing circuit C.sub.3 and the fourth image
composing circuit C.sub.4 are composed in the sixth image composing
circuit C.sub.6.
[0071] In the third-layer image composing section, the sub-images
output from the fifth image composing circuit C.sub.5 and the sixth
image composing circuit C.sub.6 are composed by the seventh image
composing circuit C.sub.7.
[0072] Hereafter, the sub-image composing method to be employed in
the image composing apparatus of the present invention will be
described.
[0073] FIG. 10 is a diagram for explaining how an image space is
partitioned into eight subspaces V.sub.1 to V.sub.8. The sub-image
for the respective subspace V.sub.i is generated by each of the
node computers 231 to 238. The number of subspaces is not
specifically limited, but to make effective use of the image
merging circuits, it will be advantageous to divide the image space
into a plurality of subspaces, in particular, 2.sup.3n subspaces
(where n is a positive integer).
[0074] FIG. 11 is a binary space partitioning tree representation
of the subspaces, showing the arrangement of the subspaces Vi as
viewed from the viewpoint.
[0075] Because the image I.sub.1 corresponding to the subspace
V.sub.1 is closest to the viewpoint, priority "1" is assigned, and
other priorities are assigned in the order of the images I.sub.3,
I.sub.2, I.sub.4, I.sub.6, I.sub.8, I.sub.5 and I.sub.7. The
priority can be determined by discriminating the sign of
a.sub.mX.sub.e+b.sub.mY.sub.e+c.sub.mZ.sub.e+d.sub.m with respect
to the planes separating the respective subspaces. Here, (X.sub.e,
Y.sub.e, Z.sub.e) are the coordinates of the viewpoint, and
(a.sub.m, b.sub.m, c.sub.m, d.sub.m) are the coefficients
determined according to the planes separating the respective
subspaces.
[0076] FIG. 12 is a diagram for explaining how the sub-images
I.sub.1 to I.sub.8 are composed. The eight sub-images I.sub.1 to
I.sub.8 can be composed by iteratively composing two sub-images in
consideration of the fact that higher priority is given to the
sub-images closer to the viewpoint.
[0077] According to the image composing apparatus of the present
invention, each sub-image is given priority instead of the Z value,
and image composing circuits for composing two sub-images in
consideration for the priority are arranged in a layered structure
to obtain high-speed image composition and high expandability.
[0078] FIG. 13 is a diagram showing the configuration of each image
composing circuit C.sub.i, which comprises a comparator 131, a
resistor 132, an interchanger 133, a composer 134, and a delay
135.
[0079] The comparator 131 compares the two priority values P.sub.X
and P.sub.Y transferred from the synchronization circuit or the
image merging circuits at the preceding stage, controls the
interchanger 133 based on the result of the comparison, and outputs
the smaller priority value (higher priority) as P.sub.Z through the
resistor 132.
[0080] Based on the result of the comparison from the comparator
131, the interchanger 133 interchanges the two pixel data I.sub.X
and I.sub.Y transferred from the synchronization circuit or the
image merging circuits at the preceding stage.
[0081] For example, when the value of the set priority P.sub.Y for
the sub-image I.sub.Y is smaller than the value of the set priority
P.sub.X for the sub-image I.sub.X, that is, when the sub-image
I.sub.Y is given higher priority, cross paths are selected, and the
sub-images I.sub.X and I.sub.Y are set as follows.
[0082] I.sub.Y.fwdarw.I.sub.A
[0083] I.sub.X.fwdarw.I.sub.B
[0084] Conversely, when the value of the set priority P.sub.Y for
the sub-image I.sub.Y is larger than the value of the set priority
P.sub.X for the sub-image I.sub.X, that is, when the sub-image
I.sub.X is given higher priority, then straight paths are selected,
and the sub-images I.sub.X and I.sub.Y are set as follows.
[0085] I.sub.X.fwdarw.I.sub.A
[0086] I.sub.Y.fwdarw.I.sub.B
[0087] The composer 134 generates composed pixel data I.sub.Z by
composing the two pixel data I.sub.A and I.sub.B in accordance with
the composing equation shown below. I .times. .times. ( R , G , B )
z = I .times. .times. ( R , G , B ) A + I .function. ( .alpha. ) A
* + I .times. .times. ( R , G , B ) B I .times. .times. ( .alpha. )
z = I .times. .times. ( .alpha. ) A * I .times. .times. ( .alpha. )
B ##EQU2## where I(R,G,B).sub.Z is the red, green, and blue
component data of the composed pixel data I.sub.Z, and
I(.alpha.).sub.Z is the transparency of the composed pixel data
I.sub.Z.
[0088] Finally, the composite pixel data I.sub.Z is generated by
storing I(R,G,B).sub.Z in No. 31-8 bits and I(.alpha.).sub.Z in No.
7-0 bits, and is output.
[0089] The high four bits of the 36-bit pixel data are set to "1"
for denoting that the data is pixel data, and the bits to be
processed by the interchanger 133 and the composer 134 are the low
32 bits. Therefore, the high four bits are directly transferred
through the delay 135 to the output side of the composer 134 and
combined with the output of the composer 134 to reproduce the
36-bit pixel data. The delay time of the delay is set equal to the
processing time required in the interchanger 133 and the composer
134.
[0090] As described above, the seven image composing circuits are
arranged in three layers and the eight sub-images are composed to
one image.
[0091] However, as the pixel data and the priority value are
separately processed in each image composing circuit in the image
composing circuit in the first-layer-third-layer, the pixel data
and the priority value are also separately output from the image
composing circuit C.sub.7 in the third-layer image composing
section 243.
[0092] Therefore, to standardize the configuration of the image
composing apparatus of the present invention, the image combing
circuit 244 (FIG. 3) arranged at the final stage of the image
composing apparatus adds the frame start and the frame sense at the
head of the pixel data output from the image merging circuit
C.sub.7 and the frame end at the tail of the data to reconstruct
the data format shown in FIG. 8. Further, the priority set
determined based on the priority value output from the image
merging circuit C.sub.7 is added in the front of the frame
data.
[0093] By applying the above configuration, the image composing
apparatus of the present invention (in the above embodiment, the
apparatus for composing eight sub-images into one image) produces
the output frame of the same format as the input frame, and it
becomes possible to increase the number of images to be composed by
arranging the above image composing apparatuses in a layered
structure.
[0094] FIG. 14 is a configuration of a multi-layer sub-image
composing apparatus constructed by arranging 8-input and 1-output
image composing apparatuses in a layered structure. When the number
of sub-images to be input is denoted by N, the number of layers S
is given by the following equation. S=Ceil(log.sub.2N)
[0095] While the above description has dealt with an image
composing apparatus for composing sub-images electrically, a
plurality of display devices may be arranged side by side and the
sub-images may be composed visually by displaying the outputs of
the synchronizing section directly on the respective display
apparatuses and thus operating the plurality of display devices as
a single display apparatus.
[0096] According to the image composing apparatus and method of the
present invention, as the sub-images are composed based on the
occlusion relationship between them, it becomes possible to easily
cope with an increase in the number of sub-images to be merged.
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